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A large variety of new applications for Internet of Things (IoT), Industrie 4.0 and other consumer products are pushing volume and manufacturing of microelectromechanical systems (MEMS) into a new phase. Due to massive use of these sensors and actuators in mobile and industrial applications smaller systems combined with low power consumption and higher versatility are required. MEMS are transducers that sense or control physical, chemical or optical quantities creating devices for applications in the area of 3D-motion tracking, pressure sensing, light shaping or detection of irradiation. The combination of MEMS with an application specific integrated circuit (ASIC) based on CMOS technology enables the entire system to interact with outside world. These ASICs are providing required features such as analog-to-digital conversion, amplification, filtering, information processing and storage as well as communication to the outside world. There are different solutions available to combine MEMS with customized CMOS circuits. One choice known as system-in-package (SiP) is the manufacturing of MEMS and CMOS on separate wafers and its subsequent integration in a multi-chip module using interposer/ rewiring technologies. Key advatanges of this technique are high flexibility, high modularity and a complete decoupled manufacturing of CMOS and MEMS. This enables a rapid development and leads to low development costs. And, there is no impact of different sizes between CMOS and MEMS chip. In order to enhance the integration density, to drive system feature size down, to suppress potential parasitic capacitances and to reduce power consumption an integrated manufacturing on the same substrate is a must and known as system-on-chip (SoC) solution. On one hand this approach can be still realized by a multi-wafer processing and a final integration using bonding technologies. This technology is often named as heterogeneous integration. Key advantage of multi-wafer technology is the possibility to use high-performance MEMS materials such as monocrystalline silicon as actuation/sensing material and its integration on CMOS wafers. Disadvantages are the required alignment accuracies when using a metallic bond or limitation for integration densities when using via-last approach. A more consistent way is a complete monolithic integration of MEMS on CMOS substrates. Especially when large transducer arrays are required (e.g. bolometers, micro-mirror arrays, CMUT arrays) a monolithic integration of MEMS on CMOS is the best solution. All advantages are now on hand – high integration densities, low parasitic capacitances and an effective usage of CMOS area. Fraunhofer IPMS applies surface and bulk micromachining technologies for the integration of MEMS on customized CMOS backplanes. To reduce development costs and time-to-market IPMS combines standard CMOS processes offered from CMOS foundries with a subsequent integration of MEMS part in our MEMS fab. Due to the application specific design of the CMOS backplane this concept allows a perfect match between ASIC and MEMS functionalities. In a typical project flow CMOS and MEMS will be manufactured and tested in parallel to shorten development time. After ASIC design is finished it will be tested using Multi- Project- Wafer run (MPW) in a CMOS foundry. Using these MPW runs a complete characterization of CMOS functionality can be realized in an early project state at low costs. Parallel to CMOS testing an entire process development of MEMS part can be done on passive devices in our MEMS fab. If CMOS and MEMS characterization is completed the MEMS part will be monolithically integrated on these customized CMOS backplanes. But there are still some challenges for the integration of MEMS on foundry fabricated CMOS backplanes, e.g.: Modifications of last CMOS/ interconnect/ ILD layers to realize an appropriate interface to MEMS Clarification of PCM (process control monitoring) test environment, depth of test structures and possible arising contamination issues In-chip surface topology after interconnect processing to define necessary actions to achieve required planarity for further processing Tuning mix-and-match lithography to achieve high overlay accuracies (Picture 1: Reached overlay accuracy between last 0,18µm CMOS and first MEMS layer of about 30- 40nm after correction step using i-line stepper) Required chip design features when using sacrificial layer technology IPMS offers a wide range of surface and bulk micromachining technologies which are particularly suitable for the fabrication of sensors and actuators on pre-fabricated CMOS wafers using monolithic integration. Especially surface micromachining using inorganic sacrificial layer technology allows the realization of rather complex MEMS structures on CMOS backplanes. Based on examples such as spatial light modulators (SLM) and capacitive micromachined ultrasonic transducers (CMUT) we will present solutions for the integration of surface micromachined MEMS on customized CMOS substrates. Figure 1

We developed a novel 512 x 320 tip-tilt micro mirror array (MMA) together with the entire related technology platform, including mirror fabrication process, integrated CMOS address circuitry and external drive electronics. The MMA itself consists of 2axis-tip-tilt actuators at 48μm pixel size, allowing a continuous pure tip-tilt motion up to 3.5° in arbitrary directions, fully calibratable at standard deviations of better than 0.025°. The mirrors are realized within a 2-level architecture defined by three structural layers, two for hinge and reinforcement suspension and one for the overlying mirror. They are fabricated by surface-micromachining within a fully CMOS compatible process. MMA programming is accomplished by an underlying CMOS backplane supporting drive voltages up to 27V and frame rates up to 3.6kHz.

We have developed a novel $\mathbf{512\ x\ 320}$ micro mirror array consisting of 2axis-tip-tilt actuators with $\mathbf{48}\mu\mathbf{m}$ pixel size, allowing a continuous, pure tip-tilt motion up to 3.5° in arbitrary directions, fully calibratable with standard deviations of better than 0.025°. The device is realized in a fully CMOS compatible process with an underlying integrated address circuitry.

In this paper, the feasibility of a large area exposure for the manufacturing of a NIL master (silicon wafer) dealing with a long writing time is shown. Fraunhofer CNT succeeded in a 355h exposure with a variable shaped e-beam using a commercially available positive tone chemically amplified resist. The wafer has been evaluated in terms of resist contrast and stability, CD uniformity, linearity, pattern quality and defectivity. Electron beam tool parameters like Wehnelt voltage and stage temperature have been analyzed. Different writing strategies and concepts will be considered to optimize the exposure and minimize stitching error defects.

A dual hard mask concept for high resolution patterning has been evaluated with focus on highly selective etching processes for semiconductor manufacturing. The integration of thin SiO2 and ZrO2 hard mask materials enables highly selective patterning via plasma etch processes for future technology nodes. The patterning sequence is demonstrated for hole arrays with sizes down to 25 nm using a 50 nm thin resist which leads to the fabrication of trenches in silicon with aspect ratios up to 20:1. Alternative ZrO2 based materials were investigated with focus on surface roughness reduction since it influences the final line edge roughness (LER). Here Si-doped ZrO2 (ALD) was compared to the undoped and crystalline ZrO2 as main selective material.

The application of phasefluid based intelligent fluids® in the field of photoresist stripping was studied. Due to their highly dynamic inner structure, phasefluids penetrate into the polymer network of photoresists and small gaps between resist layer and substrate and lift off the material from the surface. These non-aggressive stripping fluids were investigated regarding their efficiency in various resist stripping applications including initial results on copper metallization. Furthermore intelligent fluids® have been evaluated on an industry standard high volume single wafer cleaner. A baseline process on 300 mm wafers has been developed and characterized in terms of metallic and ionic impurities and defect level. Finally a general proof of concept for removal of positive tone resist from 300 mm silicon wafers is demonstrated.

Electron optics can assist in the fabrication of semiconductor devices in many challenges that arise from the ongoing decrease of structure size. Examples are augmenting optical lithography by electron beam direct write strategies and high-throughput imaging of patterned structures with multiple beam electron microscopes. We use multiple beam electron microscopy to image semiconductor wafers processed by electron beam lithography.

The fabrication of high aspect ratio silicon trenches (critical dimension < 100 nm, aspect ratio > 10:1) by dry etch processing has proven to be a challenge mainly due to limited etch selectivity of conventional hardmask materials to Si. Moreover, for future technology nodes the hardmask thickness will be limited by the thickness of the photoresist. This work focuses on a concept to enable the usage of very thin resist layers (< 100 nm) for patterning of silicon trenches by the integration of an unconventional hardmask stack consisting of SiO2 and ZrO2. Deposition of such material films has been investigated, as well as e-beam lithography exposure and finally pattern transfer by dry etching. Using this hardmask stack and 100 nm thin resist, the fabrication of 35 nm wide trenches with an aspect ratio of ~ 20:1 is demonstrated revealing a very high selectivity (> 100:1) of the ZrO2 layer to Si during the deep silicon etch. A silicon etch rate > 1.5 µm/min was achieved. The ZrO2 layer itself provides the main selectivity improvements of the final hardmask stack.

To realize fast and efficient integrated circuits the interconnect system gains an increasing importance. In particular, this is the case for logic and processor circuits with up to 12 metallization layers. In order to optimize this technology and the according processes it is desirable to generate flexible test structures in small lot production. In opposition to standard optical lithography using masks, Electron Beam Direct Write (EBDW) lithography can rapidly deliver special test structures at low cost. Furthermore, critical dimensions of future technology nodes which are not yet manufacturable by standard optical lithography tools can be produced. In this paper we demonstrate the potential of the 50kV variable shaped EBDW cluster for patterning of future back-end-of-line (BEOL) structures on full 200mm wafers. The patterned wafers have been used to develop next generation copper damascene interconnect processes for critical dimensions down to 50nm.

Along with the introduction of the 32nm technology node in the next years, the methods for correcting the proximity effect face certain limitations of measurement performance and the underlying point spread function based models themselves. To extend these methods to future technology nodes, they have to rely on more generalized coherences between nominal and measured feature sizes than just the absolute measurement values. In this work, a method is introduced to determine the forward scattering range and backward scattering ratio by printing isolated lines with various line widths and pre-assigned variable exposure doses. The line widths are then measured using standard inline scanning electron microscopy and correlated to their nominal values. This is done in terms of linearity to find the best match between the input parameters of the methodology and the intrinsic values of the resist-substrate system. A comparison between simulated and experimental results conclude that significant line width nonlinearities will occur, when relying on conventional methodologies especially for feature sizes below 40nm.

Electron beam direct write (EBDW) provides high resolution for device and technology development. A new variable shaped beam system with improved electron optics was introduced, which features the capability for the 32nm node. Because of the limited resolution of commercially available chemically amplified resists at this node, it is important to determine a stable and optimum resist process window. To compare a process window under different premises, a universally applicable and low error-prone method is needed. The isofocal dose method is investigated with regard to these properties for its use in EBDW. Experiments were performed on 50kV variable shaped electron beam direct writers using the new electron-optical column SB3050 DW (Vistec Electron Beam GmbH). Exposures are performed at different sites in Dresden (Fraunhofer CNT/Qimonda Dresden), Jena (Vistec) and Stuttgart (IMS Chips); also patterns are exposed on different layer stacks at one site. The strong need for a process window can be fulfilled by the isofocal dose method, which will be shown by contour plots.

Electron beam direct write (EBDW) with a variable shaped beam writer can be applied for very low volume applications like prototyping and personalization. Together with Infineon Technologies, the Center of Competence E-Beam Lithography of Qimonda in Dresden has demonstrated the integration of an E-Beam written back end of line metal layer into a productive 220nm node microcontroller fabrication process. For this purpose an electron beam lithography unit process was developed, and all necessary steps like data prep, proximity correction, alignment and overlay processes and etching processes were reviewed. Several test wafers have been completed in fabrication and measured electrically. At first go, full electrical functionality with a yield >70% could be demonstrated.

When using electron beam direct write for patterning, resist selection (positive or negative) plays an important role. This is because writing time for shaped beam machines is proportional to the mean density of exposed shapes. There is an optimum with respect to writing time when using either the direct exposure or the complementary exposure with reversed resist tonality. Switching from positive to negative resist or vice versa has an impact on writing time. In this paper, we derive the fundamental differences on CD accuracy when using direct or complementary exposure, which is given by the local registration error. Additionally, a simple method is developed to measure this local registration error by simple CD SEM measurement of 1:1 line/space patterns.

A sensitivity analysis (SA) algorithm was developed and tested to comprehend the influences of different test pattern sets on the calibration of a point spread function (PSF) model with complementary approaches. Variance-based SA is the method of choice. It allows attributing the variance of the output of a model to the sum of variance of each input of the model and their correlated factors. 1 The objective of this development is increasing the accuracy of the resolved PSF model in the complementary technique through the optimization of test pattern sets. Inscale® from Aselta Nanographics is used to prepare the various pattern sets and to check the consequences of development. Fraunhofer IPMS-CNT exposed the prepared data and observed those to visualize the link of sensitivities between the PSF parameters and the test pattern. First, the SA can assess the influence of test pattern sets for the determination of PSF parameters, such as which PSF parameter is affected on the employments of certain pattern. Secondly, throughout the evaluation, the SA enhances the precision of PSF through the optimization of test patterns. Finally, the developed algorithm is able to appraise what ranges of proximity effect correction is crucial on which portion of a real application pattern in the electron beam exposure.

Further work is described on a new generation of more transparent, 157 nm resist platforms, which are based upon capping of fluoroalcohol-substituted, transparent perfluorinated resins (TFR) with a tert-butoxycarbonylmethyl (BOCME) moiety. By optimizing both resin structure and loading of photoacid generator and base additive a good compromise can achieved between resolution power, dark erosion resistance, sensitivity and transparency at 157 nm. In this manner, resist systems with a transparency as low as 0.87 AU/micron were designed capable of resolving 55 nm 1:1 features, at a dose of 92 mJ/cm2 using a phase shift mask on a Exitech 157 nm small field mini-stepper. Also, these have been imaged with a larger field tool (DUV30 Micrascan VII) to give 80 nm 1.1.5 L/S features at a dose of 135 mJ/cm2 employing using a Binary mask. A description is also given of our work on 193 nm/immersion lithography. Specifically, the effects of changing resist compoents such as PAG and Base content will be discussed. Also, a description of the utility of a protective base soluble barrier coat will be given.

The concept of Main Chain Scission of photoresist polymers (MCS) is used to reducing the influence of molecular dimensions on the quality of photoresist patterns. Independent from the wavelength or lithography technique, the concept will raise in relevance as critical dimensions approach molecular dimensions. After the introduction of the MCS concept on last years conference of photopolymer science and technology, initial results are given in this paper to verify this concept.[1] Starting with polymer synthesis, after optimization of resist formulation and process conditions, ebeam patterns with the MCS resist and a commercial ebeam resist were generated. The patterns were compared with respect to their roughness. It was found, that lines printed in the MCS resist show a significant lower LER than the same patterns in the ebeam resist.

Many efforts were spent in the development of EUV technologies, but from a customer point of view EUV is still behind expectations. In parallel since years maskless lithography is included in the ITRS roadmap wherein multi electron beam direct patterning is considered as an alternative or complementary approach for patterning of advanced technology nodes. The process of multi beam exposures can be emulated by single beam technologies available in the field. While variable shape-beam direct writers are already used for niche applications, the integration capability of e-beam direct write at advanced nodes has not been proven, yet. In this study the e-beam lithography was implemented in the BEoL processes of the 28nm SRAM technology. Integrated 300mm wafers with a 28nm back-end of line (BEoL) stack from GLOBALFOUNDRIES, Dresden, were used for the experiments. For the patterning of the Metal layer a Mix and Match concept based on the sequence litho - etch - litho – etch (LELE) was developed and evaluated wherein several exposure fields were blanked out during the optical exposure. E-beam patterning results of BEoL Metal and Via layers are presented using a 50kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer IPMS-CNT. Etch results are shown and compared to the POR. In summary we demonstrate the integration capability of EBDW into a productive CMOS process flow at the example of the 28nm SRAM technology node.

The usage of phase fluid based stripping agents to remove photoresists from silicon substrates was studied. Photoresists are required for many silicon based technologies such as MEMS patterning, 3D-Integration or frontend and backend of line semiconductor applications [1]. Although the use of resists is very common, their successful integration often depends on the ability to remove the resist after certain processing steps. On the one hand the resist is changing during subsequent process steps that can cause a thermally activated cross-linking which increases the stripping complexity. Resist removal is also challenging after the formation of a hard polymer surface layer during plasma or implant processes which is called skin or crust [2]. On the other hand the choice of stripping chemistry is often limited due to the presence of functional materials such as metals which can be damaged by aggressive stripping chemistries [3].

A new correction technique has been developed not only to reduce the corner rounding, but also to restrain the building up of shot counts that is able to increase the exposure time in electron beam (e-beam) lithography. It is able to prove the developed corner rounding correction technique is useful with high accuracies throughout the simulation of several different types of correction in the data preparation software, Inscale® from Aselta Nanographics, and its comparisons with exposure images. The developed one is helpful to suppress the accumulation of shot counts either. Furthermore, it shows the general limit of corner rounding correction in a conventional variable shaped beam exposure tool with current resist process. Firstly, we are demonstrating the new method for correcting the corner rounding that either can avoid the extension of exposure shot counts, called writing time. Secondly, this study reveals the current bounds of corner rounding correction, especially the lithography employing the shaped beam tool. Finally, we propose the criteria of data preparation for the corner rounding in e-beam lithography, specifically upcoming 18nm technology node and practical applications.

We present a theoretical analysis and experimental evidences of metasurfaces based on particle resonators that achieve bright-field colour prints. We created pixels that support individual colours, miniaturized and juxtaposed at the optical diffraction limit. Different strategies are followed to offer the flexibility of using both transmitting and epi (reflective) white light sources. We discuss their potential applications in large-volume colour printing via nanoimprint lithography.

The usage of phasefluid based stripping agents to remove photoresists from silicon substrates was studied. Due to their highly dynamic inner structure phasefluids offer a new working principle, they are penetrating layers through smallest openings and lift off the material from the surface. These non-aggressive stripping fluids were investigated regarding their cleaning efficiency as well as contamination behavior to enable usage in semiconductor and MEMS manufacturing. A general proof of concept for the usage of phasefluids in resist stripping processes is shown on silicon coupons and BKM’s are given for different resist types. In addition a baseline process on 12inch wafers has been developed and characterized in terms of metallic and ionic impurities and defect level.

Organic photorefractive materials have attracted a lot of interest recently. Their optical response times of a few milliseconds, however, are not yet adequate for the desired commercial applications. We present an investigation on the correlation between the optical response time and photoelectric quantities, such as the hole mobility and the dispersivity of charge carrier transport.

We report on photoelectric and holographic investigations of an organic photorefractive material based on a low molar mass glass with both photoconductive and nonlinear optical properties. By implementing a suitable plasticizer we obtained a composite system which shows extremely fast initial response times down to 450 μs at writing beam intensities of Iwrite = 10.8 W/cm2 and 2.5 ms at the canonical intensity of Iwrite = 1 W/cm2. Furthermore, high refractive index modulations up to Δn = 6.1 × 10-3, long lifetimes and high optical quality of the samples are observed. In comparison to a second similar composite system, which was plasticized by a more polar dopand, we demonstrate the crucial role of this functional constituent on the photoelectric properties. Time-of-flight measurements show a major impact of the plasticizer on the dispersivity of charge-carrier transport. Subsequently the buildup and decay dynamics of the photorefractive grating are substantially affected. Holographic time-of-flight measure...

Photorefractive organic systems presently show much longer response times than their inorganic counterparts. The origin of this limitation is not yet fully understood. We present a detailed investigation of the photoelectric processes involved in the photorefractive effect, namely charge generation and charge transport. A comparison between conventional (TOF) and holographic time-of-flight (HTOF) experiments, which were used to determine the charge carrier mobility, is presented. The mobility determined by TOF is shown to depend on the sample thickness. The results show that charge carrier generation and transport are not the limiting factors for the cw-response time of holographic experiments on this system.

We present a detailed study of the photoelectric as well as the holographic properties of a novel organic photorefractive glass based on triphenylamine. We studied the quantum efficiency Φ of the photogeneration of charges by means of photoinduced discharge measurements. The photoconductivity σ and the charge carrier mobility μ were obtained via dc photoconduction and pulsed time-of-flight experiments, respectively. The holographic characterization was performed by two-wave and degenerate four-wave mixing experiments allowing for the determination of properties such as diffraction efficiency η, modulation of the refractive index Δn, gain coefficient Γ, and phase-shift φp of the investigated system. The experimental data for Φ could be successfully described by the Onsager formalism with a thermalization radius of r0=24 A and a primary quantum yield of Φ0=40%. We evaluated the E field and temperature-dependent measurements of μ using the Bassler formalism yielding a width of the density of states of σ=0.13 eV and a disorder parameter Σ=3.6. On this basis the lifetime and the average drift length of the charge carriers could be estimated from the dc photoconduction experiments. From the photoelectric measurements we also calculated the holographic response time that matched very well to the measured response time and described the E-field dependence satisfactorily. The presented photorefractive system shows outstanding optical properties and stability with respect to degradation. We measured a gain coefficient of Γ=90 cm-1, and a diffraction efficiency of η=27% at a response time of 30 ms for only 40-μm-thick samples. Orientational enhancement was observed and evaluated quantitatively. To our knowledge, this work presents the first determination of each of the above quantities all in one single organic photorefractive material.

A novel organic photorefractive composite system is presented consisting of the amorphous multifunctional low-molar mass compound DR1-DCTA, doped with C 60 as sensitizer and diisooctyl phthalate (DOP) as plasticizer. DR1-DCTA, a carbazole substituted triphenylamine with a covalently attached nonlinear optical azo chromophore unit has been synthesized in a 4 step reaction. The compound forms a stable glass. Its thermal, optical and electrochemical properties are discussed. Holographic experiments (2BC, DFWM) of the photorefractive composite exhibit a fast response time in the range of only 30 ms and a maximum gain coefficient of 90 cm –1 .

A variety of new functional materials based on triarylamines, such as low molecular weight glasses which possess hole conducting/photoconductive properties as well as amorphous bifunctional materials which combine photoconductive and non-linear optical (NLO) properties in one compound, have been synthesized. The new hole transporting glasses belong to the class of 1,3,5-tris(triaryldiamino)benzenes (TTADB). The hyperbranched structure and the large aryl groups attached as substituents lead to high glass transition temperatures (Tg) of up to 141°C in these compounds. The TTADBs do not recrystallize upon cooling from the melt, but form stable glasses. Cyclic voltammetry studies reveal multi-oxidation stages for these compounds of which the first oxidation is reversible. The HOMO energy values determined from CV for TTADB-1 and TTADB-2 are -4.82 and -4.94 eV, respectively. Light emitting diodes with the structure ITO/TTADB-2/Alq3/Al (where ITO=indium tin oxide) show high efficiency and large current carrying capacity. Further, bifunctional compounds have been synthesized in which a photoconductive moiety such as bis(carbazolyl)triphenylamine or bis(diphenylamino)triphenylamine is covalently bound to different NLO chromophores. Some of these compounds are thermally and morphologically stable amorphous materials, possessing Tg in the range from 85 to 122°C. Cyclic voltammetry measurements reveal that the HOMO energy values are between -4.81 and -5.45 eV. In photorefractive measurements using 40 µm thick samples, a diffraction efficiency of 27%, which corresponds to a refractive index modulation (Δn) of 3.5×10-3, a maximum two beam coupling gain coefficient (Γ) of 90 cm-1 and a response time of 40 ms were obtained.

Proximity Effects in electron beam lithography impact feature dimensions, pattern fidelity and uniformity. These effects are addressed using a mathematical model representing the radial exposure intensity distribution induced by a point electron source, commonly named as the Point Spread Function (PSF). PSF models are usually employed for predicting and compensating for effects up to 15μm. It is well known that there are also some process related phenomena that impact pattern uniformity that have a longer range, namely CMP effects, fogging, etc. Performing proximity effects corrections can result in lengthy run times as file size and pattern densities continue to increase exponentially per technology node. Running corrections for extreme long range phenomena becomes computational and file size prohibitive. Nevertheless, since extreme long range may reach up several millimeters, and new technology nodes require a high level of precision, a strategy for predicting and compensating these phenomena is crucial. In this paper a set of test patterns are presented in order to verify and calibrate the so called extreme long range effects in the electron beam lithography. Moreover, a strategy to compensate for extreme long range effects based on the pattern density is presented. Since the evaluation is based on a density map instead of the actual patterns, the computational effort is feasible. The proposed method may be performed off-line (in contrast to machine standard in-line correction). The advantage of employing off-line compensation relies on enhancing the employ of dose and/or geometry modulation. This strategy also has the advantage of being completely decoupled from other e-beam writer’s internal corrections (like Fogging Effect Correction - FEC).

In electron proximity effects correction (PEC), the quality of a correction is highly dependent on the quality of the model used to compute the effects. Therefore it is of primary importance to have a reliable methodology to extract the parameters and assess the quality of a model. Usually, model calibration procedures consist of one or more cycles of exposure and measurements on the calibration stage. The process and metrology variability may play a key role in the quality of the final model and, hence, of the PEC result. Therefore, it is important to determine at which level these variations may impact a calibration procedure and how a calibration design may be implemented in order to enable more robustness to the resulting model. In this work, metrology variability was evaluated by measuring the same wafer using two different CD-SEM tools. The information coming from these analyses was used as reference to a variation induced calibration test using synthetic data. By inserting variability in synthetic data it was possible to evaluate its impact on the resulting parameter values and in the final model error evaluation.

This paper focuses on the scaling and optimization of metal-isolator-metal capacitors integrated in 3D Si structures. Scaling to high capacitance density is aimed by the use of high-k dielectrics and a significant area enhancement realized through silicon pattering with increasing aspect ratios. By material and process optimization the capacitors show excellent IV and CV characteristics with high temperature and reliability performance independently of the 3D structure. A fully functional capacitor of 4mm2 consisting of 80 Mil trenches with an overall capacitance of 850nF can be demonstrated.

This paper focuses on zirconia and TiN based metal-isolator-metal capacitors integrated in immediate vicinity to the Si substrate. A high capacitance density is aimed by significant area enhancement realized through silicon pattering. By material optimization the capacitors also withstand higher supply voltages and show excellent temperature and reliability performance independently of the 3D structure.

A dual hard mask concept for high resolution patterning has been evaluated with focus on highly selective etching processes for semiconductor manufacturing. The integration of thin SiO2 and ZrO2 hard mask materials enables highly selective patterning via plasma etch processes for future technology nodes. The patterning sequence is demonstrated for hole arrays with sizes down to 25 nm using a 50 nm thin resist which leads to the fabrication of trenches in silicon with aspect ratios up to 20:1. Alternative ZrO2 based materials were investigated with focus on surface roughness reduction since it influences the final line etch roughness. Here Si-doped ZrO2 (ALD) and spin-coatable ZrO2 were compared to the pure and crystalline ZrO2 as main selective material.

Resist processing for future technology nodes becomes more and more complex. The resist film thickness is getting thinner and hardmask concepts (trilayer) are needed for reproducible etch transfer into the stack. Additional layers between resist and substrate are influencing the electron scattering in e-beam lithography and may also improve sensitivity and resolution. In this study, bare silicon wafers with different assisting underlayers were processed in a 300 mm CMOS manufacturing environment and were exposed on a 50 keV VISTEC SB3050DW variable-shaped electron beam direct writer at Fraunhofer CNT. The underlayers are organic-inorganic hybrid coatings with different metal additives. The negative-tone resist was evaluated in terms of contrast, sensitivity, resolution and LWR/LER as a function of the stack. The interactions between resist and different assisting underlayers on e-beam direct writing will be investigated. These layers could be used to optimize the trade-off among resolution, LWR and sensitivity in future applications.

While significant resources are invested in bringing EUV lithography to the market, multi electron beam direct patterning is still being considered as an alternative or complementary approach for patterning of advanced technology nodes. The possible introduction of direct write technology into an advanced process flow however may lead to new challenges. For example, the impact of high-energy electrons on dielectric materials and devices may lead to changes in the electrical parameters of the circuit compared to parts conventionally exposed by optical lithography. Furthermore, degradation of product reliability may occur. These questions have not yet been clarified in detail. For this study, pre-structured 300mm wafers with a 28nm BEOL stack were dry-exposed at various processing levels using a 50kV variable shaped e-beam direct writer. The electrical parameters of exposed structures were compared to non-exposed structures. The data of line resistance, capacitance, and line to line leakage were found to be within the typical distributions of the standard process. The dielectric breakdown voltages were also comparable between the splits, suggesting no dramatic TDDB performance degradation. With respect to high-k metal gate transistor parameters, a decrease in threshold voltage shift sensitivity was observed as well as a reduced sensitivity to hot carrier injection. More detailed investigations are needed to determine how these findings need to be considered and whether they represent a risk for the introduction of maskless lithography into the process flow of advanced technology nodes.

To fulfill the requirements of future technology nodes new resists with high resolution, high sensitivity and low LWR and LER respectively are needed. A new inorganic non-chemically amplified resist (XE15IB, an experimental resist provided by Inpria Corp.) was investigated. The resist is spin-cast from aqueous solution and is based on hafnium oxide. Metal oxide based resist as XE15IB supersede other resist materials due to its high etch resistance. 1, 2 This new material can be considered as a direct patternable spin on hard mask. XE15IB was processed in a 300mm complementary metal oxide semiconductor (CMOS) manufacturing environment and exposed on a 50 kV VISTEC SB3050DW variable shaped electron beam direct writer at Fraunhofer Center Nanoelectronic Technologies (CNT). The resist was evaluated in terms of contrast, sensitivity and resolution. The process characteristics required for CMOS manufacturing such as delay stability were also examined. Furthermore, by printing a large static random access Memory (SRAM) pattern (design CD of 22 nm), the exposure of a real application pattern was demonstrated.

Using electron beam direct write (EBDW) as a complementary approach together with standard optical lithography at 193nm or EUV wavelength has been proposed only lately and might be a reasonable solution for low volume CMOS manufacturing and special applications as well as design rule restrictions. Here, the high throughput of the optical litho can be combined with the high resolution and the high flexibility of the e-beam by using a mix & match approach (Litho- Etch-Litho-Etch, LELE). Complementary Lithography is mainly driven by special design requirements for unidirectional (1-D gridded) Manhattan type design layouts that enable scaling of advanced logic chips. This requires significant data prep efforts such as layout splitting. In this paper we will show recent results of Complementary Lithography using 193nm immersion generated 50nm lines/space pattern addressing the 32nm logic technology node that were cut with electron beam direct write. Regular lines and space arrays were patterned at GLOBALFOUNDRIES Dresden and have been cut in predefined areas using a VISTEC SB3050DW e-beam direct writer (50KV Variable Shaped Beam) at Fraunhofer Center Nanoelectronic Technologies (CNT), Dresden, as well as on the PML2 tool at IMS Nanofabrication, Vienna. Two types of e-beam resists were used for the cut exposure. Integration issues as well as overlay requirements and performance improvements necessary for this mix & match approach will be discussed.

Two inorganic non-chemically amplified resists (XE15CB and XE15IB) were investigated. The resists are based on hafnium oxide sulfate and spin-cast from aqueous solution. They differ in sensitivity and resolution. In contrast to other studies, the materials were coated for the first time on 300 mm wafers and exposed on a 50 kV VISTEC SB3050DW variable shaped electron beam direct writer in a near-production environment at Fraunhofer CNT. In this paper, the evaluation of this resist family and its feasibility for production will be discussed. The resists were evaluated in terms of contrast, sensitivity and resolution. The process characteristics required for CMOS manufacturing such as delay stability were also examined. Furthermore, by exposing a large SRAM pattern (design CD of 22 nm), the exposure of a real application pattern was demonstrated.

A new correction approach was developed to improve the process window of electron beam lithography and push its resolution at least one generation further using the same exposure tool. An efficient combination of dose and geometry modulation is implemented in the commercial data preparation software, called Inscale®, from Aselta Nanographics. Furthermore, the electron Resolution Improvement Feature (eRIF) is tested, which is based on the dose modulation and multiple-pass exposure, for not only overcoming the narrow resist process windows and disability of exposure tool but also more accurate correction of exposure data in the application of sub-35nm regime. Firstly, we are demonstrating the newly developed correction method through the comparison of its test exposure and the one with conventional dose modulation method. Secondly, the electron Resolution Improvement Feature is presented with the test application for complementary exposure and with the application of real design, specifically for sub-30nm nodes. Finally, we discuss the requirements of data preparation for the practical applications in e-beam lithography, especially for future technology nodes.

For the manufacturing of semiconductor technologies following the ITRS roadmap, we will face the nodes well below 32nm half pitch in the next 2~3 years. Despite being able to achieve the required resolution, which is now possible with electron beam direct write variable shaped beam (EBDW VSB) equipment and resists, it becomes critical to precisely reproduce dense line space patterns onto a wafer. This exposed pattern must meet the targets from the layout in both dimensions (horizontally and vertically). For instance, the end of a line must be printed in its entire length to allow a later placed contact to be able to land on it. Up to now, the control of printed patterns such as line ends is achieved by a proximity effect correction (PEC) which is mostly based on a dose modulation. This investigation of the line end shortening (LES) includes multiple novel approaches, also containing an additional geometrical correction, to push the limits of the available data preparation algorithms and the measurement. The designed LES test patterns, which aim to characterize the status of LES in a quick and easy way, were exposed and measured at Fraunhofer Center Nanoelectronic Technologies (CNT) using its state of the art electron beam direct writer and CD-SEM. Simulation and exposure results with the novel LES correction algorithms applied to the test pattern and a large production like pattern in the range of our target CDs in dense line space features smaller than 40nm will be shown.

For the manufacturing of semiconductor technologies following the ITRS roadmap, we will face the nodes well below 32nm half pitch in the next 2~3 years. Despite being able to achieve the required resolution, which is now possible with electron beam direct write variable shaped beam (EBDW VSB) equipment and resists, it becomes critical to precisely reproduce dense line space patterns onto a wafer. This exposed pattern must meet the targets from the layout in both dimensions (horizontally and vertically). For instance, the end of a line must be printed in its entire length to allow a later placed contact to be able to land on it. Up to now, the control of printed patterns such as line ends is achieved by a proximity effect correction (PEC) which is mostly based on a dose modulation. This investigation of the line end shortening (LES) includes multiple novel approaches, also containing an additional geometrical correction, to push the limits of the available data preparation algorithms and the measurement. The designed LES test patterns, which aim to characterize the status of LES in a quick and easy way, were exposed and measured at Fraunhofer Center Nanoelectronic Technologies (CNT) using its state of the art electron beam direct writer and CD-SEM. Simulation and exposure results with the novel LES correction algorithms applied to the test pattern and a large production like pattern in the range of our target CDs in dense line space features smaller than 40nm will be shown.

For the manufacturing of semiconductor technologies following the ITRS roadmap, we will face nodes well below a 32-nm half pitch in the next 2 to 3 years. Despite being able to achieve the required resolution, which is now possible with electron beam direct-write variable-shaped beam equipment and resists, it becomes critical to precisely reproduce dense line space patterns onto a wafer. This exposed pattern must meet the targets from the layout in both dimensions (horizontally and vertically). For instance, the end of a line must be printed in its entire length to allow a contact to be placed later. Up to now, the control of printed patterns such as line ends was achieved by a proximity effect correction mostly based on a dose modulation. This investigation of line end shortening (LES) includes multiple novel approaches, and contains an additional geometrical correction to push the limits of the available data preparation algorithms and the measurement. The designed LES test patterns, which aim to characterize the status of LES in a quick and easy way, were exposed and measured at Fraunhofer Center Nanoelectronic Technologies using its state-of-the-art electron beam direct writer and CD-SEM. Simulation and exposure results with the novel LES correction algorithms applied to the test pattern and a large production-like pattern in the range of our targeted critical structure dimensions in dense line space features smaller than 40 nm will be shown.

For shortening the writing time, especially in shaped Electron Beam Direct Writing (EBDW), it is crucial to reduce the number of shapes and the coverage of layout for exposure. The determination of conventional or reversed image printing according to the process integration is one of the concerns for time and cost-effective process in the EBDW. We have studied two different cases for the purpose above. First, the proximity effect correction (PEC) with dose modification applied on each tone of resists, positive and negative, for the printing of conventional and reversed images. The CDs that are obtained from the both printed images compared and are either with that from the simulations. Secondly, the two different types of PEC, dose and shape modification, applied to a conventional image using an identical point spread function (PSF). The line edge roughness (LER), line width roughness (LWR) and CDs in dose and shape corrected conventional image pattern have been measured and compared. The MGS/PROXECCO was used for all the preparation of exposure data mentioned above. In summary, we suggest the strategies of efficient PEC for the EBDW of contrasting images, propose the available method of PEC for the time-efficient EBDW, and for the further multiple EBDW developments.

In electron beam lithography, the electron scattering and the corresponding proximity effect highly influence the feature resolution. Especially for sub-100 nm features a compensation for this effect is needed. There are several methods of determination of the proximity parameters, which mostly are time-consuming and complex due to a need of an initial proximity effect correction and immense measurement effort. In this paper the checkerboard pattern is proposed to provide the opportunity for proximity parameter determination in a fast and easy manner without using a sophisticated CD-SEM metrology. The concept is illustrated by simulation and first experimental results are shown.