336 results on '"Chuang, Ching-Te"'
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2. A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line
3. Asymmetrical Triple-Gate FET
4. A double-sided, single-chip integration scheme using through-silicon-via for neural sensing applications
5. Impacts of gate-oxide breakdown on power-gated SRAM
6. Reducing parasitic BJT effects in partially depleted SOI digital logic circuits
7. Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50 nm double gate devices
8. Restoration of controllable hysteresis in partially depleted SOI CMOS Schmitt trigger circuits
9. 28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications
10. 0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process
11. 28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications
12. Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes
13. A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
14. A 64-channel wireless neural sensing microsystem with TSV-embedded micro-probe array for neural signal acquisition
15. Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations
16. An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer
17. Performance and Stability Benchmarking of Monolithic 3-D Logic Circuits and SRAM Cells With Monolayer and Few-Layer Transition Metal Dichalcogenide MOSFETs
18. Impacts of work function variation and line edge roughness on hybrid TFET-MOSFET monolithic 3D SRAMs
19. Performance evaluation of pass-transistor-based circuits using monolayer and bilayer 2-D transition metal dichalcogenide (TMD) MOSFETs for 5.9nm node
20. Evaluation of analog performance of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) MOSFETs
21. An Advanced 2.5-D Heterogeneous Integration Packaging for High-Density Neural Sensing Microsystem
22. Stability optimization of monolithic 3-D MoS2-n/WSe2-p SRAM cells for superthreshold and near-/sub-threshold applications
23. Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application
24. Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells
25. Impact of Random Variations on Cell Stability and Write-Ability of Low-Voltage SRAMs Using Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) MOSFETs
26. Integration of neural sensing microsystem with TSV-embedded dissolvable µ-needles array, biocompatible flexible interposer, and neural recording circuits
27. Exploration and evaluation of hybrid TFET-MOSFET monolithic 3D SRAMs considering interlayer coupling
28. Investigation of BTI reliability for monolithic 3D 6T SRAM with ultra-thin-body GeOI MOSFETs
29. An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes
30. A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper
31. 28nm ultra-low power near-/sub-threshold first-in-first-out (FIFO) memory for multi-bio-signal sensing platforms
32. Performance benchmarking of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) based logic circuits
33. Evaluation of Monolithic 3-D Logic Circuits and 6T SRAMs With InGaAs-n/Ge-p Ultra-Thin-Body MOSFETs
34. Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications
35. Energy-efficient gas recognition system with event-driven power control
36. Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications
37. Evaluation of 32-Bit carry-look-ahead adder circuit with hybrid tunneling FET and FinFET devices
38. Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits
39. A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
40. Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness
41. Impacts of NBTI and PBTI on ultra-thin-body GeOI 6T SRAM cells
42. Stability analysis for UTB GeOI 6T SRAM cells considering NBTI and PBTI
43. Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications
44. All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction
45. Analysis of monolithic 3D 6T SRAM using ultra-thin-body InGaAs/Ge MOSFETs considering interlayer coupling
46. Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices
47. 2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications
48. Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits
49. A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist
50. 0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS
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