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Ensuring safe operation of stimulators is the most important issue in neural stimulation. Safety, in terms of stimulators' electrical performances, can be related mainly to two factors; the zero-net charge transfer to tissue and the heat generated by power dissipation at tissue. This paper presents a safety ensuring neuro-stimulator for retinal vision prostheses, featuring precise charge balancing capability and low power consumption, using a 0.35 \mum HV (high voltage) CMOS process. Also, the required matching accuracy of the biphasic current pulse for safe stimulation is mathematically derived. Accurate charge balance is achieved by employing a dynamic current mirror at the output of a stimulator. In experiments, using a simple electrode model (a resistor (R) and a capacitor (C) in parallel), the proposed stimulator ensures less than 30 nA DC current flowing into tissue over all stimulation current ranges (32 \muA–1 mA), without shorting. With shorting enabled, further reduction is achieved down to 1.5 nA. Low power consumption was achieved by utilising small bias current, sharing of key biasing blocks, and utilising a short duty cycle for stimulation. Less than 30 \muW was consumed during stand-by mode, mostly by bias circuitry. [ABSTRACT FROM PUBLISHER]

Hardware security has emerged as a field concerned with issues such as integrated circuit (IC) counterfeiting, cloning, piracy, and reverse engineering. Physical unclonable functions (PUF) are hardware security primitives useful for mitigating such issues by providing hardware-specific fingerprints based on intrinsic process variations within individual IC implementations. As technology scaling progresses further into the nanometer region, emerging nanoelectronic technologies, such as memristors or RRAMs (resistive random-access memory), have become interesting options for emerging computing systems. In this article, using a comprehensive temperature dependent model of an HfOx (hafnium-oxide) memristor, based on experimental measurements, we explore the best region of operation for a memristive crossbar PUF (XbarPUF). The design considered also employs XORing and a column shuffling technique to improve reliability and resilience to machine learning attacks. We present a detailed analysis for the noise margin and discuss the scalability of the XbarPUF structure. Finally, we present results for estimates of area, power, and delay alongside security performance metrics to analyze the strengths and weaknesses of the XbarPUF. Our XbarPUF exhibits nearly ideal (near 50%) uniqueness, bit-aliasing and uniformity, good reliability of 90% and up (with 100% being ideal), a very small footprint, and low average power consumption ≈104µW. [ABSTRACT FROM AUTHOR]