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To solve the issues of low resource utilization and performance bottleneck in current server-centric data center networks (DCNs), we propose and experimentally demonstrate a disaggregated application-centric optical network (DACON) for data center infrastructures based on hybrid optical switches. DACON achieves flexible provision and dynamic reconfiguration of hardware nodes exploiting the softwared-define networking (SDN) orchestration plane. A four-node SDN-enabled disaggregated prototype is implemented with a field-programmable-gate-array-based controller of hardware nodes and nanosecond optical switches, performing a minimal node-to-node network latency of 378.6 ns and zero packet loss. Based on the unmodified Linux kernel and two different applications (distributed computing and a Memcached database), the application runtime of the disaggregated prototype is investigated and compared with the server-centric architecture. Experimental results show that the disaggregated prototype performs better with Memcached database applications, achieving a 1.46 × faster runtime than the server-centric network at a memory node access ratio of 0.9. Based on the customized control plane orchestrator and dynamic resource reallocation, the node-to-node latency is reduced by 21% when CPU nodes access memory nodes. The scalability of DACON is then numerically assessed based on experimentally measured parameters. Results show that the intra-rack node-to-node latency is less than 404.8 ns with a 6144-node network and memory node access ratio of 0.9. Finally, the cost and power consumption are also studied and compared with current DCN architectures. Results indicate DACON saves 13.4% of the cost of an interconnect network compared with current disaggregated architecture and consumes up to 31.1% less power with respect to server-centric DCN architectures.

Data centers are increasingly using high-speed circuit switches to cope with the growing demand and reduce operational costs. One of the fundamental tasks of circuit switches is to compute a sparse collection of switching configurations to support a traffic demand matrix. Such a problem has been addressed in the literature with variations of the approach proposed by Birkhoff in 1946 to decompose a doubly stochastic matrix exactly. However, the existing methods are heuristic and do not have theoretical guarantees on how well a collection of switching configurations (i.e., permutations) can approximate a traffic matrix (i.e., a scaled doubly stochastic matrix). In this paper, we revisit Birkhoff’s approach and make three contributions. First, we establish the first theoretical bound on the sparsity of Birkhoff’s algorithm (i.e., the number of switching configurations necessary to approximate a traffic matrix). In particular, we show that by using a subset of the admissible permutation matrices, Birkhoff’s algorithm obtains an ǫ-approximate decomposition with at most O(log(1/ǫ)) permutations. Second, we propose a new algorithm, Birkhoff+, which combines the wealth of Frank-Wolfe with Birkhoff’s approach to obtain sparse decompositions in a fast manner. And third, we evaluate the performance of the proposed algorithm numerically and study how this affects the performance of a circuit switch. Our results show that Birkhoff+ is superior to previous algorithms in terms of throughput, running time, and number of switching configurations.

A hybrid optical/electrical datacenter network (HOE-DCN) integrates the benefits of electrical packet switching (EPS) and optical circuit switching (OCS) for better architectural scalability. Meanwhile, as each network service usually involves multiple virtual machines (VMs) that form a virtual network (VNT), how to reconfigure the VNTs in an HOE-DCN to adapt to the dynamic network environment becomes an interesting and important problem to tackle. In this work, we optimize the procedure of VNT reconfigurations that remap VNTs to given virtual network embedding (VNE) schemes, i.e. , scheduling the required VM migrations and optical cross-connect (OXC) reconfiguration properly such that the overall VNT reconfiguration latency can be minimized. We first assume that all the VM migrations should be scheduled before the OXC reconfiguration to minimize service interruptions, and formulate a mixed integer linear programming (MILP) model to solve the scheduling problem exactly. Then, with the same assumption, we propose a time-efficient heuristic to schedule parallel VM migrations in batches such that the bandwidth competition can be significantly relieved. Finally, we divide the OXC reconfiguration into several progressive steps, and design a joint scheduling algorithm to arrange VM migrations together with the OXC reconfiguration steps.

Discrete-time queueing systems have widespread applications in packet switching networks, internet protocol, Broadband Integrated Services Digital Network (B-ISDN), circuit switched time-division m...

In this paper, it is considered the broadband backbone optical networks with wavelength routing and circuit switching used to build long-range wide area networks. In this type of network, if there is an available and acknowledged connection request, it is necessary to determine the optimal path between the optical communication nodes in the network. This also requires the assignment of an optimal set of wavelengths along the selected route between these nodes. This paper takes into account the multichannel optical communication networks with spectral multiplexing. Four different routing algorithms are modeled and analyzed for which their weight functions are determined to take into account various factors, such as the total distance of the individual routes, the total number of available wavelengths for a given route and how many of them are available for use. It is studied and compared the performance of the proposed algorithms in a multichannel optical network in terms of blocking probability.

Nowadays, optical circuit switching is becoming an increasingly favored technology in scaling data center networks for its definitive advantages in data rate, power consumption, and device cost. Concurrently, reducing coflow completion time (CCT) is of great significance for improving application-level performance. However, minimizing CCT in circuit switched networks is totally different from that in traditional packet switched networks due to port constraints and circuit reconfiguration delays. To address this issue, this article proposes Grouped Optimization-based Scheduling (GOS), a CCT minimization algorithm for circuit switched networks integrating circuit and coflow scheduling. We first formalize the CCT minimization problem into a 0-1 programming problem, then relax and solve the problem in 2 steps to obtain the coflow order and flow grouping decisions on each circuit. Thus intra-group reconfiguration delays are saved, and small coflows can be prioritized at the group level. Theoretical analysis proves GOS is a 4-approximation algorithm in average CCT. To reduce computing overheads, we further propose a heuristic approximation algorithm. Extensive simulations show that the heuristic algorithm has satisfactory CCT performance (0.12× Varys, 0.36× Sunflow) as well as high throughput (16.74× Varys, 1.32× Sunflow), and well adapts to a wide range of reconfiguration delays and algorithm decision time.

For almost a decade now, Network on Chip (NoC) concepts have evolved to provide an interesting alternative to more traditional intrachip communication architectures (e.g. shared busses) for the design of complex Systems on Chip (SoCs). A considerable number of NoC proposals are available, focusing on different sets of optimization aspects, related to specific classes of applications. Each such application employs a NoC as part of its underlying implementation infrastructure. Many of the mentioned optimization aspects target results such as Quality of Service (QoS) achievement and/or power consumption reduction. On the other hand, the use of NoCs brings about the solution of new design problems, such to the choice of synchronization method to employ between NoC routers and application modules mapping. Although the availability of NoC structures is already rather ample, some design choices are at base of many, if not most, NoC proposals. These include the use of wormhole packet switching and virtual channels. This work pledges against this practice. It discusses trade-offs of using circuit or packet switching, arguing in favor the use of the former with fixed size packets (cells). Quantitative data supports the argumentation. Also, the work proposes and justifies replacing the use of virtual channels by replicated channels, based on the abundance of wires in current and expected deep sub-micron technologies. Finally, the work proposes a transmission method coupling the use of session layer structures to circuit switching to better support application implementation. The main reported result is the availability of a router with reduced latency and area, a communication architecture adapted for high-performance applications.

Novel approaches to switching ultra-fast semiconductor optical amplifiers using artificial intelligence algorithms (particle swarm optimisation, ant colony optimisation, and a genetic algorithm) are developed and applied both in simulation and experiment. Effective off-on switching (settling) times of 542 ps are demonstrated with just 4.8% overshoot, achieving an order of magnitude improvement over previous attempts described in the literature and standard dampening techniques from control theory., This manuscript was accepted for publication in the IEEE/OSA Journal of Lightwave Technology on 21st June 2020. Open access code: https://github.com/cwfparsonson/soa_driving Open access data: https://doi.org/10.5522/04/12356696.v1

Photonic network-on-chip is utilized as a candidate paradigm for important attributes such as high bandwidth and low energy consumption. In this paper, a non-blocking five-port photonic router is proposed for the 2-D mesh topology, which is called Surix. Surix has been designed for improving the physical layer and the network’s performance parameters in multi-core network topologies. Moreover, a new routing algorithm on Surix is proposed, in which turning models and the circuit switching method are used for mitigating photonic insertion loss and power consumption of the photonic layer. The proposed algorithm can select various source and destination nodes through the selected routes with the lowest insertion loss and power consumption. The simulation results show that Surix outperforms conventional routers in network performance parameters. For instance, the insertion loss of Surix in the mesh topology shows a 9.92–37.15 percent improvement compared to conventional routers.

This paper presents an experimental research on configuration optimization of a frost-free refrigerator-freezer with the parallel circuit cycle based on the analysis of circuit switching characteristics. Through combination optimization of R-fan voltage, F-fan voltage, R-capillary tube flow capacity, refrigerant charge, structure of suction pipe, F-compressor speed and R-compressor speed, the system could save 9.27% energy consumption compared with the initial condition. The experimental results also showed that the larger the R-capillary tube flow capacity, the larger the flow rate of the RC, resulting in the quickly temperature drop in R-cabinet and slowly temperature drop in R-cabinet based on “R-cabinet temperature priority” control strategy. Additionally, the R-cabinet temperature drop rate decreased with the increase of ambient temperature but the F-cabinet temperature drop rate was almost unaffected by the ambient temperature.

We introduce PULSE, a sub-microsecond optical circuit-switched data centre network architecture controlled by distributed hardware schedulers. PULSE is a flat architecture that uses parallel passive coupler-based broadcast and select networks. We employ a novel transceiver architecture, for dynamic wavelength-timeslot selection, to achieve a reconfiguration time down to O(100ps), establishing timeslots of O(10ns). A novel scheduling algorithm that has a clock period of 2.3ns performs multiple iterations to maximize throughput, wavelength usage and reduce latency, enhancing the overall performance. In order to scale, the single-hop PULSE architecture uses sub-networks that are disjoint by using multiple transceivers for each node in 64 node racks. At the reconfiguration circuit duration (epoch = 120 ns), the scheduling algorithm is shown to achieve up to 93% throughput and 100% wavelength usage of 64 wavelengths, incurring an average latency that ranges from 0.7-1.2 microseconds with best-case 0.4 microsecond median and 5 microsecond tail latency, limited by the timeslot (20 ns) and epoch size (120 ns). We show how the 4096-node PULSE architecture allows up to 260k optical channels to be re-used across sub-networks achieving a capacity of 25.6 Pbps with an energy consumption of 85 pJ/bit., 16 pages, 12 figures

This article discusses a DC–DC converter based solar fed PV array system for low power applications. A single diode based solar panel is designed and modelled for this PV array system. At low value of irradiance in solar panel, the system will perform with better accuracy. To acquire better efficiency, the similar system is operated with Maximum Power Point Tracking (MPPT) control algorithm. The solar panel current v/s Voltage (I–V) and Power v/s Voltage (P–V) characteristics curves are obtained from Matlab simulation. The comparison of simulation curves is also done with the curves obtained from the experiment results. The detailed investigation of DC–DC converters with solar fed system with soft-switching technique is also performed. This soft-switching technique is formed by using the resonant inductors and capacitors. These passive components reduce the circuit switching losses. The Zero Voltage Switching (ZVS) technique is used to eliminate the switching losses developed in the circuit at the time of switching transitions. This technique also reduces the dv/dt noise owing to junction capacity discharge. This Proposed ZETA and SEPIC converters based system are modelled and simulated in MATLAB program and its performance is evaluated through experimentation in the terms of losses and efficiency. From the performance study of ZVS ZETA and SEPIC converter, increment in efficiency are obtained 1.97% and 7.23% under Perturb and Observe MPPT control and 4.14% and 0.41% in Incremental Conductance MPPT control respectively as compared to its conventional ZETA and SEPIC converter.

As data centers enter the exascale computing era, the traffic exchanged between internal network nodes, increases exponentially. Optical networking is an attractive solution to deliver the high capacity, low latency, and scalable interconnection needed. Among other switching methods, packet switching is particularly interesting as it can be widely deployed in the network to handle rapidly-changing traffic of arbitrary size. Nanosecond-reconfigurable photonic integrated switch fabrics, built as multi-stage architectures such as the Clos network, are key enablers to scalable packet switching. However, the accompanying control plane needs to also operate on packet timescales. Designing a central scheduler, to control an optical packet switch in nanoseconds, presents a challenge especially as the switch size increases. To this end, we present a highly-parallel, modular scheduler design for Clos switches along with a proposed routing scheme to enable nanosecond scalable scheduling. We synthesize our scheduler as an application-specific integrated circuit (ASIC) and demonstrate scaling to a 256 × 256 size with an ultra-low scheduling delay of only 6.0 ns. In a cycle-accurate rack-scale network emulation, for this switch size, we show a minimum end-to-end latency of 30.8 ns and maintain nanosecond average latency up to 80% of input traffic load. We achieve zero packet loss and short-tailed packet latency distributions for all traffic loads and switch sizes. Our work is compared to state-of-the-art optical switches, in terms of scheduling delay, packet latency, and switch throughput.

In this paper, a general description of the problem of calculating probability–time characteristics was presented. At the initial stage of studying this problem, we studied the asynchronous data transmission of the constituent broadband digital network with the integration of services for both the channel switching subnetwork and the packet switching subnetwork. And also the circuit switching subnetwork was investigated using the bypass of the direction of transmission of the stream of multi-channel calls. At the same time, the source data of the problem of calculating probabilistic characteristics were set for the channel switching subnetwork, the characteristics that were determined during the solution of the problem were listed, and some assumptions were described that made it possible to adequately approximate the study of such a model to the functioning of a real network. Next, a mathematical model for calculating the loss probabilities was described, both for communication channels and for nodes of the channel switching subnetwork included in the asynchronous transfer mode network. The model of information traffic transmission is presented, where the method is implemented using network bypass directions. A method has been developed for generating a nodal load of a channel switching subnet and a system of equations has been obtained, the solution of which determines the value of a nodal load relative to the probability of loss on communication channels and proved the uniqueness of the solution of this system of equations.

Fast optical circuit switching has significant potential to solve scaling issues with traditional packet-switch-based networks and improve bandwidth and power efficiency in datacenter and high-performance computing applications. One difficultly in utilizing a fast optical switch is that the optical signal must be rapidly reacquired after each switching event so as to not significantly impact the overall throughput of the system. Here we present a system-level integration of a nanosecond-scale $2\times 2$ silicon photonic switch with a 25-Gbps burst-mode receiver that can lock in 31 ns. A novel FPGA-based control plane was used to generate test data, control the silicon photonic switch and burst-mode receiver, and measure bit errors at 12.5 and 20 Gbps. Error-free links (BER $ ) with system-level reconfiguration times below 60 ns (at 20 Gbps) and 90 ns (at 12.5 Gbps) including bit- and frame-synchronization are demonstrated.

In handover procedure, target cell would be prepared and UE will move on target cell based on the configuration sent by source eNodeB to User Equipment. Cell Reselection happens only when the user equipment (or Mobile Phone) is in Idle MODE, and the User Equipment needs to go a more appropriate cell. The main feature of CSFB Ps handover does not interrupt data transfer when switching from Long Term Evolution to UTRAN/GSM. After switching to 3G is already in connected mode it does not waste time to switch to connected mode. This feature let us improve call setup time when we make call in LTE.