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Multi-finger floating-base silicon controlled rectifiers (SCRs) of discrete technologies are investigated by transmission line pulses (TLP) with short (300ps) and long (10ns) pulse rise times (RT). Transient interferometric mapping (TIM) is applied to study the finger triggering dynamics. The measurements are correlated with TCAD simulation. It is found that for short RT the fingers trigger simultaneously which is due to the positive influence of a voltage overshoot related to delayed conductivity modulation. For long RT the fingers trigger sequentially which is accompanied by the voltage drops near the holding voltage. The time delay between the triggering of neighboring fingers is in the 3–150ns range and depends on the actual current density in fingers. The sequential finger triggering is due to lateral carrier diffusion-limited processes and the coupling via substrate currents.

The operation of stacked MOSFET circuit for RF switch application under electrostatic discharge (ESD) conditions is studied by transmission line pulse (TLP) and transient interferometric mapping (TIM) techniques combined with circuit simulation. TLP pulses with 100–840 ns durations were applied to the device composed of 16 stacked multifinger MOSFET blocks with gate and drain resistors, fabricated in a bulk technology. ESD discharge paths related to MOSFET channel and to open-base breakdown have been identified to have dominant role in explaining the complex voltage and current waveforms. The overall circuit behavior during TLP pulses is analyzed taking into account calibrated breakdown measurements on test structures. In order to explain the heat dissipation in MOSFET blocks measured by TIM, additional discharge paths related to block-to-block coupling due to parasitic bipolar action have been modeled and discussed. Besides the analysis of the device behavior, we have also investigated peculiar optical TIM signal related to anisotropic reflectivity and phase response due to dense multifinger block structure.

Transient interferometric mapping (TIM) and backside light emission microscopy (EMMI) are applied to study the trigger behavior and on-state spreading in discrete-technology electrostatic discharge (ESD) protection silicon controlled rectifier (SCR) test-structures without and with trigger taps. The trigger taps or device corners are clearly identified as regions where the avalanche breakdown and SCR action are initiated. The regions relevant to the holding current can be identified by EMMI. In SCR mode the injection regions from the npn and pnp emitters have been localized by TIM. The on-state spreading (OSS) speed of 1–4 μm/ns obtained from TIM is consistent with the results of 3D TCAD simulations. The driving force of the OSS is discussed on the basis of TCAD results.

Successive voltage drops near the holding voltage associated with sequential finger triggering (SFT) are observed in multi-finger floating-base SCRs. A time delay between the triggering of neighboring fingers is in the 3–150ns range and it is observed only for long pulse rise times (10ns). TCAD simulation explains that SFT is due to lateral carrier diffusion-limited processes.

This paper reports an analysis of the degradation mechanisms of GaN-based normally-off transistors submitted to off-state stress, forward-gate operation and electrostatic discharges. The analysis was carried out on transistors with p-type gate, rated for 600 V operation, developed within the European Project HIPOSWITCH. DC measurements, thermal analysis by transient interferometric mapping (TIM), and transmission line pulse (TLP) were used in combination to achieve a complete description of the degradation and failure processes. The results of this investigation indicate that: (i) the analyzed devices have a breakdown voltage (measured at 1 mA/mm) higher than 600 V; in off-state, drain current originates from gate–drain leakage for drain voltages (VDS) smaller than 500 V, and from vertical leakage through the conductive substrate for higher drain bias. (ii) step-stress experiments carried out in off-state conditions may induce instabilities in both drain–source conduction and gate leakage. Failure consists in the shortening of the gate junction, and occurs at VDS higher than 600 V. (iii) in forward bias, the p-type gate is stable up to 7 V; for higher gate voltages, a time-dependent degradation is detected, due to the high electric field across the AlGaN barrier; (iv) TIM analysis performed under short-circuited load conditions revealed hot spots at the drain side of the channel in the access region, thus indicating that these regions may behave as weak spots under high bias operation. Cumulative device degradation under such repeating pulses has also been revealed. (v) TLP tests were carried out to evaluate the voltage limits of the devices under off-state and on-state conditions. The results described within this paper provide relevant information on the reliability issues of state-of-the-art normally-off HEMTs with p-type gate.

In this work, current multiplication at high electric field in epitaxial boron-doped diamond with high acceptor concentration is analyzed, including self-heating effect and impurity impact ionization. Quasi-static current-voltage (I-V) characteristics were measured using a transmission-line pulse setup with 100 ns pulse duration on samples with two Ohmic titanium/gold electrodes. Unambiguous exponential and super-exponential behaviors are observed in the I-V curves along with, in some cases, negative differential resistance. The self-heating effect is analyzed using transient interferometric mapping of the thermal energy distribution between electrodes with an ns time scale. Measured I-V characteristics are modelled by finite element method and by considering boron acceptor ionization due to self-heating effect and impurity impact ionization. Simulated I-V characteristics, in particular the appearance of the negative differential resistance region attributed to self-heating, are in good agreement with experimental data.

We analyse high temperature effects (up to 420 °C) in the performances of p-GaN gate normally-off AlGaN/GaN HEMTs on Si and SiC substrates for power applications. With increasing temperature, IDMAX (R ON ) decreases (increases) and the threshold voltage slightly decreases independently of the substrate and doping. The room temperature (RT) DC IV characteristics of the devices after 90 min at temperatures above 300 °C are not affected. Step stress experiments at 420 °C show more than twofold decrease of the blocking capabilities compared to RT. Finally, thermal activation of the vertical leakage current has been analysed up to 180 °C.

The ESD robustness of multi-finger nMOSFET transistors in an advanced RF CMOS technology has been analysed by both TLP and, for the first time, by transient interferometric mapping (TIM) technique. Failure current It2 has been studied for different source, gate and bulk contact grounding configurations, for TLP pulse duration between 25 ns and 550 ns and TLP rise time of 1 ns and 10 ns. The lateral distribution of dissipated thermal energy during a TLP pulse has been measured by TIM. The ESD failures for selected pad configurations are investigated by DC-IV and physical failure analysis. The highest (lowest) It2 has been revealed for floating (grounded) gate and bulk pads, and attributed to the pn junction (gate oxide) damage.

Current conduction mechanism, including electron mobility, electron drift velocity (vd) and electrical break-down have been investigated in a 0.5 μm-thick (0001) InN layer grown by molecular-beam epitaxy on a GaN/sapphire template. Electron mobility (μ) of 1040 cm2/Vs and a free electron concentration (n) of 2.1 × 1018 cm−3 were measured at room temperature with only a limited change down to 20 K, suggesting scattering on dislocations and ionized impurities. Photoluminescence spectra and high-resolution X-ray diffraction correlated with the Hall experiment showing an emission peak at 0.69 eV, a full-width half-maximum of 30 meV, and a dislocation density Ndis ∼ 5.6 × 1010 cm−2. Current-voltage (I-V) characterization was done in a pulsed (10 ns-width) mode on InN resistors prepared by plasma processing and Ohmic contacts evaporation. Resistors with a different channel length ranging from 4 to 15.8 μm obeyed the Ohm law up to an electric field intensity Eknee ∼ 22 kV/cm, when vd ≥ 2.5 × 105 m/s. For higher ...

DC and transient self-heating effects are investigated in normally off AlGaN/GaN transistors designed for a high-power operation. Electrical and optical methods are combined with thermal simulations; 2-μs-long voltage pulses dissipating about 4.5 W/mm are applied on four different transistor structures combining GaN or AlGaN buffer on an n-type SiC substrate with or without Ar implantation. Transistors with only 5% Al mass fraction in the buffer show almost a threefold increase in the transient self-heating if compared with devices on the GaN buffer. On the other hand, 2-μs-long pulses were found not to be long enough for the Ar-implanted SiC substrate to influence the device self-heating unless AlGaN composition changes. In the dc mode, however, both the buffer composition and Ar implantation significantly influence the self-heating effect with the highest temperature rise for the transistor having the AlGaN buffer grown on the Ar-implanted SiC. We point on possible tradeoffs between the transistor high-power design and the device thermal resistance.

Electrostatic discharge behavior of integrated SiGe heterojunction bipolar transistors is investigated by transmission line pulse (TLP) and transient interferometric mapping techniques. When stressing collector - base junction in reverse direction, two distinct non-thermal failure modes, depending on TLP pulse rise time (RT), have been found: For RT ≥ 10 ns the observed failure at a critical voltage is attributed to base corner breakdown as supported by failure analysis. For RT ≤ 5 ns the failure occurs due to parasitic capacitance coupling which virtually short-circuits the base-emitter junction at the pulse beginning and thus induces a parasitic bipolar action.

We report on fabrication of enhancement-mode True-MOS high electron mobility transistor (HEMT) with ZrO 2 gate dielectric. The GaN cap and AlGaN layers in the gate area are completely recessed by dry etching up to the GaN channel layer. The increase in channel resistance subsequent to the recess is compensated by adopting sub-micrometer gates and the negative V th shift is mitigated by using a high-k dielectric. The maximum output current of 0.45 A/mm for a 0.5 μm gate length shows that the above concept can be promising for switching applications.

We analyse vertical breakdown signatures in normally-off and normally-on AlGaN/GaN HEMTs on Si and SiC substrate for power applications. The probability distribution function of the breakdown voltage V BD values shows mostly a bimodal distribution that is characteristic for substrate/epitaxy type and bias polarity. Different types of distribution functions are tested. The vertical breakdown is found to be a time dependent phenomenon and hypotheses for its initiation are discussed. Using backside infrared microscopy, we found that the breakdown occurs in localized spots, related to current filaments. Failure localisation under pulsed mode shows better spatial localisation compared to the DC conditions.

We provide theoretical and simulation analysis of the small signal response of SiO2/AlGaN/GaN metal insulator semiconductor (MIS) capacitors from depletion to spill over region, where the AlGaN/SiO2 interface is accumulated with free electrons. A lumped element model of the gate stack, including the response of traps at the III-N/dielectric interface, is proposed and represented in terms of equivalent parallel capacitance, Cp, and conductance, Gp. Cp -voltage and Gp -voltage dependences are modelled taking into account bias dependent AlGaN barrier dynamic resistance Rbr and the effective channel resistance. In particular, in the spill-over region, the drop of Cp with the frequency increase can be explained even without taking into account the response of interface traps, solely by considering the intrinsic response of the gate stack (i.e., no trap effects) and the decrease of Rbr with the applied forward bias. Furthermore, we show the limitations of the conductance method for the evaluation of the density...

We perform a comprehensive electrical transport and physical characterization of metal oxide semiconductor heterostructure field effect transistors with ZrO 2 gate dielectrics, having partially (referred here as MOS-HFET) and fully (here called true-MOS-FET) recessed GaN/AlGaN/GaN barrier, giving normally-on and normally-off behavior, respectively. The mobility of the MOS-HFETs decreases with the proximity of the Coulomb scattering centers, situated at the ZrO 2 /AlGaN interface. The effect of the etching procedure and ZrO 2 deposition on the formation of the interfacial charges, N int , is evaluated by X-ray Photoelectron Spectroscopy and by fitting the threshold voltage values to numerical model. For the both device types, the extracted value of N int lies within 15% around 2.8 × 10 13 cm −2 , which is of the order of polarization charge, showing that our low-damage three step etching procedure does not introduce extra interface states.