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Future space based particle physics experiments require detectors to be low power to ensure efficiency where no large amounts of energy can be continuously provided. The AstroPix chip aims for a power consumption of 1.5mW/cm2 and energy resolution of 2% at600keV per sensor. To determine the readiness of several wafers of different resistivities, 3 experiments were conducted. CV and IV data were taken using a probe station in SCIPP’s electronics room. The results determined that while the IV relationship looked normal for sensors with lower resistivities (from wafers 2 and 6), the sensors with higher resistivities (from wafers 10 and 11) had much higher current than anticipated, which inhibited the use of high voltage as breakdown occurred early.Another experiment consisted of taking data from a laser edge-TCT scan; this test confirmed the strange behavior of high resistivity chips as voltage amplitude pulses losttheir shape and amplitude with higher bias voltages which is contrary to intuition and the behavior of the lower resistivity chips. This led to the idea that with a high enough bias voltage, the leakage current incapacitates some of the transistors in W10 and W11 chips.The last experiment conducted was an infrared radiation scan of certain chips with the intention of furthering the investigation of the aforementioned anomalies. The result was that the backs of the high resistivity chips had different potentials than the fronts of the chips; when conducting tape was used on the backside of these chips, the current hit compliance (10mA) at a low voltage (10V). However, when using insulating tape or testing the chip on a metal chuck with probes in the high voltage and grounding pads, the chip was able to reach a higher voltage (220V) with the same current limit. This test shed lighton instances of higher power dissipation along the edges of certain chips which led to ideas about design flaws and differences in how different chips distributed current and dissipated power.

Amongst the piezoelectric thin films suited for microelectromechanical systems (MEMS), AlN has gained particular technological relevance due to its unique material properties (large bandgap, high dielectric strength, resistivity, thermal conductivity, elastic modulus, and acoustic velocity), sufficient piezoelectric coefficients, and compatibility with CMOS microfabrication processes. This critical review targets the CMOS-compatible low-temperature deposition of AlN by reactive magnetron sputtering and various possibilities for AlN doping with Sc and other transition metal ions. Deposition process parameters such as the substrate temperature, gas ratio, discharge power, deposition and base pressure, as well as the effects of the substrate/underlying layer roughness and post-deposition annealing, are discussed. This review aims at digesting the most relevant information for process development and quality control of doped and undoped CMOS-compatible piezoelectric AlN thin films. [ABSTRACT FROM AUTHOR]

In this work, design, simulation and comparative analysis of a novel Negative Capacitance FET (NCFET), Carbon Nanotube FET (CNTFET), FinFET and CMOS based astable multivibrator (AMV) and a current starved astable multivibrator (CSAMV) have been done. A performance comparison of the proposed circuits is made using variations in resistance, capacitance, temperature, and supply voltage ( V DD ) using HSPICE simulations. Most of the performance parameters are improved in the case of NCFET based CSAMV. An increase of 1.03% in the amplitude of output square wave in CNTFET-AMV when compared with FinFET-AMV was observed. A significant increase in the maximum frequency was achieved by 216% in NCFET-CSAMV compared with FinFET-AMV. The maximum frequency achieved is 220 MHz in the case of NCFET-CSAMV. It was also observed that NCFET-AMV Starts to function appropriately at 0.08 V compared to FinFET-AMV, which starts to function appropriately at 0.39 V. The average power dissipation was 2.41 times higher in FinFET-CSAMV than in NCFET-CSAMV. The average power consumed is a little higher in the case of NCFET-CSAMV than CMOS-AMV. Still, it can be overcome if the circuit is operated at a lower V DD . [ABSTRACT FROM AUTHOR]

This work presents a numerical analysis of a 2.45 GHz full-wave bridge rectifier for RF (radio frequency) energy harvesting under low-power input conditions, and a guideline for developing a figure of merit (FOM) for RF energy harvester rectennas by relying on data science techniques, laying the foundation for a universally accepted FOM. The performance of the full-wave bridge rectifier, using two types of Schottky diodes, HSMS2850 and SMS7630, was evaluated at −5 and −15 dBm, with the diodes achieving maximum power conversion efficiencies (PCEs) of 57% and 33%, respectively, and reflection coefficient S11 values below −30 dB. A printed circuit board was designed to prepare for future laboratory measurements offering insights into real-world performance. Additionally, a double-voltage rectifier was simulated, achieving PCE values of 41% and 66% at similar input power levels; furthermore, various CMOS-based rectifier topologies reached PCE values of 69% at −5 dBm and 43.6% at −26 dBm. [ABSTRACT FROM AUTHOR]

Frequency divider circuits divide the frequency of an input signal by a specified ratio. They are critical components in analog, digital, and mixed-signal microelectronics. In power-constrained environments, such as cryogenic electronics or implanted biomedical devices, minimizing power consumption is crucial. This paper reviews operational principles, benefits, trade-offs, and circuit solutions of three main typologies of frequency divider: Current Mode Logic (CML), Injection-Locking (IL), and True Single-Phase Clock (TSPC). Distinct trade-offs between operation speed, power efficiency, complexity, and integration make each of them suitable for specific applications. Nevertheless, hybrid circuit solutions combining different typologies could potentially balance performance and energy efficiency. This paper thus also reports and discusses examples of hybrid frequency dividers. Examples of frequency dividers implemented in emerging technologies, such as the FinFETs CMOS, are addressed, as well. The purpose of this paper is to guide designers in selecting frequency divider solutions that best meet the design-specific requirements. [ABSTRACT FROM AUTHOR]

This paper presents the design and the performance of a wide tuning-range millimeter-wave (mm-wave) two-core class-C 60 GHz VCO in 40 nm CMOS process, which can be integrated into wireless communication transceivers and radar sensors. The proposed architecture consists of a two-core 30 GHz fundamental VCO, a gain-boosted frequency doubler and an adaptive bias configuration. The two-core fundamental VCO structure achieves frequency generation in the vicinity of 30 GHz, where each VCO core targets a different frequency band. The two bands have sufficient overlap to accommodate for corner variations providing a large continuous tuning range. The desired frequency band is selected by activating or deactivating the appropriate VCO core, resulting in a robust switchless structure. This approach enables a considerably broad tuning range without compromising phase noise performance. Furthermore, the proposed topology utilizes an adaptive bias mechanism for robust start-up. Initially, the selected VCO core begins oscillating in class-B mode, and subsequently it transitions into class-C operation to offer improved performance. From post-layout simulations, after frequency doubling, the low-band VCO covers frequencies from 50.25 to 60.40 GHz, while the high-band VCO core spans frequencies from 58.8 to 73 GHz, yielding an overall tuning range of 36.92%. Owing to the gain-boosting topology, output power exceeds −14.2 dBm across the whole bandwidth. Simulated phase noise remains better than −92.1 dBc/Hz at a 1 MHz offset for all bands. Additionally, the two VCO cores never operate simultaneously, aiding in power efficiency. [ABSTRACT FROM AUTHOR]

Silicon-based Hall application-specific integrated circuit (ASIC) chips have become very successful, making them ideal for flexible electronic and sensor devices. In this study, we designed, simulated, and tested flexible hybrid integration angle sensors that can be made using complementary metal-oxide-semiconductor (CMOS) technology. These sensors are manufactured on a 100 µm-thick flexible polyimide (PI) membrane, which is suitable for large-scale production and has strong potential for industrial use. The Hall sensors have a sensitivity of 0.205 V/mT. Importantly, their sensitivity remains stable even after being bent to a minimum radius of 10 mm and after undergoing 100 bending cycles. The experiment shows that these flexible hybrid integration devices are promising as angle sensors. [ABSTRACT FROM AUTHOR]

CMOS logic gates inevitably generate timing jitter as they propagate digital signals. A portion of this jitter is a fundamental property of CMOS gates which cannot be eliminated or reduced, and thereby imposes a lower limit to achievable circuit jitter. The value of this intrinsic jitter of each gate is very small, but can be measured with a dedicated test circuit composed of chains of CMOS inverters. The measurements of the circuit also lead to the determination of the component of jitter which is caused by noise of the power supply which operates the gates. [ABSTRACT FROM AUTHOR]

Neuromorphic circuits offer a means to emulate or interface with the nervous system, yet detailed model implementations remain underexplored. This paper proposes an analog CMOS realization of the Pinsky-Rinzel (PR) neuron model, a conductance-based two-compartmental model of hippocampal CA3 pyramidal neurons capable of producing spike and complex bursting. To achieve first-order dynamics, we introduce a seven-segment approximation circuit with a customizable architecture based on the variable's behavior. For second-order dynamics, we modify the architectures of the log-domain low pass filter and Tau-cell. To enhance power and area efficiency, we implement conductances and reversal potentials using current mirrors within circuit blocks. Additionally, we propose four compact subthreshold multipliers specifically tailored for neuromorphic systems, while eliminating any unnecessary DC current across circuit blocks. These modifications led to a 150-fold reduction in power consumption compared to state-of-the-art conductance-based implementations. Simulation results demonstrate the independent operation of soma and dendrite compartments for spike generation, while coupling generates complex bursting. Realized in TSMC 65 nm CMOS technology with a 0.2 V subthreshold power supply, the circuit operates in the 50–300 kHz frequency range, showcasing an average power consumption of 125.1 nW. Finally, Monte Carlo simulations for both spiking and complex bursting modes are evaluated in 200 points. These results not only validate the functionality of the proposed circuit but also position it as a versatile platform for implementing various conductance-based models, including astrocytes. [ABSTRACT FROM AUTHOR]

This review into recent advancements in silicon-based technology, with a particular emphasis on the biomedical applications of silicon sensors. Owing to their diminutive size, high sensitivity, and intrinsic compatibility with electronic systems, silicon-based sensors have found widespread utilization across healthcare, industrial, and environmental monitoring domains. In the realm of biomedical sensing, silicon has demonstrated significant potential to enhance human health outcomes while simultaneously driving progress in microfabrication techniques for multifunctional device development. The review systematically examines the versatile roles of silicon in the fabrication of electrodes, sensing channels, and substrates. Silicon electrodes are widely used in electrochemical biosensors for glucose monitoring and neural activity recording, while sensing channels in field-effect transistor biosensors enable the detection of cancer biomarkers and small molecules. Porous silicon substrates are applied in optical biosensors for label-free protein and pathogen detection. Key challenges in this field, including the interaction of silicon with biomolecules, the economic barriers to miniaturization, and issues related to signal stability, are critically analyzed. Proposed strategies to address these challenges and improve sensor functionality and reliability are also discussed. Furthermore, the article explores emerging developments in silicon-based biosensors, particularly their integration into wearable technologies. The pivotal role of artificial intelligence (AI) in enhancing the performance, functionality, and real-time capabilities of these sensors is also highlighted. This review provides a comprehensive overview of the current state, challenges, and future directions in the field of silicon-based biomedical sensing technologies. [ABSTRACT FROM AUTHOR]

This paper presents a low-noise CMOS transimpedance-limiting amplifier (CTLA) for application in LiDAR sensor systems. The proposed CTLA employs a dual-feedback architecture that combines the passive and active feedback mechanisms simultaneously, thereby enabling automatic limiting operations for input photocurrents exceeding 100 µApp (up to 1.06 mApp) without introducing signal distortions. This design methodology can eliminate the need for a power-hungry multi-stage limiting amplifier, hence significantly improving the power efficiency of LiDAR sensors. The practical implementation for this purpose is to insert a simple NMOS switch between the on-chip avalanche photodiode (APD) and the active feedback amplifier, which then can provide automatic on/off switching in response to variations of the input currents. In particular, the feedback resistor in the active feedback path should be carefully optimized to guarantee the circuit's robustness and stability. To validate its practicality, the proposed CTLA chips were fabricated in a 180 nm CMOS process, demonstrating a transimpedance gain of 88.8 dBΩ, a −3 dB bandwidth of 629 MHz, a noise current spectral density of 2.31 pA/√Hz, an input dynamic range of 56.6 dB, and a power dissipation of 23.6 mW from a single 1.8 V supply. The chip core was realized within a compact area of 180 × 50 µm2. The proposed CTLA shows a potential solution that is well-suited for power-efficient LiDAR sensor systems in real-world scenarios. [ABSTRACT FROM AUTHOR]

Chemical sensors, relying on electrical conductance changes in a gas-sensitive material due to the surrounding gas, have the (dis-)advantage of reacting with multiple target gases and humidity. In this work, we report CMOS-integrated SnO2 thin film-based gas sensors, which are functionalized with mono-, bi-, and trimetallic nanoparticles (NPs) to optimize the sensor performance. The spray pyrolysis technology was used to deposit the metal oxide sensing layer on top of a CMOS-fabricated micro-hotplate (µhp), and magnetron sputtering inert-gas condensation was employed to functionalize the sensing layer with metallic NPs, Ag-, Pd-, and Ru-NPs, and all combinations thereof were used as catalysts to improve the sensor response to carbon monoxide and to suppress the cross-sensitivity toward humidity. The focus of this work is the detection of toxic carbon monoxide and a specific hydrocarbon mixture (HCmix) in a concentration range of 5–50 ppm at different temperatures and humidity levels. The use of CMOS chips ensures low-power, integrated sensors, ready to apply in cell phones, watches, etc., for air quality-monitoring purposes. [ABSTRACT FROM AUTHOR]

In recent years Quantum Cellular Automata (QCA) technology has emerged as an ideal option to substitute the current CMOS technology. QCA offers operation in the terahertz range, small area, and low power in nano-scale circuit design. This paper explores the application of quantum dot cellular automata(QCA) technology in efficient floorplanning of digital code converters using the tile based architecture of QCA XOR gate. The proposed code converter circuits exhibits the benefits of low cell count, area, cost and low energy dissipation. The suggested layouts have achieved the 11.42% reduction in cell count, 29.53% reduction in total occupational area,30.93% reduction in cost and 11.52% increase in area utilization factor in comparison to similar counterparts. The functional validity of the suggested designs were validated using QCADesigner 2.0.3 tool. In addition, the energy dissipation analysis were calculated using the QCAPro tool at standard tunelling energy levels o 0.5EK, 1.0EK, 1.5EK. [ABSTRACT FROM AUTHOR]

Full adder circuits are basic digital used in almost all multiplier architectures. Consequently, they serve as the fundamental building blocks in many digital signal or image processing systems. Different logic styles are employed in the design of full adder circuits, with the hybrid logic style being the most recent method for implementing low-power full adders. A hybrid full adder primarily relies on the XOR-XNOR module. This module greatly affects the performance of any hybrid full adder in terms of driving capability, power consumption, delay, and area. This paper proposes a new design of a hybrid full adder by introducing the CCGDI technique-based XOR-XNOR module. Simulation results demonstrate that the proposed CCGDI-based hybrid full adder architecture, constructed with a ratioless 12 transistors, consumes 9.48 µw of power and has a latency of 34.23 ps. A comparison with other state-of-the-art structures of hybrid full adders reveals a significant improvement in PDP (power-delay product) and driving capability. [ABSTRACT FROM AUTHOR]

In embedded applications and digital signal processing systems, multipliers are crucial components. In these applications, there is an increasing need for energy-efficient circuits. We use an approximate adder for error tolerance in the computational process to improve performance and reduce power consumption. Due to human perceptual constraints, computational errors do not significantly affect applications like image, audio, and video processing. Adiabatic logic (AL), which recycles energy, can also be used to build circuits that require less energy. In this work, we propose a carry save array multiplier employing an approximate adder based on CMOS logic and clocked CMOS adiabatic logic (CCAL) to conserve power. Additionally, using a precise full adder, multiplier parameters like average power and power delay product are calculated and compared with the multiplier. We performed simulations using 180 nm technology in Cadence Virtuoso. [ABSTRACT FROM AUTHOR]

A D-band phase shifter for CMOS transmitters in a millimeter-wave imaging system is proposed based on vector modulator configuration. Depending on the phase control biasing, the output impedance variation of phase shifters at the millimeter-wave transmitter can interfere with optimizing the operation of power amplifiers with a fixed input impedance. The proposed phase shifter incorporates an output-matching circuit with transformers to minimize output impedance variations. Differential I and Q channels are coupled in each transformer and combined at the power combiner. This configuration can minimize the impedance variation at the output port and increase the saturated output power of the proposed phase shifter. The proposed phase shifter, implemented on 0.184 mm2 using a 65-nm CMOS process, exhibits a maximum gain of -11 dB, a phase shift of over 180°, and an input-referred P1dB of 7 dBm in the frequency bandwidth of 115-135 GHz. Th e total current consumption is a maximum of 36 mA at a supply voltage of 1.2 V. [ABSTRACT FROM AUTHOR]

This study describes a VDBA (Voltage Differencing Buffered Amplifier)-based memristor emulator and its use in an instrumentation amplifier for biomedical applications. The proposed grounded and floating memristor has been implemented using a single VDBA and grounded MOS-Capacitor. The VDBA used in this article has also been designed and uses eighteen transistors only. The proposed memristor emulator can be operated in both decremental and incremental modes. The suggested emulator's robustness has been verified using a variety of evaluations, including non-ideal inspection, variations of process corner, temperature swings, and non-volatility performance. Using 45 nm CMOS process parameters in the Cadence environment, the layout has been accomplished, and simulations and observations of the theoretical fingerprint characteristics have been made. The incremental and decremental mode of operation for grounded/floating memristor can be easily obtained by modifying the circuit slightly. The shape of the pinched-hysteresis loop is maintained up to 5 MHz. The functionality of the proposed memristor has also been tested by integrating it with the Instrumentation amplifier to amplify weak bio-medical signals.

This paper presents a D-band 16-element phased-array transceiver IC with integrated dual-polarized antenna for 6G wireless communications. Fabricated in 28-nm CMOS, the transceiver operates with five component carriers (5CCs) supporting carrier aggregation in the 138–150 GHz range with 12 GHz bandwidth. The transceiver implements various circuit techniques to overcome the $f_{T}$ limitations of 28-nm CMOS, including differential amplifiers with cross-coupled capacitors and transformer-based inter-stage matching networks. The TX achieves a maximum EIRP of 45.5 dBm with saturated output power and demonstrates EVMs of 5.34-7.2% for 64-QAM signals at 30 Gbps. The RX exhibits less than 8 dB noise figure and achieves EVMs of 5.47-7.21% for 64-QAM signals at 24 Gbps. In over-the-air link testing at 2 m distance, the system achieves less than 4% EVM with both 64- and 256-QAM OFDM signals, representing the best performance reported to date for D-band CMOS implementations. The transceiver IC occupies 29.7 mm2 die area and consumes 3,681 mW and 747 mW for TX and RX operation, respectively.

In this paper, a CMOS Class-J Doherty power amplifier (PA) integrating a Class-G driver and an Impedance-Modulated-Quadrature-Transformer (IMQT) to enhance back-off efficiency for multimode operations is presented. The Class-J Doherty PA utilizes a second harmonic termination to improve its efficiency. To further augment efficiency at deep back-off output power, a single-supply-rail Class-G driver operates with the IMQT, modulating the interstage impedance between the driver and the Doherty stages. The IMQT features a stacked transformer architecture and dynamically adjusts its impedance by switching a floating, intermediate coil between the transformer’s primary and secondary windings. A comparator regulates the IMQT based on the Class-G driver’s operation. The IMQT-DPA, fabricated using a 65nm CMOS process, operates at a center frequency of 28 GHz with a supply headroom of 1.8V. The PA achieves an average output power of 14 dBm with a back-off efficiency of 21%, representing a 1.4-fold efficiency enhancement compared to conventional Class-B operation. Under low-power mode (VDD/2) with a Class-G driver operation, the average output power is 11.3 dBm with a 1.3-fold efficiency improvement.

This work presents dynamic state writing by combining ferroelectric (FE) polarization together with charge injection (CI) on Si-based ferroelectric MOSFETs as a novel approach for non-volatile memory design. FE capacitors are non-destructively integrated in the Back-End-of-Line (BEOL) with Si MOSFETs to create FE-Metal-FETs (FeMFETs). We explore the FE/MOS area ratio (AR) as a critical design parameter, particularly in the context of dynamic writing processes, where various voltage pulse trains are applied for analog potentiation and depression of the memory state. AR significantly influences both the electric field distribution over the FE and the extent of CI from the top electrode. Constant-pulse writing schemes enable analog threshold voltage modulation by considering the AR, with reduced voltages and faster operation for smaller ARs. Retention of intermittent states written by FE polarization combined with CI is demonstrated, illustrating the stability and effectiveness of FeMFET devices and AR optimization for memory applications.