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The research paper represents a novel approach to the design and optimization of a compiler for a domain-specific language (DSL) focused on geometric shape creation and manipulation. The primary objective is to develop a compiler capable of generating efficient machine code while offering users a high level of abstraction. The paper begins with an overview of DSLs and compilers, emphasizing their importance in software development. Next, it outlines the specific requirements of the geometric shape DSL and proposes a compiler design that addresses them. This innovative approach considers DSL's unique features, such as shape creation and manipulation, and aims to generate high-quality machine code. The paper also discusses optimization techniques to enhance the generated code's quality and performance, including loop unrolling and instruction scheduling. These optimizations are particularly suited to the DSL, which focuses on geometric shape creation and manipulation and are integral to achieving efficient machine code generation. In conclusion, the paper emphasizes the novelty of this approach to DSL compiler design and anticipates exciting results from testing the compiler developed for the geometric shape DSL. [ABSTRACT FROM AUTHOR]

Widely used compilers like GCC and LLVM usually have hundreds of optimizations controlled by optimization flags, which are enabled or disabled during compilation to improve the runtime performance (e.g., small execution time) of the compiler program. Due to the large number of optimization flags and their combination, it is difficult for compiler users to manually tune compiler optimization flags. In the literature, a number of autotuning techniques have been proposed, which tune optimization flags for a compiled program by comparing its actual runtime performance with different optimization flag combinations. Due to the huge search space and heavy actual runtime cost, these techniques suffer from the widely recognized efficiency problem. To reduce the heavy runtime cost, in this article we propose a lightweight learning approach that uses a small number of actual runtime performance data to predict the runtime performance of a compiled program with various optimization flag combinations. Furthermore, to reduce the search space, we design a novel particle swarm algorithm that tunes compiler optimization flags with the prediction model. To evaluate the performance of the proposed approach, CompTuner, we conduct an extensive experimental study on two popular C compilers, GCC and LLVM, with two widely used benchmarks, cBench and PolyBench. The experimental results show that CompTuner significantly outperforms the six compared techniques, including the state-of-the-art technique BOCA. [ABSTRACT FROM AUTHOR]

Software solutions to address computational challenges are ubiquitous in our daily lives. One specific application area where software is often used is in embedded systems, which, like other digital electronic devices, are vulnerable to side-channel analysis attacks. Although masking is the most common countermeasure and provides a solid theoretical foundation for ensuring security, recent research has revealed a crucial gap between theoretical and real-world security. This shortcoming stems from the micro-architectural effects of the underlying micro-processor. Common security models used to formally verify masking schemes such as the d-probing model fully ignore the micro-architectural leakages that lead to a set of instructions that unintentionally recombine the shares. Manual generation of masked assembly code that remains secure in the presence of such micro-architectural recombinations often involves trial and error, and is non-trivial even for experts. Motivated by this, we present PoMMES, which enables inexperienced software developers to automatically compile masked functions written in a high-level programming language into assembly code, while preserving the theoretically proven security in practice. Compared to the state of the art, based on a general model for microarchitectural effects, our scheme allows the generation of practically secure masked software at arbitrary security orders for in-order processors. The major contribution of PoMMES is its micro-architecture aware register allocation algorithm, which is one of the crucial steps during the compilation process. In addition to simulation-based assessments that we conducted by open-source tools dedicated to evaluating masked software implementations, we confirm the effectiveness of the PoMMES-generated codes through experimental analysis. We present the result of power consumption based leakage assessments of several case studies running on a Cortex M0+ micro-controller, which is commonly deployed in industry.

Since the last decade to upcoming era the need of machine learning based compilation approaches has become indispensable for every aspect of growing technology especially artificial intelligence and network computing areas. These approaches are used to enhance the result quality by their improved performance as well as handles compiler optimization problems namely optimization selection and phase ordering. It has enthused from a vague research place in middle of the road movement. Wealth of present compiler optimization techniques leads to finding the best heuristic parameters to tune each optimization tactic using machine learning. In this research paper, we highlighted the term machine learning and compiler along with relationship between compiler optimization and machine learning with the identity of the concept of models, training, and approaches.

JavaScript has significantly evolved, broadening its capabilities. However, the uptake of tail call optimization (TCO) remains limited, largely due to concerns about debugging difficulties and the potential increase in overall complexity. This paper highlights the compelling importance of tail calls within web applications, advocating for TCO as a means to boost performance and enhance memory efficiency. We present an innovative TCO technique that leverages the native stack within JavaScript engines, capitalizing on the native stack’s inherent benefits over heap memory. This technique is carefully crafted to comply with diverse TCO standards, prioritizing simplicity and providing debugging features. We tackle the inherent challenges of TCO and successfully deploy our method in a lightweight JavaScript engine. Our approach is rigorously evaluated, proving its effectiveness and practicality. Notably, our implementation facilitates considerable memory savings for web applications, comparable to the maximum Resident Set Size (RSS), and achieves an average performance improvement of approximately 19.8% for algorithms that are heavily recursive. This research not only demonstrates the versatility and efficiency of our TCO strategy but also makes a significant contribution to the wider adoption and comprehension of TCO, thereby improving JavaScript engines’ performance and memory management efficiency.

Approximate computing techniques, such as precision tuning, are widely recognized as key enablers for the next generation of computing systems, where computation quality metrics play an important role. In precision tuning, a trade-off between the accuracy of computations and latency (and/or energy) is established, but identifying the opportunities for applying this approximate computing technique is often challenging. In this article, we compare two different approaches — worst-case static annotation and profile-guided annotation — and their implications when used in a precision tuning framework. To ensure a fair comparison, we implement the profile-guided approach in an existing tool, TAFFO, and experimentally compare it to the original static approach used by the tool. We validate our considerations using the well-known PolyBench/C benchmark suite, and two real-world application case studies. Our findings demonstrate that the profile-guided approach, fed with reasonable profiling data, in addition to needing less expertise to employ, delivers comparable speedup and better accuracy than the static approach.

Brain-inspired computing is a new technology that draws on the principles of brain science and is oriented to the efficient development of artificial general intelligence (AGI), and a brain-inspired computing system is a hierarchical system composed of neuromorphic chips, basic software and hardware, and algorithms/applications that embody this technology. While the system is developing rapidly, it faces various challenges and opportunities brought by interdisciplinary research, including the issue of software and hardware fragmentation. This paper analyzes the status quo of brain-inspired computing systems. Enlightened by some design principle and methodology of general-purpose computers, it is proposed to construct "general-purpose" brain-inspired computing systems. A general-purpose brain-inspired computing system refers to a brain-inspired computing hierarchy constructed based on the design philosophy of decoupling software and hardware, which can flexibly support various brain-inspired computing applications and neuromorphic chips with different architectures. Further, this paper introduces our recent work in these aspects, including the ANN (artificial neural network)/SNN (spiking neural network) development tools, the hardware agnostic compilation infrastructure, and the chip micro-architecture with high flexibility of programming and high performance; these studies show that the "general-purpose" system can remarkably improve the efficiency of application development and enhance the productivity of basic software, thereby being conductive to accelerating the advancement of various brain-inspired algorithms and applications. We believe that this is the key to the collaborative research and development, and the evolution of applications, basic software and chips in this field, and conducive to building a favorable software/hardware ecosystem of brain-inspired computing. [ABSTRACT FROM AUTHOR]

Software developers use a significant amount of time reading and interpreting error messages. However, error messages have often been based on either anecdotal evidence or expert opinion, disregarding novices, who arguably are the ones who benefit the most from effective error messages. Furthermore, the usability aspects of Structured Query Language (SQL) error messages have not received much scientific attention. In this mixed-methods study, we coded a total of 128 error messages from eight database management systems (DBMS), and using data from 311 participants, analysed 4,796 queries using regression analysis to find out if and how acknowledged error message qualities explain SQL syntax error fixing success rates. Additionally, we performed a conventional content analysis on 1,505 suggestions on how to improve SQL error messages, and based on the analysis, formulated a framework consisting of nine guidelines for SQL error message design. The results indicate that general error message qualities do not necessarily explain query fixing success in the context of SQL syntax errors and that even some novel NewSQL systems fail to account for basic error message design guidelines. The error message design framework and examples of its practical applications shown in this study are applicable in educational contexts as well as by DBMS vendors in understanding novice perspectives in error message design. [ABSTRACT FROM AUTHOR]

The continuing prominence of machine learning has led to an increased focus on enhancing the inference performance of edge devices to reduce latency and improve efficiency. Two widely adopted strategies for accelerating computational performance are quantisation and the utilisation of AI hardware accelerators. Each type of accelerator or inference engine offers distinct advantages, with accelerators primarily designed to optimise neural network operations. In this paper, we present an innovative method for integrating TVM's quantisation flow with the MediaTek Neuropilot AI accelerator. We outline the process of converting the TVM relay intermediate-representation quantised neural network dialect model to a tensor-oriented quantisation format, with the aim of harnessing the full potential of both TVM and MediaTek NeuroPilot. This integration enables more efficient neural network inference while preserving the accuracy of the results. We assessed the effectiveness of our proposed integration by conducting a series of experiments and comparing the performance of our approach with that of TVM equipped with an autotuning mechanism. The findings indicate that our approach substantially outperforms TVM in both floating-point model inference and quantised model inference, with inference speedups of up to 11× and up to 70×, respectively. These results underscore the potential of our approach in accelerating AI performance across a diverse range of applications and edge devices. Moreover, a key contribution of our work is providing a valuable practical method for other hardware companies interested in integrating TVM with their own accelerators to achieve performance gains. [ABSTRACT FROM AUTHOR]

In the realm of programming languages, interpreters fundamentally rely on syntax analysis (parsing) for establishing a correct evaluation hierarchy. Traditional parsing methods, however, present limitations in terms of optimization. This study introduces an innovative approach that circumvents syntax analysis in the interpretation of functional programming languages. The proposed method employs a novel subroutine, transforming program expressions into a series of atomic expressions, herein referred to as the "molecular program." Each atomic expression within this molecular program constitutes an element of the program's lexicon, assigned a unique identifier that supplants its role in the original expression. The evaluation process adopts a recursive methodology, where the evaluation of a single variable invariably leads to the sequential evaluation of related variables. For the purposes of clarity and demonstration, this approach is exemplified using Lucid, a notable functional programming language. It is posited that this syntax-free interpretation method can be universally applied to any functional programming language that operates on the principles of expressions, functions, or formulas. The efficacy of this method is validated through rigorous testing, suggesting an enhancement in the efficiency of programming language interpretation. [ABSTRACT FROM AUTHOR]

Agile hardware design is gaining increasing momentum and bringing new chips in larger quantities to the market faster. However, it also takes new challenges for compiler developers to retarget existing compilers to these new chips in shorter time than ever before. Currently, retargeting a compiler backend, e.g., an LLVM backend to a new target, requires compiler developers to write manually a set of target description files (totalling 10 300+ lines of code (LOC) for RISC-V in LLVM), which is error-prone and time-consuming. In this paper, we introduce a new approach, Automatic Target Description File Generation (ATG), which accelerates the generation of a compiler backend for a new target by generating its target description files automatically. Given a new target, ATG proceeds in two stages. First, ATG synthesizes a small list of target-specific properties and a list of code-layout templates from the target description files of a set of existing targets with similar instruction set architectures (ISAs). Second, ATG requests compiler developers to fill in the information for each instruction in the new target in tabular form according to the list of target-specific properties synthesized and then generates its target description files automatically according to the list of code-layout templates synthesized. The first stage can often be reused by different new targets sharing similar ISAs. We evaluate ATG using nine RISC-V instruction sets drawn from a total of 1 029 instructions in LLVM 12.0. ATG enables compiler developers to generate compiler backends for these ISAs that emit the same assembly code as the existing compiler backends for RISC-V but with significantly less development effort (by specifying each instruction in terms of up to 61 target-specific properties only). [ABSTRACT FROM AUTHOR]

Computation-in-memory (CIM) chips offer an energy-efficient approach to artificial intelligence computing workloads. Resistive random-access memory (RRAM)-based CIM chips have proven to be a promising solution for overcoming the von Neumann bottleneck. In this paper, we review our recent studies on the architecture-circuit-technology co-optimization of scalable CIM chips and related hardware demonstrations. To further minimize data movements between memory and computing units, architecture optimization methods have been introduced. Then, we propose a device-architecture-algorithm co-design simulator to provide guidelines for designing CIM systems. A physics-based compact RRAM model and an array-level analog computing model were embedded in the simulator. In addition, a CIM compiler was proposed to optimize the on-chip dataflow. Finally, research perspectives are proposed for future development. [ABSTRACT FROM AUTHOR]

The paper brings forward an idea of multi-threaded computation synchronization based on the shared semaphored cache in the multi-core CPUs. It is dedicated to the implementation of multi-core PLC control, embedded solution or parallel computation of models described using hardware description languages. The shared semaphored cache is implemented as guarded memory cells within a dedicated section of the cache memory that is shared by multiple cores. This enables the cores to speed up the data exchange and seamlessly synchronize the computation. The idea has been verified by creating a multi-core system model using Verilog HDL. The simulation of task synchronization methods allows for proving the benefits of shared semaphored memory cells over standard synchronization methods. The proposed idea enhances the computation in the algorithms that consist of relatively short tasks that can be processed in parallel and requires fast synchronization mechanisms to avoid data race conditions.

A compiler is a system software that takes code written in a high-level language as input and converts it into machine code by selecting the appropriate instructions from the instruction set of the corresponding computer architecture. Thus, depending on this selection process, different conversions with the same functionality are possible. Consequently, there are studies in the literature that compare the performance of different compilers on problems from various domains. However, to the best of our knowledge, no research has yet investigated the impact of different versions of a compiler on the optimization domain. This study seeks to fill this research gap by examining the effects of different versions of GCC on TSP, a well-known combinatorial optimization problem, for the first time in the literature. In this respect, seven different versions of GCC were employed, and four widely used metaheuristics, namely Simulated Annealing, Genetic Algorithm, Tabu Search, and Ant Colony Optimization, were implemented in C++ programming language to solve TSP. The experiments conducted have revealed that different versions of GCC make a significant difference in the performance of various metaheuristic-based solvers for TSP. [ABSTRACT FROM AUTHOR]

Partial control-flow linearization is a code transformation conceived to maximize work performed in vectorized programs. In this article, we find a new service for it. We show that partial control-flow linearization protects programs against timing attacks. This transformation is sound: Given an instance of its public inputs, the partially linearized program always runs the same sequence of instructions, regardless of secret inputs. Incidentally, if the original program is publicly safe, then accesses to the data cache will be data oblivious in the transformed code. The transformation is optimal: Every branch that depends on some secret data is linearized; no branch that depends on only public data is linearized. Therefore, the transformation preserves loops that depend exclusively on public information. If every branch that leaves a loop depends on secret data, then the transformed program will not terminate. Our transformation extends previous work in non-trivial ways. It handles C constructs such as “goto,” “break,” “switch,” and “continue,” which are absent in the FaCT domain-specific language (2018). Like Constantine (2021), our transformation ensures operation invariance but without requiring profiling information. Additionally, in contrast to SC-Eliminator (2018) and Lif (2021), it handles programs containing loops whose trip count is not known at compilation time. [ABSTRACT FROM AUTHOR]

We present a tiny MultiLayer Perceptron (MLP) accelerator named Single Perceptron Linear Vector Processor (SPLVP) that aims at extending the capabilities of limited resources MCUs, enabling inference time speedup and main CPU off-load. It is based on a single perceptron hardware unit, enhanced with an additional accumulation input and scaling features, that is sequentially scheduled to cover all the nodes of the network. The accelerator supports both linear and Rectified Linear Unit (ReLU) activation and its firmware can be generated from 8-bit tflite quantized models. We also present a complete design toolchain that encompasses supervised learning, compilation, assembly, simulation, and device programming. The hardware support for extra accumulation input and scaling, together with the processor memory partitioning, are the key features that enable significant speedups. By solving a toy recognition problem based on image data captured from an infra-red camera, measurements show that the execution speed of SPLVP at 80MHz outperforms an ARM Cortex-M4 STM32L476 microcontroller by a factor of 9.2 when the same ANN is translated to MCU code using the STM CubeMX-Ai converter at the same clock frequency. SPLVP is synthesized on a low-cost and gate-count Cyclone 10 LP FPGA resulting in an 18% logic and 77% memory occupation. The SPLVP assembly code can be directly converted into a VHDL description that directly hardcodes the ANN. The execution speed of an ANN model for Iris classification, fully synthesized, improves by a factor of 209 compared to firmware execution on the MCU. To verify the operation of SPLVP and its design framework, we have designed various tiny Machine Learning (ML) classifiers, for which we briefly discuss the obtained performance and the preprocessing techniques used. Across all these classifiers, the obtained speedup compared to the STM32 is 8.3–14.9 $\times $ .

Noisy intermediate-scale quantum computers are widely used for quantum computing (QC) from quantum cloud providers. Among them, superconducting quantum computers, with their high scalability and mature processing technology based on traditional silicon-based chips, have become the preferred solution for most commercial companies and research institutions to develop QC. However, superconducting quantum computers suffer from fluctuation due to noisy environments. To maintain reliability for every execution, calibration of the quantum processor is significantly important. During the long procedure to calibrate physical quantum bits (qubits), quantum processors must be turned into offline mode. In this work, we propose a real-time calibration framework (RCF) to execute quantum program tasks and calibrate in-demand qubits simultaneously, without interrupting quantum processors. Across a widely used noisy intermediate-scale quantum (NISQ) evaluation benchmark suite such as QASMBench, RCF achieves up to 18% reliability improvement for applications. For reliability on different physical qubits, RCF achieves an average gain of 15.7% (up to 36.7%). For cloud quantum machines, the throughput can be improved up to 9.5 throughput per minute (6.5 on average) based on baseline calibration time. In conclusion, RCF offers a reliable solution for large-scale, long-serving quantum machines.

MVX is one of the most popular active defense technologies. Ideally, when not under attack, the MVX architecture provides normal program functions. Unfortunately, when a multi-threaded program runs in MVX architecture, because different program variants have inconsistent threads execution orders of shared resource operations, different variants will produce state inconsistency and trigger false attack alarm. This problem makes it difficult for multi-threaded programs to run in MVX architecture. This paper proposed a compiler-supported synchronous compilation model for shared resource operations in multi-threaded programs. This model took the shared resource operations as synchronization points, analyzed the timing and mode of shared resource operations in multi-threaded programs. The model ensured the consistency of multiple threads operating on shared resource in different variants at runtime, eliminating the false attack alarms. Based on LLVM 12. 0 compilation framework, this paper designed and implemented a prototype system based on the synchronous compilation model, and conducted simulation experiments on the prototype. The experimental results show that, processed by prototype system, multi-threaded programs have significantly lower false positive rates in MVX architecture. This indicates that,as a universal method, the synchronous compilation model can effectively eliminate the false attack alarms of multi-threaded programs running in MVX architecture, and improve the availability of MVX. [ABSTRACT FROM AUTHOR]

In migrating and upgrading an Ethereum smart contract, it is necessary to transfer both the code as well as the stored data. Various methods attempt to migrate or upgrade a smart contract, but they are mostly manual, error-prone, and applicable only before deployment. Further, they have challenges in extracting the storage state of complex mapping data structures along with their keys. In this work, we present Smartmuv as an automatic source-code-based static analysis tool to analyze and extract the state from the storage-trie of smart contracts. Based on the abstract syntax tree and the control flow graphs of the Solidity source code, the tool analyzes each state variable including mapping types along the inheritance hierarchy. It also provides the upgrade algorithm that initializes the extracted state in the constructor of new smart contract. Smartmuv safely approximates the origin of the keys used in the mapping to extract values and has been able to extract the mapping state of 23,673 smart contracts with 95.7% overall precision. Moreover, we also validate the Smartmuv’s extracted state with the third-party tool Etherscan. [ABSTRACT FROM AUTHOR]

The paper brings forward an idea of multi-threaded computation synchronization based on the shared semaphored cache in the multi-core CPUs. It is dedicated to the implementation of multi-core PLC control, embedded solution or parallel computation of models described using hardware description languages. The shared semaphored cache is implemented as guarded memory cells within a dedicated section of the cache memory that is shared by multiple cores. This enables the cores to speed up the data exchange and seamlessly synchronize the computation. The idea has been verified by creating a multi-core system model using Verilog HDL. The simulation of task synchronization methods allows for proving the benefits of shared semaphored memory cells over standard synchronization methods. The proposed idea enhances the computation in the algorithms that consist of relatively short tasks that can be processed in parallel and requires fast synchronization mechanisms to avoid data race conditions. [ABSTRACT FROM AUTHOR]

The paper addresses the challenge of transmitting a big number of files stored in a data center (DC), encrypting them by compilers, and sending them through a network at an acceptable time. Face to the big number of files, only one compiler may not be sufficient to encrypt data in an acceptable time. In this paper, we consider the problem of several compilers and the objective is to find an algorithm that can give an efficient schedule for the given files to be compiled by the compilers. The main objective of the work is to minimize the gap in the total size of assigned files between compilers. This minimization ensures the fair distribution of files to different compilers. This problem is considered to be a very hard problem. This paper presents two research axes. The first axis is related to architecture. We propose a novel pre-compiler architecture in this context. The second axis is algorithmic development. We develop six algorithms to solve the problem, in this context. These algorithms are based on the dispatching rules method, decomposition method, and an iterative approach. These algorithms give approximate solutions for the studied problem. An experimental result is implemented to show the performance of algorithms. Several indicators are used to measure the performance of the proposed algorithms. In addition, five classes are proposed to test the algorithms with a total of 2350 instances. A comparison between the proposed algorithms is presented in different tables discussed to show the performance of each algorithm. The result showed that the best algorithm is the Iterative-mixed Smallest-Longest-Heuristic (ISL) with a percentage equal to 97.7% and an average running time equal to 0.148 s. All other algorithms did not exceed 22% as a percentage. The best algorithm excluding ISL is Iterative-mixed Longest-Smallest Heuristic (ILS) with a percentage equal to 21,4% and an average running time equal to 0.150 s. [ABSTRACT FROM AUTHOR]

Objectives. Developing the element base of field-programmable gate arrays (FPGA) may significantly affect the design of electronic devices due to the enhanced logical capacity of such chips and the general tendency towards increased subsystem integration. The system-on-a-chip (SoC) concept is aimed at combining receiving, processing, and exchange subsystems onto a single chip, as well as at implementing control, diagnostic, and other auxiliary subsystems. The study aimed at developing a method for soft processor applications, i.e., processors based on configurable logical resources, for implementing control functions in an FPGA-based SoC.Methods. A digital system design methodology was used.Results. For soft processors, a unified design route based on selecting architectural parameters qualitatively corresponding to control tasks was considered. In particular, such parameters as instruction set addressness, number of pipeline cycles, and arithmetic logic unit configuration are adjustable at the design stage to allow the optimization of the soft processor in the discrete parameter space. An approach to rapid prototyping of the assembler based on stack-oriented programming language with regular grammar was also considered. The control of digital signal processing hardware as part of an SoC is the promising application area for soft processors. An implementation is considered on the example of an SoC based on Xilinx Virtex-7 FPGA containing several processor cores developed using the proposed methodology.Conclusions. The considered approaches to soft processor design allow the rapid prototyping of the control processor core for operation as part of an FPGA-based SoC.

As the scale of digital circuit design increases, design and verification using conventional hardware description languages (HDLs), such as verilog-HDL and VHDL, limit efficiency. Consequently, high level synthesis (HLS), as well as domain specific languages (DSLs), which alternates conventional HDLs, are beginning to garner attention. We proposed a design framework that uses the C language as a register transfer level descriptive language. In this study, we introduced a LLVM compiler infrastructure to extend our previous work, support the C/C++ standard as the input code, and aggressively optimize the circuit design. In addition to supporting a single module generation, we extended our framework to support the hierarchical module description for efficient system design. We demonstrated the conversion of the input of C/C++ code into the verilog code, optimize its logic, and construct pipelined logic to achieve the original behavior in multiple clock cycles. Our framework offers a significantly efficient system-level hardware design and a powerful debugging environment with software development platforms and tool-sets. The generated hardware logic performs as well as or better than hand-written logic using conventional HDLs. [ABSTRACT FROM AUTHOR]

This paper introduces BioScript, a domain-specific language (DSL) for programmable biochemistry which executes on emerging microfluidic platforms. The goal of this research is to provide a simple, intuitive, and type-safe DSL that is accessible to life science practitioners. The novel feature of the language is its syntax, which aims to optimize human readability; the technical contributions of the paper include the BioScript type system and relevant portions of its compiler. The type system ensures that certain types of errors, specific to biochemistry, do not occur, including the interaction of chemicals that may be unsafe. The compiler includes novel optimizations that place biochemical operations to execute concurrently on a spatial 2D array platform on the granularity of a control flow graph, as opposed to individual basic blocks. Results are obtained using both a cycle-accurate microfluidic simulator and a software interface to a real-world platform.

Introduction: Privacy concerns arise whenever sensitive data is outsourced to untrusted Machine Learning as a Service (MLaaS) platforms. Fully Homomorphic Encryption (FHE) emerges one of the most promising solutions to implementing privacy-preserving MLaaS. But prior FHE-based MLaaS faces challenges from both software and hardware perspectives. First, FHE can be implemented by various schemes including BGV, BFV, and CKKS, which are good at different FHE operations, e.g., additions, multiplications, and rotations. Different neural network architectures require different numbers of FHE operations, thereby preferring different FHE schemes. However, state-of-the-art MLaaS just naïvely chooses one FHE scheme to build FHE-based neural networks without considering other FHE schemes. Second, state-of-the-art MLaaS uses power-hungry hardware accelerators to process FHE-based inferences. Typically, prior high-performance FHE accelerators consume >160 Watt, due to their huge capacity (e.g., 512 MB) on-chip SRAM scratchpad memories.Methods: In this paper, we propose a software and hardware co-designed FHE-based MLaaS framework, CoFHE. From the software perspective, we propose an FHE compiler to select the best FHE scheme for a network architecture. We also build a low-power and high-density NAND-SPIN and SRAM hybrid scratchpad memory system for FHE hardware accelerators.Results: On average, under the same security and accuracy constraints, on average, CoFHE accelerates various FHE-based inferences by 18%, and reduces the energy consumption of various FHE-based inferences by 26%.Discussion: CoFHE greatly improves the latency and energy efficiency of FHE-based MLaaS.

We present taffo, a framework that automatically performs precision tuning to exploit the performance/accuracy trade-off. In order to avoid expensive dynamic analyses, taffo leverages programmer annotations which encapsulate domain knowledge about the conditions under which the software being optimized will run. As a result, taffo is easy to use and provides state-of-the-art optimization efficacy in a variety of hardware configurations and application domains. We provide guidelines for the effective exploitation of taffo by showing a typical example of usage on a simple application, achieving a speedup up to 60% at the price of an absolute error of 3.53×10−5. taffo is modular and based on the solid llvm technology, which allows extensibility to improved analysis techniques, and comprehensive support for the most common precision-reduced data types and programming languages. As a result, the taffo technology has been selected as the precision tuning tool of the European Training Network on Approximate Computing.

Modern reduced instruction set computer processors are based on a load/store architecture, where all computations are performed on register operands. Compilers therefore allocate registers based on demand, and when occupancy is at maximum, register contents are spilled onto the stack and then retrieved later as data is needed. This phenomenon has security implications that cannot be ignored, as data on the stack is subject to well-known memory corruption attacks. Moreover, works presented so far are mainly targeting protection of pointers to code (e.g., return addresses), but are ineffective for protecting other context data in the stack. This article presents a security solution for spilled registers, generalizing the use of ARM pointer authentication (PA) for this purpose. The protection is enforced by the LLVM compiler via additional compiler passes and modifications. The solution provides guarantees for both integrity and confidentiality protection, and also addressing reuse attack problems associated with PA usage. Experimental data collected demonstrates the effectiveness of the solution against corruption and eavesdropping. We test our solution using SPEC CPU 2017, which confirms the functional viability of our solution. Additionally, we expose real-world performance overhead metrics of our protection design on a ARM-PA-enabled processor. [ABSTRACT FROM AUTHOR]

Hardware acceleration of Artificial Intelligence (AI) workloads has gained widespread popularity with its potential to deliver unprecedented performance and efficiency. An important challenge remains in how AI accelerators are programmed to sustain high utilization without impacting end-user productivity. Prior software optimizations start with an input graph and focus on node-level optimizations, viz. dataflows and hierarchical tiling, and graph-level optimizations such as operation fusion. However, little effort has been devoted to inter-node on-chip scratchpad memory (SPM) management in Deep Learning (DL) accelerators, whose significance is bolstered by the recent trends in complex network topologies and the emergence of eager execution in DL frameworks. We characterize and show that there exists up to a 5.2× performance gap in DL inference to be bridged using SPM management and propose OnSRAM, a novel SPM management framework integrated with the compiler runtime of a DL accelerator. We develop two variants, viz. OnSRAM-Static, which works on static graphs to identify data structures that can be lucratively held on-chip based on their size, liveness and significance, and OnSRAM-Eager, which targets an eager execution model (no graph) and uses a history-based speculative scheme to hold/discard data structures. We integrate OnSRAM with TensorFlow and analyze it on multiple accelerator configurations. Across a suite of 12 images, objects, and language networks, on a 3 TFLOP system with a 2 MB SPM and 32 GBps external memory bandwidth, OnSRAM-Static and OnSRAMEager achieve 1.02-4.8× and 1.02-3.1× reduction in inference latency (batch size of 1), over a baseline with no SPM management. In terms of energy savings, we observe average reductions of 1.51× (up to 4.1×) and 1.23× (up to 2.9×) for the static and eager execution scenarios, respectively. [ABSTRACT FROM AUTHOR]

In the noisy intermediate-scale quantum (NISQ) era, the idea of quantum multiprogramming, running multiple quantum circuits (QCs) simultaneously on the same hardware, helps to improve the throughput of quantum computation. However, the crosstalk, unwanted interference between qubits on NISQ processors, may cause performance degradation when using multiprogramming. To address this challenge, we introduce palloq (parallel allocation of QCs), a novel compilation protocol. Palloq improves the performance of quantum multiprogramming on NISQ processors, while paying attention to 1) the combination of QCs chosen for parallel execution and 2) the assignment of program qubit variables to physical qubits, to reduce unwanted interference among the active set of QCs. We also propose a software-based crosstalk detection protocol using a new combination of randomized benchmarking methods. Our method successfully characterizes the suitability of hardware for multiprogramming with relatively low detection costs. We found a tradeoff between the success rate and execution time of the multiprogramming. Our results will be of value when device throughput becomes a significant bottleneck. Until service providers have enough quantum processors available to more than meet demand, this approach will be attractive to the service providers and users who want to optimize job management and throughput of the processor.

Modern compilers offer many optimization options.It is a complex problem to choose which parameter values,which combination of options and in which order to apply these options.Among them,the optimization phase ordering is the most dif-ficult one.With the improvement of traditional methods (iterative compilation combined with heuristic optimization search) and the emergence of new technologies (machine learning),it is possible to build a relatively efficient and intelligent compiler automatic tuning framework.This paper summarizes the research ideas and application methods of predecessors by investigating the related research in the past decades.Firstly,the development of compiler automatic tuning is introduced,including early manual methods,cost function driven methods,iterative compilation and machine learning-based prediction methods.Then,this paper focuses on the direct prediction based on machine learning and the automatic optimization method of iterative compilation driven by machine learning.Last but not least,several successful frameworks and some recent research results are listed.Current challenges and some key future research directions are also pointed out.