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The studies of band-to-band tunneling (BTBT) nanowire FETs as a possible successor to CMOS FETs and the impact of interconnect parasitics on the performance of BTBT nanowire FETs are presented. The ultra-low-power consumption with reasonable throughput enhanced the BTBT switches that could be used as a promising substitute for the conventional thermal MOSFETs in the deep nanometer regime.

A method is described for isolating different n+ surface anodes of a pixel detector in CMOS technology. The 90-nm standard CMOS test structure with 950-nm-spaced pixels that can be reverse biased with 10 V of relative difference without significant degradation of the dark current has shown the feasibility.

The effect of gate-tunneling leakage in the MOS capacitor on the circuit performance of the phase-locked loop (PLL) in the nanoscale CMOS technology is examined. The MOS capacitors with different oxide thicknesses are used for examining their affect on the PLL performance and the locked time, static phase error and jitter of the second-order PLL are degraded by the gate-tunneling of the MOS capacitor used in the loop filter.

A novel slow-wave transmission line with optimized slot-type floating shields in advanced CMOS technology is described. The results have shown a higher effective relative permittivity value, which is improved by a factor of more than 9, and a better quality factor, which is improved by a factor of more than 6, as compared to conventional transmission lines.

A minimalist MOSFET model is developed that has described the current-voltage (I-V) behavior of short-channel MOSEFTs over the complete region of device operation. The model is used for analyzing the effect of variation of the physical parameters and for technology road-mapping exercises and it can also form the basis of a compact model for circuit simulation with the addition of models relating its parameters to physical device dimensions.

Integrated current-sensing circuits intended for smart-power and embedded applications featuring galvanic isolation are implemented. They are based on magnetic detection using a CMOS-compatible split-drain transistor that provides a very linear output current versus magnetic field. Two approaches are used to generate the magnetic field: the coil approach and the strip approach. In the first, the current to be sensed flows through an integrated coil placed atop the split-drain transistor and produces a magnetic coupling strong enough to cause a detectable current. The second approach features an array of 126 paralleled split-drain transistors placed along a metal strip intended to carry higher current levels. Both techniques were realized as integrated current sensors built in 0.35 [micro]m CMOS technology. The calculated and measured sensitivities were around 1 and 0.75 [micro]A/A for the coil and strip approaches, respectively. For a typical single split-drain bias current of 50 [micro]A, the minimum detectable currents within 1 Hz are 2.8 and 42 [micro]A/[square root of Hz] for the coil and strip approaches, respectively. The strip can carry currents up to 500 mA, whereas the flowing current in the coil is limited to 20 mA. Thus, the choice is based on the resolution and sensing current level of the application. Index Terms--Current measurement, noise correlation, split drain.

This paper reports a tungsten microhotplate fabricated in a standard CMOS process and the implementation of a MicroPirani pressure sensor with it. A monolithic constant-current circuit including an operational amplifier is used to bias the tungsten microhotplate to measure the gas pressure. The sensor shows a linear response to the gas pressure in the range of 1-100 Pa when driven by a constant current of 7 mA. In this regime, the sensitivity of the sensor is 0.23 mV/Pa, the linearity is 4.95%, and the hysteresis is 8.69%. The MicroPirani pressure sensor in this paper can be used in a medium-vacuum measurement. Because tungsten in a standard CMOS process has a large temperature coefficient regardless of the different manufacturing processes, the design of the tungsten microhotplate can be applied to other thermal-based sensors, even in different standard CMOS processes. Index Terms--CMOS pressure sensor, microelectromechanical systems (MEMS), pressure sensor, tungsten microhotplate.

This paper presents compact CMOS quadrature hybrids by using the transformer over-coupling technique to eliminate significant phase error in the presence of low-Q CMOS components. The technique includes the inductive and capacitive couplings, where the former is realized by employing a tightly inductive-coupled transformer and the latter by an additional capacitor across the transformer winding. Their phase balance effects are investigated and the design methodology is presented. The measurement results show that the designed 24-GHz CMOS quadrature hybrid has excellent phase balance within [+ or -] 0.6[degrees] and amplitude balance less than [+ or -] 0.3 dB over a 16% fractional bandwidth with extremely compact size of 0.05 [mm.sup.2]. For the 2.4-GHz hybrid monolithic microwave integrated circuit, it has measured phase balance of [+ or -] 0.8[degrees] and amplitude balance of [+ or -] 0.3 dB over a 10% fractional bandwidth with a chip area of 0.1 [mm.sup.2]. Index Terms--Broadside coupler, directional coupler, even--odd mode theory, phase balance, quadrature hybrid.

A 2.4/5.7-GHz dual-band Weaver-Hartley architecture, using 0.18-[micro]m CMOS technology, is demonstrated in this paper. The 2.4-GHz signal is set to be the image signal when the desired signal is at 5.7 GHz, and vice versa. Since the Weaver and Hartley systems are combined into this architecture, the demonstrated architecture rejects not only the first image signal, but also the secondary image signal. The image-rejection ratios of the first image signal and the secondary image signal are better than 40 and 46 dB, respectively. In this paper, a diagrammatic explanation is employed to obtain the image-rejection mechanisms of the Weaver-Hartley architecture. Index Terms--Divider, Hartley architecture, image rejection, secondary image rejection, Weaver architecture.

A compact and broadband 0.8-77.5-GHz passive distributed drain mixer using standard 0.13-[micro]m CMOS technology is presented in this paper. To extend the operation bandwidth, a uniform distributed topology is utilized for wideband matching. This paper also analyzes the device size and number of stages for the bandwidth of the CMOS distributed drain mixer. To optimize the conversion gain performance of the CMOS drain mixer, a gate bias optimization method is proposed and successfully implemented in the mixer design. This mixer consumes zero dc power and exhibits a measured conversion loss of 5.5 [+ or -] 1 dB from 0.8 to 77.5 GHz with a compact size of 0.67 x 0.58 [mm.sup.2]. The output 1-dB compression point is -8.5 dBm at 20 GHz. To best of our knowledge, this monolithic microwave integrated circuit has the widest operation bandwidth among CMOS wideband mixers to date with good conversion efficiency and zero dc power consumption. Index Terms--CMOS, distributed mixer, drain mixer, millimeter wave (MMW).

This paper presents a planar electronically steerable series-fed patch array for 2.4-GHz industrial, scientific, and medical band applications. The proposed steerable array uses 0[degrees] tunable positive/negative-refractive-index (PRI/NRI) phase shifters to center its radiation about the broadside direction and allow scanning in both directions off the broadside. Using the PRI/NRI phase shifters also minimizes the squinting of the main beam across the operating bandwidth. The tunable PRI/NRI phase shifters employ 0.13-[micro]m CMOS tunable active inductors, as well as varactors in order to extend their phase tuning range and maintain a low return loss across the entire phase tuning range. The feed network of the proposed array uses [lambda]/4 impedance transformers. This allows using identical interstage phase shifters, which share the same control voltages to tune all stages. Furthermore, using the impedance transformers in combination with the CMOS-based constant-impedance PRI/NRI phase shifters guarantees a low return loss for the antenna array across its entire scan angle range. The antenna array was fabricated, and is capable of continuously steering its main beam from -27[degrees] to +22[degrees] off the broadside direction with a gain of 8.4 dBi at 2.4 GHz. This is achieved by changing the varactors' control voltage from 3.5 to 15 V. Across the entire scan angle range, the array return loss is less than -10 dB across a bandwidth of 70 MHz, and the relative sidelobe level is always less than -10 dB. Furthermore, the proposed design achieves very low beam squinting of 1.3[degrees]/100 MHz at broadside and a 1-dB compression point of 4.5 dBm. Index Terms--Electronic beam steering, phased antenna array, positive/negative-refractive-index (PRI/NRI) metamaterial phase shifter, tunable active inductor (TAI).

This paper explores the use of active feedback to boost the transconductance of a common-gate (CG) low-noise amplifier and achieve simultaneous low noise and input power match. Unlike transformer coupled topologies, the CG input stage is dc-coupled to a self-biased common-source feedback amplifier (for [g.sub.m] boosting), thus eliminating the need of external bias circuitry. Noise and intermodulation analysis with and without [g.sub.m] boosting are extensively studied yielding closed-form expressions of the noise figure (NF) and third-order input-referred intercept point (IIP3) that are useful for circuit design and optimization. A 9.6-GHz differential prototype implemented in a 0.18-[micro]m technology using only NMOS transistors, achieves a minimum NF of 4 dB, an IIP3 of -11.3 dBm, a return loss of -17 dB, and a transducer gain of 18 dB while dissipating 10 m (excluding buffer circuit) from a 1.8-V supply voltage. The active chip area is 0.11 [micro][m.sup.2]. Index Terms--CMOS, low-noise amplifier (LNA), noise figure (NF), noise matching, radio frequency integrated circuits (RFICs).

A design methodology and protection strategy for ESD charged-device-model robust digital system via use of scalable postbreakdown transistor macromodel for 90- and 130-nm technologies is presented. The newly designed method and correct-by-construction protection strategy, which is successfully integrated in mainstream product design flow, showed no ESD-CDM damage of core transistor gate oxides.

A low-noise video rate CMOS image sensor based on charge modulation technique for the time-resolved fluorescence lifetime imaging microscopy (FLIM) with subnanosecond time resolution is described. The CMOS image sensor and ultraviolet laser diode as a light source could be used to successfully measure the decaying images and lifetimes of fura-2 solutions having different concentrations.

Spatially-resolved picosecond laser induced transients have been measured in a 0.18 [micro]m CMOS inverter test structure as a function of temperature. Sensitive n-drain and p-drain nodes have been scaled in size to accommodate characteristic differences between ion and laser tracks. Images based on pulse characteristics have been collected from 325 K to 400 K and transient currents extracted from laser strikes to both the OFF drain and its surroundings. With increasing temperature strikes to the OFF drain result in a pulse width which appears to broadens whilst the charge collected surprisingly decreases. Index Terms--CMOS devices, ionizing radiation, lasers, microwave circuits, space radiation effects, temperature effects.

The design of a large-neighborhood cellular nonlinear network (LN-CNN) with propagating connections is proposed. The propagating connections are utilized to achieve large-neighborhood templates in the shape of diamonds. Based on the propagating connections, each LN-CNN cell can only be connected to neighboring cells without interconnections to farther cells. Thus, it is suitable for very large scale integration implementation. The LN-CNN functions of diffusion, deblurring, and Muller-Lyer illusion are successfully verified. Meanwhile, the functions of erosion and dilation are expanded with the diamond-shaped LN templates. Furthermore, the simple N- and P-type synapses stop all the static current paths so that the dc power dissipation can be reduced to only 0.7 mW on standby and 18 mW in operation. An experimental LN-CNN chip with a 20 x 20 array has been fabricated using 0.18-[micro]m CMOS technology. With the proposed LN-CNN chip, more applications and LN-CNN templates can be studied further. Index Terms--Cellular neural networks (CNNs), CMOS, large-neighborhood (LN), propagating connections.

Statistical circuit analysis and optimization are critical for robust nanoscale CMOS design. To accurately perform such analysis, primary process variation sources need to be identified and modeled for further circuit simulation. In this work, a rigorous method to extract process variations from in situ IV measurements is present. Transistor statistics are collected from a test chip fabricated in a 65-nm process. Gate length (L), threshold voltage ([V.sub.th]) and mobility ([mu]) are recognized as the leading variation sources, due to the tremendous process challenges in lithography, channel doping, and the stress engineering. To decompose these variations, three critical IV points from the cut-off and linear regions are identified. The extracted L, [V.sub.th] and [mu] variations are normally distributed, with negligible spatial correlation. By including extracted variations in the nominal model file, accurate prediction of the change of drive current in all operation regions and process corners is achieved. The new extraction method guarantees excellent model matching with hardware for further statistical circuit analysis. Index Terms--Compact modeling, process variation, spatial correlation, threshold voltage variation.

A new equivalent-circuit model for transmission lines and inductors on silicon is proposed. The SPICE-compatible model is suitable for time-domain simulators. It is able to fit the frequency-dependent behavior of the RLGC parameters well into the millimeter-wave range. The model is extracted from electromagnetic simulations with a simple analytic procedure with no need for tuning or optimization. A method for making the model scalable with both line length and width (or inductor diameter) is proposed. Based on this new model, a scalable measurement deembedding methodology is proposed, that can greatly reduce wafer area needed for test and deembedding structures. The fully scalable model results are compared with measurements of devices fabricated in a 90 nm CMOS process. Index Terms--CMOS millimeter-wave integrated circuits, deembedding, inductors, integrated circuit modeling, monolithic microwave integrated circuits (MMICs), scalable models, transmission lines.

A 2.4-5.4-GHz CMOS reconfigurable low-noise amplifier (LNA) is designed. It consists of two stages: a broadband input stage for a steady input matching and noise performance, and a reconfigurable band-selective stage which provides a wide-range frequency tuning from 2.4 to 5.4 GHz and a 12-dB stepped gain with linearity adjustment. The frequency tuning is conducted by a multitapped switching inductor and varactors. Careful design of the switching inductor achieves consistent performance among frequency configurations. The stepped gain and linearity adjustment are provided by a size-switchable transistor with a variable biasing. Fabricated in 0.13[micro]m CMOS technology this LNA exhibits performance including up to 25 dB power gain, 2.2-3.1 dB noise figure and less than 5 mW power consumption under 1 V power supply. Index Terms--Dual reactive feedback, low-noise amplifier (LNA), multistandard, reconfigurable, switching inductor.

A general equivalent-circuit-based method for the de-embedding of scattering parameters is presented. An equivalent circuit representation is used to model the embedding package. The parameters in the models are estimated with a statistical method using measured data from all de-embedding standards jointly together. Hence, it is possible to assess parameter estimates and their variance and covariance due to measurement uncertainties. A general de-embedding equation, which is valid for any five-port with a defined nodal admittance matrix, is derived and used in the subsequent de-embedding of measured device data. Different equivalent circuit models for the embedding network are then studied, and tradeoffs between model complexity and uncertainty are evaluated. Furthermore, the influence of varying number and combinations of de-embedding standards on the parameter estimates is investigated. The method is verified, using both measured and synthetic data, and compared against previously published work. It is found to be more general while keeping or improving accuracy. Index Terms--CMOS, de-embedding, high-frequency measurement, maximum-likelihood estimation, scattering parameters, semiconductor device modeling.

This paper presents the design and results of detailed tests of a CMOS active pixel chip for charged particle detection with in-pixel charge storage for correlated double sampling and readout in rolling shutter mode at frequencies up to 25 MHz. This detector is developed in the framework of R&D for the Vertex Tracker for a future [e.sup.+][e.sup.-] Linear Collider. Index Terms--Monolithic Si pixel sensors.

Single-photon (SPA) and two-photon laser absorption (TPA) techniques are established as reliable, effective methods to study specific single-event (SE) phenomena in advanced CMOS technologies. However, dense metal-fill in these nanoscale processes can prevent the use of top-side SPA in some cases. This paper demonstrates a novel methodology enabling top-side laser SPA single-event effects (SEEs) measurements in the presence of dense metal-fill for a test circuit fabricated in a commercial 90 nm CMOS process and validates it using unimpeded, through-wafer TPA approach. This is achieved by measuring and comparing the SEU thresholds for the sample circuit using both techniques. Index Terms--Complementary metal-oxide-semiconductor (CMOS), laser, metal-fill, single event (SE), single-photon absorption (SPA), two-photon absorption (TPA).

SEUs due to combinational logic in 90 nm CMOS is analyzed at various speeds using a new design approach called the Combinational Circuit for Radiation Effects Self-Test (C-CREST). C-CREST allows the cross-section of combinational logic to be increased while minimizing propagation delay. The design was fabricated in IBM's 9SF CMOS process and underwent broadbeam testing that distinguished combinational logic errors from latch errors. Results confirm that the design is effective in testing combinational logic for SE vulnerabilities with minimum speed penalty. Index Terms--Combinational logic, DICE latch, single event, single event transient, single event upset, window of vulnerability.