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Wearable devices have gained significant popularity for continuous Electrocardiogram (ECG) monitoring due to their compactness and convenience. Day-by-day and 24/7 monitoring without gaps is demanded to promptly detect unusual symptoms that are short-term warning signs of dangerous diseases. Cost-saving criteria are the highest priority to extend the use time of devices and maintain the system operation. However, not all measured signals are useful because the signal quality will be affected by many things such as motion artifacts and muscle noise. Demands on classifying and sending only the usable signal is a requirement, it can save the battery on wearable devices and the expense on the server side (i.e., cloud-based processing), such as storage and processing resources. Therefore, Signal Quality Indices (SQIs) have been developed and researched to determine signal quality to meet the above requirements. This study introduces a novel SQI approach to classify signals. The proposed method has three contributions: 1) exponentially Weighted Mean-Variance (EWMV), a lightweight equation, to identify peaks, followed by applying an adaptive threshold to define peaks that have the same shape as R-peaks; 2) outlier elimination process is proposed to enhance the accuracy; and 3) maximal Overlap Discrete Wavelet Transform (MODWT) is employed to categorize ECG signals into a new class, potentially containing signals relevant to pathological analysis. Experimental results demonstrate that our algorithm achieves the highest sensitivity for both noisy and noiseless data sets. Specifically, it achieved a sensitivity of 99.31% for clean signals and 97.69% for noisy signals. In the case of the PhysioNet challenge data set, while our sensitivity of 96.37% may not be the highest, our accuracy stands out at 95.10%, surpassing other methods recently reviewed. Additionally, our approach demonstrates the lowest trade-off between sensitivity and accuracy among the surveyed SQI techniques.

Substitution boxes (S-Boxes) are essential elements of modern block ciphers, serving as non-linear characteristics that enhance the resistance of these ciphers against cryptanalysis. This research presents a new approach for constructing lightweight S-Boxes that possess strong cryptographic characteristics by combining an enhanced logistic map and an enhanced sine map. The proposed novel algorithm has optimized multiple parameters according to the security threshold set. This study has conducted the most comprehensive evaluation of criteria for S-Boxes to date. The analysis results of the generated $4\times 4$ and $5\times 5$ S-Boxes have achieved optimal criteria in terms of the Strict Avalanche Criterion (SAC) and the Bit Independence Criterion (BIC) that no previous S-Boxes have achieved. Furthermore, parameters related to side-channel attack resistance have been optimized in the design stage of S-Boxes. The constructed S-Boxes with high security can be applied to replace S-Boxes of the same size in existing algorithms or to develop lightweight block cipher algorithms. This research has made a significant contribution to the construction of S-Boxes.

The efficiency of polynomial multiplication execution majorly impacts the performance of lattice-based post-quantum cryptosystems. In this research, we propose a high-speed hardware architecture to accelerate polynomial multiplication based on the Number Theoretic Transform (NTT) in CRYSTAL-Kyber and CRYSTAL-Dilithium. We design a Digital Signal Processing (DSP) architecture for modular multiplication in butterfly and Point-Wise Multiplication (PWM) operations. Our method reduces the critical path delay of an $n$ -bit multiplier to that of a ( $2n$ -2)-bit adder, optimizing both area and speed. These dedicated DSPs are employed in butterfly and PWM operations, completely eliminating the pre-process and post-process of NTT transforms. Furthermore, we introduce a novel unified pipelined architecture for the NTT and Inverse NTT (INTT) transformations of Kyber and Dilithium, with corresponding high-speed (Radix-2) and ultra-high-speed (Radix-4) versions. Lastly, we construct a complete hardware accelerator for polynomial matrix-vector multiplication in Kyber. The Field-Programmable Gate Array (FPGA) implementation results have proven that our designs have significantly improved execution time by $3.4\times $ – $9.6\times $ for the NTT transforms in Dilithium and $1.36\times $ – $34.16\times $ for Kyber polynomial multiplication, compared to previous studies reported to date. Additionally, the hardware footprint results indicate that our proposed architectures exhibit superior hardware performance in Area-Time-Product (ATP), corresponding to a 44%–96% improvement. The proposed architectures are efficient and well-suited for high-performance lattice-based cryptography systems.

In the modern era of the Internet of Things (IoT), especially with the rapid development of quantum computers, the implementation of postquantum cryptography algorithms in numerous terminals allows them to defend against potential future quantum attack threats. Lattice-based cryptography can withstand quantum computing attacks, making it a viable substitute for the currently prevalent classical public-key cryptography technique. However, the algorithm’s significant time complexity places a substantial computational burden on the already resource-limited chip in the IoT terminal. In lattice-based cryptography algorithms, the polynomial multiplication on the finite field is well known as the most time-consuming process. Therefore, investigations into efficient methods for calculating polynomial multiplication are essential for adopting these quantum-resistant lattice-based algorithms on a low-profile IoT terminal. Number theoretic transform (NTT), a variant of fast Fourier transform (FFT), is a technique widely employed to accelerate polynomial multiplication on the finite field to achieve a subquadratic time complexity. This study presents an efficient FPGA-based implementation of number theoretic transform for the CRYSTAL Kyber, a lattice-based public-key cryptography algorithm. Our hybrid design, which supports both forward and inverse NTT, is able run at high frequencies up to 417 MHz on a low-profile Artix7-XC7A100T and achieve a low latency of 1.10μs while achieving state-of-the-art hardware efficiency, consuming only 541-LUTs, 680 FFs, and four 18 Kb BRAMs. This is made possible thanks to the newly proposed multilevel pipeline butterfly unit architecture in combination with employing an effective coefficient accessing pattern.

Internet-of-things networks consist of multiple sensor devices spread over a wide area. In order to protect the data from unauthorized access and tampering, it is essential to ensure secure communication between the sensor devices and the central server. This security measure aims to guarantee authenticity, confidentiality, and data integrity. Unlike traditional computing systems, sensor node devices are often limited regarding memory and computing power. Lightweight communication protocols, such as LoRaWAN, were introduced to overcome these limitations. However, despite the lightweight feature, the protocol is vulnerable to different types of attacks. This proposal presents a highly secure key establishment protocol that combines two cryptography schemes: Elliptic Curve Qu–Vanstone and signcryption key encapsulation. The protocol provides a method to establish a secure channel that inherits the security properties of the two schemes. Also, it allows for fast rekeying with only one exchange message, significantly reducing the handshake complexity in low-bandwidth communication. In addition, the selected schemes complement each other and share the same mathematical operations in elliptic curve cryptography. Moreover, with the rise of a community-friendly platform like RISC-V, we implemented the protocol on a RISC-V system to evaluate its overheads regarding the cycle count and execution time.

In this study, we describe the operation of piezoelectric energy converters and electromechanical modeling of piezoelectric energy harvesting (PEH) devices based on microelectromechanical systems (MEMS) for low-power sensors. Consideration is given to a piezoelectric energy harvester based on standard MEMS. The parameters are determined and optimized using a simple MEMS cantilever model. On top of a Brass substrate, the model uses a single layer of piezoelectric material. We utilized the finite element method (FEM) models created with software tools NanoHUB and COMSOL to analyze the electromechanical behavior of MEMS-based piezoelectric energy harvesting (PEH) devices. The electromechanical modeling was applied to predict the modal and harmonic response of the PEH devices. By using a modal analysis, the resonant frequencies are 182 Hz for the FEM models of the PZT-5H PEH device through NanoHUB and COMSOL. The simulated MEMS can provide a voltage between 1.7 and 1.9 mV, 0.074 µW of output power. The produced voltage and output power may be increased by connecting the piezoelectric layers in parallel and series. And the Internet of Things (IoT) sensors might be driven by this array of devices.

Abstract In modern embedded systems, security issues including side‐channel attacks (SCAs) are becoming of paramount importance since the embedded devices are ubiquitous in many categories of consumer electronics. Recently, deep learning (DL) has been introduced as a new promising approach for profiled and non‐profiled SCAs. This paper proposes and evaluates the applications of different DL techniques including the Convolutional Neural Network and the multilayer perceptron models for non‐profiled attacks on the AES‐128 encryption implementation. Especially, the proposed network is fine‐tuned with different number of hidden layers, labelling techniques and activation functions. Along with the designed models, a dataset reconstruction and labelling technique for the proposed model has also been performed for solving the high dimension data and imbalanced dataset problem. As a result, the DL based SCA with our reconstructed dataset for different targets of ASCAD, RISC‐V microcontroller, and ChipWhisperer boards has achieved a higher performance of non‐profiled attacks. Specifically, necessary investigations to evaluate the efficiency of the proposed techniques against different SCA countermeasures, such as masking and hiding, have been performed. In addition, the effect of the activation function on the proposed DL models was investigated. The experimental results have clarified that the exponential linear unit function is better than the rectified linear unit in fighting against noise generation‐based hiding countermeasure.

With the rising data evolution, the demand for secured communications over networks is rising immensely. Elliptic Curve Cryptography (ECC) provides an attractive solution to fulfill the requirements of modern network applications. Many proposals published over the year over different variants of ECC satisfied some of the issues. Nevertheless, modern network applications such as Internet-of-Thing (IoT) and Software-Defined Networking (SDN) put the requirements on various aspects and can only be solved by different ECC algorithms. Looking at this point of view, an efficient architecture that could combine multiple ECC algorithms becomes an urgent request. In addition, even though many investigations of ECC on Field-Programmable Gate Arrays (FPGA), an efficient architecture that could be well-deployed on Application-Specific Integrated Circuit (ASIC) needs to get more study. Therefore, this paper proposes an area-efficient ECC hardware design that could integrate multiple ECC algorithms. The proposed design is deployed on both ASIC and FPGA platforms. Four well-known ECC-based Digital Signature Algorithms (DSAs), which are the Edwards-curve Digital Signature Algorithm (EdDSA) with Curve25519, Elliptic Curve Digital Signature Algorithm (ECDSA) with National Institute of Standards and Technology (NIST) Curve P-256, P-384, and P-521, are implemented. Furthermore, the design supports all DSA schemes: public-key generation, signature generation, and verification. We also provide optimized calculation flows for modular multiplication, modular inversion, point addition, point doubling, and Elliptic Curve Point Multiplication (ECPM) for two different elliptic curves: the NIST curve and Edward curve, on a unique architecture. The calculation processes are designed in projective coordinates and optimized in time and space to achieve a high level of parallelism. The proposed ECC processor could run up to 102-MHz on ASIC 180-nm and 109.7-MHz on Xilinx Virtex-7. In terms of area, The processor occupies 377,471 gates with 4.87- $mm^{2}$ on the ASIC platform and 11,401 slices on the FPGA platform. The experimental results show that our combinational design achieves area-efficient even when compared with other single-functional architecture on both ASIC and FPGA.

The Number Theoretic Transform (NTT) has been widely used to speed up polynomial multiplication in lattice-based post-quantum algorithms. All NTT operands use modular arithmetic, especially modular multiplication, which significantly influences NTT hardware implementation efficiency. Until now, most hardware implementations used Digital Signal Processing (DSP) to multiply two integers and optimally perform modulo computations from the multiplication product. This paper presents a customized Lattice-DSP (L-DSP) for modular multiplication based on the Karatsuba algorithm, Vedic multiplier, and modular reduction methods. The proposed L-DSP performs both integer multiplication and modular reduction simultaneously for lattice-based cryptography. As a result, the speed and area efficiency of the L-DSPs are 283 MHz for 77 SLICEs, 272 MHz for 87 SLICEs, and 256 MHz for 101 SLICEs with the parameters q of 3329, 7681, and 12,289, respectively. In addition, the N−1 multiplier in the Inverse-NTT (INTT) calculation is also eliminated, reducing the size of the Butterfly Unit (BU) in CRYSTAL-Kyber to about 104 SLICEs, equivalent to a conventional multiplication in the other studies. Based on the proposed DSP, a Point-Wise Matrix Multiplication (PWMM) architecture for CRYSTAL-Kyber is designed on a hardware footprint equivalent to 386 SLICEs. Furthermore, this research is the first DSP designed for lattice-based Post-quantum Cryptography (PQC) modular multiplication.

Information security is a fundamental and urgent issue in the digital transformation era. Cryptographic techniques and digital signatures have been applied to protect and authenticate relevant information. However, with the advent of quantum computers and quantum algorithms, classical cryptographic techniques have been in danger of collapsing because quantum computers can solve complex problems in polynomial time. Stemming from that risk, researchers worldwide have stepped up research on post-quantum algorithms to resist attack by quantum computers. In this review paper, we survey studies in recent years on post-quantum cryptography (PQC) and provide statistics on the number and content of publications, including a literature overview, detailed explanations of the most common methods so far, current implementation status, implementation comparisons, and discussion on future work. These studies focused on essential public cryptography techniques and digital signature schemes, and the US National Institute of Standards and Technology (NIST) launched a competition to select the best candidate for the expected standard. Recent studies have practically implemented the public key encryption/key encapsulation mechanism (PKE/KEM) and digital signature schemes on different hardware platforms and applied various optimization measures based on other criteria. Along with the increasing number of scientific publications, the recent trend of PQC research is increasingly evident and is the general trend in the cryptography industry. The movement opens up a promising avenue for researchers in public key cryptography and digital signatures, especially on algorithms selected by NIST.

True Random Number Generator (TRNG) provides the different keys for device authentication and cryptography. Typically, the TRNG is implemented in a standalone module into the systems, increasing the complexity and area of the implementation. In addition, the system needs to store the key generated by the TRNG in non-volatile memory for the different applications. However, implementing a Non-Volatile Random Access Memory (NVRAM) requires additional technology features, usually unavailable or expensive. This paper presents a unified NVRAM-TRNG in a $0.18\mu m$ standard CMOS technology without an additional mask or fabrication steps. The unified implementation does not need additional circuits for the random number generation mode. The differential NVRAM bit cell is implemented using a high voltage transistor to resist the non-volatile memory application. The NVRAM presents times of 15-ms of programming and erasing and 20-ns of reading functions. The bit cell needs a voltage of 8.5-V for the programming and erasing functions. The TRNG implemented passes the NIST SP800-22 statistical test and NIST SP800-90B entropy test with a 0.9859 minimum entropy. The entropy and statistical test are applied with Process, Voltage, and Temperature (PVT) variations. The implementation occupies a 476- $\mu m^{2}$ with 14.69- $10^{3} F^{2}$ of area normalized. Besides, the NVRAM bit cell in TRNG mode shows a bit rate of 50-Mbps. Finally, the implementation as TRNG reports a 49.5- $\mu W$ power consumption with 0.99-pJ/bit energy efficiency, respectively.

True Random Number Generator (TRNG) is used in many applications, generally for generating random cryptography keys. In this way, the trust of the cryptography system depends on the quality of the random numbers generated. However, the entropy fluctuations produced by external perturbations generate some false positives in the random sequence. These false positives can generate a disastrous scenario, depending on the application. This work presents the results of different tests to demonstrate the robustness and health of the TRNG based on frequency collapse. The TRNG passed all entropy tests provided for NIST SP800-90B and AIS31. The entropy test denotes a 0.9789 minimum normalized entropy and 7.998 Shannon entropy. In addition, the TRNG passes the health tests provided for NIST SP800-90B. The health test shows a number of identical values $I_{v}=0\%$ , $I_{v-1} < 0.004\%$ and a maximum cutoff value $MC_{v}=10$ with $LMC_{v}=13$ in the repetition count and adaptive proportion tests, respectively. The implementation passed all the statistical tests provided for NIST SP800-22 and AIS20. Besides, the implementation passes the different tests with Process, Voltage, and Temperature (PVT) variations. The TRNG is implemented in a $0.18~\mu m$ General Purpose (GP) CMOS technology, occupying $25600~\mu m^{2}$ with four entropy sources. Finally, the implementation presents a 7.3 until 9.2-Mb/s of bit rate, 0.56 until 1.88-mW of power consumption, and 77.2 until 204.3-pJ/bit of energy per bit using an entropy source with 16 and 2 delay stages, respectively.

A Trusted Execution Environment (TEE) sets a platform to secure applications based on the Chain-of-Trust (CoT). The starting point of the CoT is called the Root-of-Trust (RoT). However, the RoT implementation often relies on obscurity and provides little flexibility when generating keys to the system. In this paper, a TEE System-on-a-Chip (SoC) architecture is proposed based on a heterogeneous design by combining 64-bit Linux-capable processors with a 32-bit Micro-Controller Unit (MCU). The TEE is built on the 64-bit cores, while the 32-bit MCU takes care of sensitive data and activities. The MCU is isolated from the TEE side by an Isolated Bus (IBus) that sits above the conventional System Bus (SBus). Besides the 32-bit processor, the isolated sub-system contains a Random Access Memory (RAM), a Read-Only Memory (ROM) for storing the boot program, and another ROM for storing root keys. For cryptography accelerators, we have 512-bit Secure Hashing Algorithm 3 (SHA3-512), 128/256-bit Advanced Encryption Standard (AES-128/256), Ed25519, and True Random Number Generator (TRNG) attached to the Peripheral Bus (PBus). Additionally, besides the public channel, the TRNG module also has a private channel that goes directly to the IBus. With RoT implemented inside the isolated sub-system, the RoT is inaccessible from the TEE side after boot. Furthermore, the hidden MCU’s secure boot program makes the key generation flexible and could be updated for many security schemes. To summarize, the proposed design features a flexible and secure boot procedure with complete isolation from the TEE domain. Moreover, exclusive secure storage for the root key and cryptographic accelerators are available for the boot process. The implementation was tested on a Virtex-7 XC7VX485T Field-Programmable-Gate-Array (FPGA). It was also synthesized in a Very Large-Scale Integrated (VLSI) circuit with the ROHM-180nm process library.

Side channel attack (SCA) is a class of crypt-analytic attacks for security evaluation of cryptographic and embedded microprocessor implementations. Among several SCA approaches, the correlation power analysis (CPA) is an efficient way to recover the secret key of the specific cryptographic algorithms running on the target devices such as embedded microprocessors. However, the evaluation process is time-consuming since a large number of traces are required to overcome the impact of noise. Hence, this paper proposes new methods to reduce the computation time by using Point of Interest (POI) extractor with the power trace biasing technique and the correlation distribution for the low complexity correlation power analysis (CPA). The theoretical explanations are provided and the experiments on different platforms such as ASCAD and RISC-V processor based databases are conducted to justify the proposed techniques. Especially, our experiments are performed with different protected schemes such as masking, hiding and combined hiding-masking techniques. The experimental results indicate that our proposed methods provide reliable results in comparison with the standard CPA. By using only a half of the power traces for taking the POIs, our first proposal not only decreases the execution time approximately by half but also enhances the success rate of the attack. Moreover, the second method based on power trace biasing technique is proposed in order to achieve better results and reduce the number of traces needed for selecting the POIs. With only 28.9% of given power traces needed, our second proposed technique reduces the execution time to only 2.6 times of the standard CPA.

The security of Internet of Things (IoTs) devices in recent years has created interest in developing implementations of lightweight cryptographic algorithms for such systems. Additionally, open-source hardware and field-programable gate arrays (FPGAs) are gaining traction via newly developed tools, frameworks, and HDLs. This enables new methods of creating hardware and systems faster, more simply, and more efficiently. In this paper, the implementation of a system-on-chip (SoC) based on a 32-bit RISC-V processor with lightweight cryptographic accelerator cores in FPGA and an open-source integrating framework is presented. The system consists of a 32-bit VexRiscv processor, written in SpinalHDL, and lightweight cryptographic accelerator cores for the PRINCE block cipher, the PRESENT-80 block cipher, the ChaCha stream cipher, and the SHA3-512 hash function, written in Verilog HDL and optimized for low latency with fewer clock cycles. The primary aim of this work was to develop a customized SoC platform with a register-controlled bus suitable for integrating lightweight cryptographic cores to become compact embedded systems that require encryption functionalities. Additionally, custom firmware was developed to verify the functionality of the SoC with all integrated accelerator cores, and to evaluate the speed of cryptographic processing. The proposed system was successfully implemented in a Xilinx Nexys4 DDR FPGA development board. The resources of the system in the FPGA were low with 11,830 LUTs and 9552 FFs. The proposed system can be applicable to enhancing the security of Internet of Things systems.

Fully depleted silicon-on-insulator (FD-SOI) technology is renowned for its back-gate bias voltage controllability. It allows devices fabricated with FD-SOI technology to be optimized for low power consumption or high performance with proper back-gate biases, depending on the required application. This article proposes using the back-gate biasing technique in novel countermeasures against power analysis attacks. Theoretical explanations are discussed, and realistic differential power analysis (DPA) attacks, targeting AES-128 encryption on a 65-nm STOB 32-bit RISC-V microcontroller, are conducted to justify the proposed idea. The experimental results show that when compared with applying no bias, applying our first proposal, which involves using forward back-gate bias, not only improves the test device performance but also enhances its resistance to DPA attacks. Moreover, vulnerability to DPA attacks is kept unchanged when a reverse back-gate bias is applied to achieve low power consumption. The DPA resistance is even more vital when combining the back-gate bias technique with a lower supply voltage. The number of power traces required to retrieve the secret key successfully increases by 14.5 times in the best case. Even better DPA resistance can be obtained when the back-gate bias of the targeted microcontroller is dynamically randomized, as suggested by our second proposal of a random dynamic back-gate bias (RDBB). When RDBB is applied, the number of power traces required to retrieve the secret key successfully significantly increases by 33.4 times.

All cryptography systems have a True Random Number Generator (TRNG). In the process of validating, these systems are necessary for prototyping in Field Programmable Gate Array (FPGA). However, TRNG uses an entropy source based on non-deterministic effects challenging to replicate in FPGA. This work shows the problems and solutions to implement an entropy source based on frequency collapse in multimodal Ring Oscillators (RO). The entropy source implemented in FPGA pass all SP800-90B tests from the National Institute of Standards and Technology (NIST) with a good entropy compared to related works. The TRNG passes all NIST SP800-22 with and without the post-processing stage. Besides, the TRNG and the post-processing stage pass all tests of Application notes and Interpretation of the Scheme (AIS31). The TRNG implementation on a Xilinx Artix-7 XC7A100TCSG324 FPGA occupies less than 1% of the resources. This work presents $0.62~\mu \text{s}$ up to $9.92~\mu \text{s}$ of sampling latency and 1.1 Mbps up to 9.1 Mbps of bit rate throughput.

Cryptographic System-on-Chips (SoCs) are becoming more and more popular. In these systems, cryptographic accelerators are integrated with processor cores to provide users with the software’s flexibility and hardware’s high performance. First, this work aimed to confirm the vulnerability of cryptographic SoCs against several types of power analysis attacks. Then, the novel Random Dynamic Frequency Scaling (RDFS) countermeasure is proposed to improve the resistance of such systems. The proposed RDFS countermeasure improved the power analysis resistance while maintaining low-performance overhead and hardware costs by generating more than 219,000 distinct frequencies for driving only the cryptographic accelerators. The effectiveness of the proposed RDFS countermeasure is demonstrated by conducting realistic Correlation Power Analysis (CPA) attacks, Deep-Learning-based Side-Channel Analysis (DL-SCA) attacks, and Test Vector Leakage Assessment (TVLA) testing methodology. The experimental results show that the RISC-V SoC protected by RDFS countermeasure can withstand CPA attacks and TVLA test with more than five million power traces, which is the best result compared to other related works. The proposed RDFS countermeasure also harden the targeted RISC-V SoC’s resistance against DL-SCA attacks.

Computer designers have included techniques such as speculative execution and caching to optimize speed and performance. Unfortunately, they could be exploited by the recently discovered cache-side channel attack, spectre. The purpose of this research is to resolve this problem on the open-source RISC-V architecture. Previously, software mitigation techniques and hardware modifications have been investigated on Intel or ARM system to address these issues. However, they are either difficult to implement or have resulted in a significant loss of performance. This work presents a real-time detection approach for cache side-channel attacks such as spectre on the RISC-V processor. By monitoring the CPU’s cache activity with Hardware Performance Counters and analyzing the gathered data with a neural network, we extend previous researches in the field of cache side-channel identification. Since cache side-channels frequently result in a significantly altered cache usage pattern, the proposed multi-layer perceptron network can detect an attack event with an accuracy greater than 99% in our test environment with low performance overhead. This is the first time, to our knowledge, that a spectre attack on the RISC-V architecture has been detected in run-time via hardware events and machine learning.

The Trusted Execution Environment (TEE) offers a software platform for secure applications. The TEE offers a memory isolation scheme and software authentication from a high privilege mode. The procedure uses different algorithms such as hashes and signatures, to authenticate the application to secure. Although the TEE hardware has been defined for memory isolation, the security algorithms often are executed using software implementations. In this paper, a RISC-V system compatible with TEEs featuring security algorithm accelerators is presented. The hardware accelerators are the SHA-3 hash and the Ed25519 elliptic curve algorithms. TileLink is used for the communications between the processor and the register of the accelerators. For the TEE boot, the software procedures are switched with the accelerated counterpart. Comparing to the software approach, a 2.5-decade increment is observed in the throughput of the signature procedure using the SHA-3 acceleration for big chunks of data. The Ed25519 performs 90% better compared to the software counterpart in execution times.

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it.

Hardware acceleration of cryptography algorithms represents an emerging approach to obtain benefits in terms of speed and side-channel resistance compared to software implementations. In addition, a hardware implementation can provide the possibility of unifying the functionality with some secure primitive, for example, a true random number generator (TRNG) or a physical unclonable function (PUF). This paper presents a unified PUF-ChaCha20 in a field-programmable gate-array (FPGA) implementation. The problems and solutions of the PUF implementation are described, exploiting the metastability in latches. The Xilinx Artix-7 XC7A100TCSG324-1 FPGA implementation occupies 2416 look-up tables (LUTs) and 1026 flips-flops (FFs), reporting a 3.11% area overhead. The PUF exhibits values of 49.15%, 47.52%, and 99.25% for the average uniformity, uniqueness, and reliability, respectively. Finally, ChaCha20 reports a speed of 0.343 cycles per bit with the unified implementation.

Transport Layer Security (TLS) provides a secure channel for end-to-end communications in computer networks. The ChaCha20–Poly1305 cipher suite is introduced in TLS 1.3, mitigating the sidechannel attacks in the cipher suites based on the Advanced Encryption Standard (AES). However, the few implementations cannot provide sufficient speed compared to other encryption standards with Authenticated Encryption with Associated Data (AEAD). This paper shows ChaCha20 and Poly1305 primitives. In addition, a compatible ChaCha20–Poly1305 AEAD with TLS 1.3 is implemented with a fault detector to reduce the problems in fragmented blocks. The AEAD implementation reaches 1.4-cycles-per-byte in a standalone core. Additionally, the system implementation presents 11.56-cycles-per-byte in an RISC-V environment using a TileLink bus. The implementation in Xilinx Virtex-7 XC7VX485T Field-Programmable Gate-Array (FPGA) denotes 10,808 Look-Up Tables (LUT) and 3731 Flip-Flops (FFs), represented in 23% and 48% of ChaCha20 and Poly1305, respectively. Finally, the hardware implementation of ChaCha20–Poly1305 AEAD demonstrates the viability of using a different option from the conventional cipher suite based on AES for TLS 1.3.

In cryptography, elliptic curve cryptography (ECC) is considered an efficient and secure method to implement digital signature algorithms (DSAs). ECC plays an essential role in many security applications, such as transport layer security (TLS), internet protocol security (IPsec), and wireless sensor networks (WSNs). The proposed designs of ECC hardware implementation only focus on a single ECC variant and use many resources. These proposals cannot be used for resource-constrained applications or for the devices that need to provide multiple levels of security. This work provides a multi-functional elliptic curve digital signature algorithm (ECDSA) and Edwards-curve digital signature algorithm (EdDSA) hardware implementation. The core can run multiple ECDSA/EdDSA algorithms in a single design. The design consumes fewer resources than the other single-functional design, and is not based on digital signal processors (DSP). The experiments show that the proposed core could run up to 112.2 megahertz with Virtex-7 devices while consuming only 10,259 slices in total.

In image compression and video coding, quantization error helps to reduce the amount of information ofthe high frequency components. However, in temporal prediction the quantization error contributes its valueas noise in the total residual information. Therefore, the residual signal of the inter-picture prediction isgreater than the expected one and always differs zero value even input video contains only homogeneousframes. In this paper, we reveal negative effects of quantization errors in inter prediction and propose a videoencoding scheme which is able to avoid side effects of quantization errors in the stationary parts. We proposeto implement a motion detection algorithm as the first stage of video encoding to separate the video into twoparts: motion and static. The motion information allows us to force residual data of non-changed part to zeroand keep the residual signal of motion regularly. Beside, we design block-based filters which improve motionresults and filter those results fit into block encode size well. Fixed residual data of static information permitsus to pre-calculate its quantized coefficient and create a bypass encoding path for it. Experimental resultswith the JPEG compression (MJPEG-DPCM) showed that the proposed method produces lower bitrate thanthe conventional MJPEG-DPCM at the same quantization parameter and a lower computational complexity.

Bitmap index is recognized as a promising candidate for online analytics processing systems, because it effectively supports not only parallel processing but also complex and multi-dimensional queries. However, bitmap index creation is a time-consuming task. In this paper, by taking full advantage of massive parallel computing of field-programmable gate array (FPGA), two hardware accelerators of bitmap index creation, namely BIC64K8 and BIC32K16, are originally proposed. Each of the accelerator contains two primary components, namely an enhanced content-addressable memory and a query logic array module, which allow BIC64K8 and BIC32K16 to index 65 536 8-bit words and 32 768 16-bit words in parallel, at every clock cycle. The experimental results on an Intel Arria V 5ASTFD5 FPGA prove that at 100 MHz, BIC64K8 and BIC32K16 achieve the approximate indexing throughput of 1.43 GB/s and 1.46 GB/s, respectively. The throughputs are also proven to be stable, regardless the size of the data sets. More significantly, BIC32K16 only consumes as low as 6.76% and 3.28% of energy compared to the central-processing-unit- and graphic-processing-unit-based designs, respectively.

Central processing unit (CPU) and graphics processing unit (GPU) are weak (“weak” means inefficiency) at detecting information represented by search, reference and recognition for reason of computer architecture. The memorism processor is a memory base processor which complements CPU's weak point. The two memorism processors called set operating processors (SOP) and database processors (DBP) are the device technology that covers the processing that CPUs and GPUs are not good at. Their profitability in various information processing including rapidity and energy saving performance has been proved and therefore there are great expectations for them as a device technology in the post-Moore era. In addition to the conventional SOPs and DBPs, we have developed cross operating processors (XOP), which are excellent at combination/comparison operation and therefore we have applied for a patent of it. These three memorism processors are expected to play a great role in the evolution of the artificial intelligence. This paper is contributed as continuation of [K. Inoue, M. Odaka and C.-K. Pham: Memorism Processor which complements weak point of von Neumann processor, Proc. SII2016, pp. 267-270, 2016], and the authors propose computation that is more suitable for the artificial intelligence era.