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This work presents a reconfigurable-band analog filter capable of performing the low-pass, high-pass, band-pass or all-pass functions. The proposed filter is a simple and compact cell composed of only two RC networks and one differential Operational Transconductance Amplifier (OTA). To select the desired filter type, two configurations must be done: 1) the two RC network shall be configured as low-pass/low-pass, high-pass/high-pass or low-pass/high-pass, 2) the input signals must be fed in differential or single mode. To validate theory and simulations, the proposed reconfigurable-band filter was designed, fabricated and measured to meet the biomedical band (0.1 Hz - 10 kHz) in a $0.5 ~\mu \text{m}$ CMOS standard fabrication process. To achieve the extremely low RC time constants imposed by the biomedical band, the R element was implemented using PMOS high-value programmable resistor. The prototype exhibits a silicon area of $470 ~\mu \text{m}$ x $250 ~\mu \text{m}$ and a power consumption of $96.32 ~\mu \text{W}$ using a ± 0.8 V symmetric power supply. Due to this circuit’s ability to perform four filter-functions, its operation band can be tuned over five decades, its power consumption is in the nano and micro-watt regime, and it is area compact, the proposed analog filter is a suitable candidate for being an analog standard-cell.

Manufacturing yield, overkill, and defect level can limit the feasibility of analog circuits in SoCs. The conventional method of handling process and environmental variation is to assign the design margin such that the design meets specifications at several processes and environmental corners. However, checking only a few extreme corners limits performance more than the more rigorous statistical approach of computing manufacturing and quality figure of merit. On the other hand, the statistical approach requires transistor level simulation of hundreds or thousands of samples, not just a few corners, and hence is very time-consuming. This paper gives a way to sidestep the problem by characterizing each of many samples of building blocks once at the transistor level. The building blocks are scalable so that statistics are preserved when a building block is adjusted to the requirement of a higher level design. Many design scenarios may be rapidly explored by assembling and scaling the building block samples without SPICE simulation. A continuous-time low-pass filter design example is used to extract the requirements of the building block approach. The requirements include a method to assemble building blocks (biquad element for the example) into a filter design while preserving the statistics that would have been extracted by simulation of the entire filter at the transistor level. The assembly method for both linear and nonlinear response is proposed.

A method for the design of a noise transfer function (NTF) is presented in which the stopband of a continuous‐time high‐pass filter with monotonic passband characteristics is minimised by optimally placing an arbitrary number of imaginary‐axis zeros. Towards this end, the Papoulis, Halpern, and least‐squares monotonic polynomials have been used in the high‐pass filter design. The NTF is derived by applying the bilinear transformation on a continuous‐time high‐pass filter that minimises the in‐band energy and satisfies all the realisability constraints of a Delta‐Sigma modulator (DSM). By way of examples, it is shown that the signal‐to‐quantisation noise ratio achieved by the NTF designed by the proposed method is higher than that obtained by the NTF designed using a recently published method. The signal‐to‐noise ratio of the NTF designed with the proposed method is higher for a wide range of signal amplitude. [ABSTRACT FROM AUTHOR]

A novel auto-tuning method for the integrated continuous-time filter is proposed in this paper. On the one hand, an off-chip digital controller is adopted here to decrease the on-chip hardware as well as to increase the efficiency and the flexibility of the auto-tuning strategy. As a result, both the calibration and the programmability of the cut-off frequency can be realized by software, meanwhile some non-idealities of the circuit can also be compensated by software. On the other hand, the on-chip auto-tuning circuit is designed based on the master-slave architecture, where a novel and simple master circuit is adopted with digital input and output interfaces, thus providing convenient connections for the controller without the ADC or DAC devices. With the PCB technology, a 6th-order active-RC filter with the proposed auto-tuning method is also implemented to verify the validity and the flexibility of this method. [ABSTRACT FROM AUTHOR]

SUMMARY This paper presents an ultra-low-power fourth-order bandpass operational transconductance amplifier-C (OTA-C) filter for an implantable cardiac microstimulator used to detect the R-wave of intracardiac electrograms. The OTA-C filter fabricated by TSMC 0.35-µm complementary metal-oxide-semiconductor (CMOS) technology is operated in the subthreshold region to save power under a supply voltage of 1 V. The current cancellation technique is adopted to reduce the transconductance of the amplifier. Through this, the low-frequency OTA-C filter can be realized by ultra-low transconductance with on-chip capacitors. Direct comparison to conventional RLC ladders replaced by OTA-C circuits shows that the method of reducing the number of OTAs further diminishes power consumption. Design issues, including ultra-low transconductance, linearity, and noise, are also discussed. Measurement results show that the low-voltage, low-power filter has a bandwidth between 10 and 50 Hz, third inter-modulation distortion of −40 dB, dynamic range of 43 dB, and power consumption of only 12 nW. The real electrocardiography signal is fed into the bandpass filter to verify the function of signal processing with the distribution of the R-wave. Copyright © 2012 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

New circuit design techniques for implementing very high-valued resistors are presented, significantly improving power and area efficiency of analog front-end signal processing in ultra-low power biomedical systems. Ranging in value from few hundreds of $$\hbox{M}\Upomega$$ to few hundreds of $$\hbox{G}\Upomega$$, the proposed floating resistors occupy a very small area, and produce accurately tunable characteristics. Using this approach, a low-pass MOSFET-C filter with tunable cutoff frequency ( f = 20 Hz-184 kHz) has been implemented in a conventional 0.18 μm CMOS technology. Occupying 0.045 mm/pole, the power consumption of this filter is 540 pW/Hz/pole with a measured IMFDR of 70 dB. [ABSTRACT FROM AUTHOR]

In this paper, an inverter based transconductor using double CMOS pair is proposed for implementation of a reconfigurable analog baseband block consisting of a variable gain amplifier (VGA) and a second order lowpass G-C filter. The centre frequency of the filter is varied using current steering DAC. Major contributions of this paper are: proposal for operating the transconductance (G) stage and current steering DAC in sub-threshold region in order to minimize the power dissipation, design of variable gain amplifier (VGA) using switched G cells with dummy stages, proposal for a digital tuning technique for the filter based on phase comparison method for compensation against process, voltage and temperature variations. The proposed analog baseband block is designed and implemented on TSMC-0.18 μm CMOS process with 1.8 V supply using g/I design methodology. The post layout simulation results demonstrate the tunability of the centre frequency from 100 KHz to 20 MHz which meets the requirements of zero IF receivers for SDR applications. The third order input intercept point (IIP3) is found to be 15 dBVp for an input signal of 100 mVp. The power dissipated by the baseband block is 1 mW and 5 mW at 100 KHz and 20 MHz respectively and it requires silicon area of 0.173 mm. The SFDR over the entire bandwidth is 58 dB. The proposed approach guarantees the upper bound on THD to be-40 dB for 300 mVpp signal swing. The use of inverters with double CMOS pair results in 34 dB higher PSRR compared to those using push pull inverter. [ABSTRACT FROM AUTHOR]

A dispersion tolerant receiver for fiber-optic links, in 0.18 µm SiGe BiCMOS, implements a Class-2 partial response maximum likelihood (PRML) equalization entirely in the analog domain. Post-FEC error free operation is achieved with data received from over 400 Km of uncompensated single mode fiber (SMF). The 4.5WASIC operates at up to 11.1 Gb/s and includes a variable gain amplifier (VGA) with automatic gain control (AGC), a 1.5-3.5 GHz programmable continuous-time filter (CTF), a 5-tap sampled-time finite-impulse response (FIR) filter, a decision directed timing recovery, and a 4-state analog Viterbi detector implementation. The receiver is compliant with XFI jitter specifications for Telecom applications (SONET OC-192 and G.709 "OTU-2"). [ABSTRACT FROM AUTHOR]

This paper presents a 100-kHz fifth-order Chebychev tow-pass filter (LPF) using the proposed dynamic biasing (DB) technique which enables wide dynamic range under a low-supply voltage. The change of state variables in the internal nodes of the filter can be corrected by using a novel simplified scheme, avoiding the output transient owing to dynamic biasing. The filter, including an automatic frequency tuning system based on the voltage-controlled-filter (VCF) architecture and voltage reference circuit, is fabricated in a 0.18-μm standard CMOS technology with a 0.5-V threshold voltage and consumes 443 μW from a power supply of 0.6 V. The output noise and the in-band IIP3 are 575 PArms and 219 μA, respectively. The filter achieves a dynamic range of 89 dB. [ABSTRACT FROM AUTHOR]

This paper presents a very robust 6x OSR receiver for 0.2-2 Gb/s binary NRZ signals, introducing an adaptive equalizer that is auto-calibrating on sample data statistics for reliable data recovery in presence of excessive intersymbol interference, noise and crosstalk. The proposed time domain analysis of the data eye obtained with the oversampling architecture is used to tune the equalizer transfer characteristic. The auto-calibration scheme is fully implemented in the digital domain, resulting in a hardware and power efficient architecture with low process-voltage-temperature (PVT) sensitivity. This robust and highly digitized receiver is demonstrated in 0.18 µm CMOS technology and is able to equalize variable cable losses up to 22 dB @ 1 GHz. The self-adaptive equalizer solution occupies only 0.05 mm² and consumes 9 mW from a 1.8 V supply and can handle up to 20 m 100-Ω STP cable @ 2 Gb/s. The entire receiver consumes 110 mW operating at 2 Gb/s with bit error rates of better than < 10-12. [ABSTRACT FROM AUTHOR]

A 10 Gb/s receiver, containing an adaptive equalizer, a clock and data recovery, and a de-multiplexer, is implemented in 0.13-μm CMOS. The chip is intended for long-haul optical fiber links where chromatic and polarization mode dispersions are reach-limiting factors. The equalization is performed by a continuous time filter and a two-tap decision feedback equalizer while automatic threshold and phase adjustments are embedded in the CDR. Use of an analog equalizer with digital adaptation garners total power dissipation of 950 mw. Error-free operation over 200 km of single mode fiber is demonstrated. With 140 km of single mode fiber, optical signal to noise ratio penalty is only 2 dB. Differential group delay of 100 ps can also be tolerated. [ABSTRACT FROM AUTHOR]

In this paper, a "composite" source-follower is presented. Using a positive-feedback, the structure synthesizes complex poles with a single branch. This allows to realize a single-branch biquadratic cell. Moreover, due to the intrinsic feedback present in any source-follower, the proposed cell performs larger linearity for smaller Vov(= VGS - VTH). This is the opposite of other active filters and allows saving the power otherwise used to increase linearity. A fourth-order prototype satisfy typical WLAN 802.11.a/b/g baseband filter specifications has been realized in a 0.18 µm CMOS at 1.8-V supply. It achieves a 175-dBm IIP3 and a -40 dB HD3 for a 600-mVpp-diff input signal amplitude. A 24-μVrms noise gives a DR = 79 dB, with 2.25-mA current consumption. [ABSTRACT FROM AUTHOR]

An accurately tuned low-voltage linear continuous-time filter is presented in this paper. Accurate tuning is achieved using time-constant matched master-slave tuning combined with power-up mismatch calibration. A low-pass biquad designed for a corner frequency of 115 kHz achieves better than -80-dB total harmonic distortion with a 250-mVpp 10-kHz input signal. The prototype implemented in 0.18-pm CMOS process occupies an area of 0.4 mm² and dissipates 4.6 mW (2.6 mW for the filter and 2 mW for tuning) of power. [ABSTRACT FROM AUTHOR]

A third-order Gm-C Butterworth low-pass filter implementing Gm-tuning and Gm-switching to maximize the tuning range is described. This filter is intended to be used as a channel-selection/anti-aliasing filter in the analog baseband part of a zero-IF radio receiver architecture for multimode mobile communications. Its Gm-switching feature allows extending the tuning range and adapting the power consumption. The filter's cutoff frequency ranges from 50 kHz to 2.2 MHz. An Input IP3 of up to +18 dBVp is achieved, for a total worst-case power consumption of 7.3 mW for both I and Q paths, and an effective area of less than 0.5 mm² in a 0.25-µm SiGe BiCMOS process. A new figure of merit is introduced for comparison of published low-pass tunable filters including noise, linearity, and tuning range. [ABSTRACT FROM AUTHOR]

This paper presents a novel efficient method for conversion between arbitrary sampling rates. The method allows arbitrary number of zeros at multiples of both input and output sampling rates, thus it has both good anti-imaging and good anti-aliasing properties. Further, two equivalent efficient implementation structures are presented. The implementation is done either by using the modified Farrow or transposed modified Farrow structure. By choosing one of these two alternatives appropriately, it is possible to shift most of the operations to lower sampling rate. [ABSTRACT FROM AUTHOR]

Techniques for implementing micropower analog filters using digital CMOS process technology are described. PMOS devices operating in accumulation are used for the integration capacitors, and the voltage swing across them is limited by employing current-mode operation using the log domain approach. The latter is implemented using enhanced lateral bipolar transistors. A second-order low-pass filter with a cutoff frequency of 22 kHz, fabricated in a 0.25-μm digital CMOS technology, consumes 4.1 μW from a 1.5-V supply and has an rms output noise of 0.25 nA. The filter's signal-to-noise ratio at 1% total harmonic distortion (THD) is 56 dB and its maximum S/(N+THD) is 45 dB. The chip occupies 0.085 mm2. [ABSTRACT FROM PUBLISHER]

Design techniques for read channel equalizers used in magnetic recording systems are presented. The equalization is based on a multi-level dual decision feedback architecture. The signal processing at low power and high speed is realized by using a continuous-time adaptive forward filter with an infinite impulse response. Furthermore, circuit structures with reduced offset-voltage sensitivities are developed for the equalizer implementation. As a result, the data rate in the intended application can be greater than 200 Mbits/s. [ABSTRACT FROM AUTHOR]

This paper is a practical guide to building higher-order filters with single-amplifier biquadratic MOSFET–C sections. Theory, design guidelines, and measurement electronics are discussed by example of a 7th-order current-mode filter built to the specifications of a 1× DVD read channel filter. The 7th-order filter was fabricated with the double-poly 0.6-micron CMOS process by AMS. It is continuously tunable from 4.5 MHz up to 10 MHz, covers a chip area of only 0.24 mm2, and consumes 49 mW from a 3.3-V supply. The SNR at -40 dB of harmonic distortion is between 48 dB and 50 dB over the whole tuning range. The comparatively low power consumption and chip area could be achieved by using single-amplifier biquadratic building blocks implemented as MOSFET–C filters and generating the control voltage of the MOSFET resistors with an on-chip charge pump. The technique is, with a small loss of SNR, also applicable on fabrication processes where only gate-oxide capacitors are available. [ABSTRACT FROM AUTHOR]

This paper proposes an automatic tuning system to adjust frequency characteristics of integrated continuous-time filters especially at high frequencies. Frequency characteristic deterioration of a filter using integrators with electrically controllable unity-gain frequencies can be easily evaluated and compensated even when they are affected by deviations of element values and parasitic elements. The compensation requires detection of both frequency and excess phase shifts of the integrators. Their two values are electrically detected by two detection systems usually used in the conventional frequency tuning system. The proposed system is stable, simple and easy to be implemented on an integrated circuit. As an example a 4th-order biquad bandpass filter with 10 MHz center frequency, 2 MHz passband width, and 0.5 dB passband ripples is designed using a bipolar process. Simulation results by SPICE show the effectiveness of the proposed system. [ABSTRACT FROM AUTHOR]