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This paper presents the results of experimental studies of the influence of high-frequency magnetron sputtering power on the structural and electrophysical properties of nanocrystalline ZnO films. It is shown that at a magnetron sputtering power of 75 W in an argon atmosphere at room temperature, ZnO films have a relatively smooth surface and a uniform nanocrystalline structure. Based on the results obtained, the formation and study of resistive switching of transparent ITO/ZnO/ITO memristor structures as well as a crossbar array based on them were performed. It is demonstrated that memristor structures based on ZnO films obtained at a magnetron sputtering power of 75 W exhibit stable resistive switching for 1000 cycles between high resistance states (HRS = 537.4 ± 26.7 Ω) and low resistance states (LRS = 291.4 ± 38.5 Ω), while the resistance ratio in HRS/LRS is ~1.8. On the basis of the experimental findings, we carried out mathematical modeling of the resistive switching of this structure, and it demonstrated that the regions with an increase in the electric field strength along the edge of the upper electrode become the main sources of oxygen vacancy generation in ZnO film. A crossbar array of 16 transparent ITO/ZnO/ITO memristor structures was also fabricated, demonstrating 20,000 resistive switching cycles between LRS = 13.8 ± 1.4 kΩ and HRS = 34.8 ± 2.6 kΩ for all devices, with a resistance ratio of HRS/LRS of ~2.5. The obtained results can be used in the development of technological processes for the manufacturing of transparent memristor crossbars for neuromorphic structures of machine vision, robotics, and artificial intelligence systems. [ABSTRACT FROM AUTHOR]

Data encryption is an essential building block in modern electronic systems to prevent spying and hacking. Every day more and more objects produce electronic data, and this needs to be encrypted before being transmitted. Hence, designing devices, circuits, and systems for data encryption that can be integrated in all kinds of objects and that consume low amounts of energy is highly necessary. Here, this work reports the fabrication of flexible and transparent electronic circuits consisting of devices that exhibit threshold‐type resistive switching with a high degree of stochasticity. The cycle‐to‐cycle variability of switching voltages and state currents is significant but confined within a well‐defined range, which is consistent across multiple devices. This allows to design an efficient protocol for true random number generation. The circuits are fabricated with only synthetic 2D materials, can be fabricated in a scalable manner, and can be integrated in any object. [ABSTRACT FROM AUTHOR]

Two‐dimensional (2D) materials are widely used in numerous optoelectronic devices due to their ultra‐thin dimensions and versatile surfaces. However, less attention is paid to distinguishing the light‐matter interactions along the vertical and horizontal paths within the same 2D lattice, as well as comparatively investigating the optoelectronic behaviors between the sensitive top and bottom surfaces. Here, a dual‐crossbar configured architecture is designed and constructed based on Bi2O2Se semiconductor, featuring highly compact three‐in‐one assembly, namely bottom surface horizontal (BSH), middle sandwich vertical (MSV) and top surface horizontal (TSH) devices. The MSV with nanoscale channel possesses efficient separation and transportation of the photogenerated electrons and holes, responding faster to the light stimulation and compared favorably to the BSH and TSH devices. The optoelectric behaviors of the BSH device can be regulated by the characteristics of the substrate due to closer contact. Nevertheless, the performance of the TSH device is more sensitive to the environment, such as dopant absorption and heat dispersion, thus enabling the non‐volatile photoresponse and can be employed as an artificial optoelectronic synapse. This work highlights the importance of designing the device architecture based on the intrinsic structural advantages of 2D materials, paving the way toward integrated optoelectronics. [ABSTRACT FROM AUTHOR]

Resistive random-access memory (RRAM) is a crucial element for next-generation large-scale memory arrays, analogue neuromorphic computing and energy-efficient System-on-Chip applications. For these applications, RRAM elements are arranged into Crossbar arrays, where rectifying selector devices are required for correct read operation of the memory cells. One of the key advantages of RRAM is its high scalability due to the filamentary mechanism of resistive switching, as the cell conductivity is not dependent on the cell area. Thus, a selector device becomes a limiting factor in Crossbar arrays in terms of scalability, as its area exceeds the minimal possible area of an RRAM cell. We propose a tunnel diode selector, which is self-aligned with an RRAM cell and, thus, occupies the same area. In this study, we address the theoretical and modeling aspects of creating a self-aligned selector with optimal parameters to avoid any deterioration of RRAM cell performance. We investigate the possibilities of using a tunnel diode based on single- and double-layer dielectrics and determine their optimal physical properties to be used in an HfOx-based RRAM Crossbar array. [ABSTRACT FROM AUTHOR]

Neuromorphic computing has seen great interest as leaps in artificial intelligence (AI) applications have exposed limitations due to heavy memory access, with the von Neumann computing architecture. The parallel in‐memory computing provided by neuromorphic computing has the potential to significantly improve latency and power consumption. Key to analog neuromorphic computing hardware are memristors, providing non‐volatile multistate conductance levels, high switching speed, and energy efficiency. Ferroelectric tunnel junction (FTJ) memristors are prime candidates for this purpose, but the impact of the particular characteristics for their performance upon integration into large crossbar arrays, the core compute element for both inference and training in deep neural networks, requires close investigation. In this work, a W/HfxZr1−xO2/TiN FTJ with 60 programmable conductance states, a dynamic range (DR) up to 10, current density >3 A m−2 at Vread = 0.3 V and highly nonlinear current–voltage (I–V) characteristics (>1100) is experimentally demonstrated. Using a circuit macro‐model, the system level performance of a true crossbar array is evaluated and a 92% classification accuracy of the modified nation institute of science and technology (MNIST) dataset is achieved. Finally, the low on conductance in combination with the highly nonlinear I–V characteristics enable the realization of large selector‐free crossbar arrays for neuromorphic hardware accelerators. [ABSTRACT FROM AUTHOR]

Paper present possibility of creation a neuromatrix in the form crossbar architecture on a silicon substrate is shown. Crossbar architecture in the form of a set of nanosized conductors, between which there is a layer of titanium oxide, capable of changing its conductivity under the action of the applied voltage, it is proposed to form using the metho d of local anodic oxidation. The results is present of the study technological parameters of the metho d of local anodic oxidation silicon and titanium for the implementation of the elements of this neuromatrix in the form of a memristor structures. [ABSTRACT FROM AUTHOR]

Nanoscale chips inherently suffer from higher defect densities than traditional lithography-based VLSI designs. So defect tolerant designs are required at this scale. Mapping different functions in a very large nanoscale crossbar containing defective cross-points is a hard searching problem. In this work, we studied traditional sorting-based methods followed by two other proposed approaches based on Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) to find a proper assignment of different functions in the nanoscale crossbar circuit having defective cross-points. The objective of the proposed algorithm is to map a very large number of functions within the very large size defective-crossbar if there exists any solution. The number of generations required to get a solution may vary depending on the position of defect points and on-inputs of the functions inspite of having the same defect percentage. Our proposed methods based on GA and PSO work more efficiently with the increase of number of functions, crossbar area and defect percentage in comparison with the traditional sorting-based methods. Experimental results show that our meta-heuristic-based approaches outperform the earlier sorting-based approaches in terms of mapping success percentage. [ABSTRACT FROM AUTHOR]

Many designs of in-memory logic computing using ReRAM have been proposed and even a few of them have been experimentally demonstrated. However, the ability to cascade and extend the designed circuits is limited. In this work, we elaborate a design called time-sum-logic based on 2T1R memristor arrays and implement arithmetic computing circuits using memristors by integrating both time and space dimension. The core method of our design is to use sum of minterms to transfer logic to time sequence by 2T1R memristor arrays. This method is extensible by extending the number of layers to realize multi-bit arithmetic computing. Remarkably, cascading between different layers is elaborated carefully and pipelines are adopted to manage the sequence of memristors’ writing and reading and lower the complexity and latency. In this way, the proposed circuits will be more efficient and can support high data throughout. Based on our design, 4-bit full adder and $4\times 4$ multiplier are designed with pipelines, and n-bit full adders and m $\times $ n multipliers could be easily constructed. The low latency and high efficiency confirm the advantages we have illustrated and show a promised application prospect.

Real-time spike sorting and processing are crucial for closed-loop brain-machine interfaces and neural prosthetics. Recent developments in high-density multi-electrode arrays with hundreds of electrodes have enabled simultaneous recordings of spikes from a large number of neurons. However, the high channel count imposes stringent demands on real-time spike sorting hardware regarding data transmission bandwidth and computation complexity. Thus, it is necessary to develop a specialized real-time hardware that can sort neural spikes on the fly with high throughputs while consuming minimal power. Here, we present a real-time, low latency spike sorting processor that utilizes high-density CuOx resistive crossbars to implement in-memory spike sorting in a massively parallel manner. We developed a fabrication process which is compatible with CMOS BEOL integration. We extensively characterized switching characteristics and statistical variations of the CuOx memory devices. In order to implement spike sorting with crossbar arrays, we developed a template matching-based spike sorting algorithm that can be directly mapped onto RRAM crossbars. By using synthetic and in vivo recordings of extracellular spikes, we experimentally demonstrated energy efficient spike sorting with high accuracy. Our neuromorphic interface offers substantial improvements in area (~1000× less area), power (~200× less power), and latency (4.8μs latency for sorting 100 channels) for real-time spike sorting compared to other hardware implementations based on FPGAs and microcontrollers.

Neuromorphic computing has seen great interest as leaps in artificial intelligence (AI) applications have exposed limitations due to heavy memory access, with the von Neumann computing architecture. The parallel in‐memory computing provided by neuromorphic computing has the potential to significantly improve latency and power consumption. Key to analog neuromorphic computing hardware are memristors, providing non‐volatile multistate conductance levels, high switching speed, and energy efficiency. Ferroelectric tunnel junction (FTJ) memristors are prime candidates for this purpose, but the impact of the particular characteristics for their performance upon integration into large crossbar arrays, the core compute element for both inference and training in deep neural networks, requires close investigation. In this work, a W/Hf x Zr1−x O2/TiN FTJ with 60 programmable conductance states, a dynamic range (DR) up to 10, current density >3 A m−2 at V read = 0.3 V and highly nonlinear current–voltage (I–V) characteristics (>1100) is experimentally demonstrated. Using a circuit macro‐model, the system level performance of a true crossbar array is evaluated and a 92% classification accuracy of the modified nation institute of science and technology (MNIST) dataset is achieved. Finally, the low on conductance in combination with the highly nonlinear I–V characteristics enable the realization of large selector‐free crossbar arrays for neuromorphic hardware accelerators.

Although digital processors offer high computing accuracy, they suffer enormously from lengthy execution times and high energy consumption as a result of the numerous communications between the processors and storage units. The disadvantage is especially acute when performing data-intensive operations, such as deep neural networks and matrix operations. To address this, several novel ideas and devices for implementing in-memory computing have been proposed. One of them is the memristor. Because of their scalability, nonvolatility, and analog storage characteristics, memristors have considerable potential and have achieved some encouraging research results. An eigenpair estimation method and a memristor-based crossbar structure are presented in this paper. The method differs from conventional computers in that the execution is carried out with the least number of controls and data transfers as possible. Almost all of the desired outcomes can be attributed to fundamental physical laws, such as Ohm's law and Kirchhoff's law. This method is then applied to principal component analysis (PCA) in the end. [ABSTRACT FROM AUTHOR]

The semiconductor industry has seen significant technological advancements, leading to an increase in the number of processing cores in a system-on-chip (SoC). To facilitate communication among the numerous on-chip cores, a network-on-chip (NoC) is employed. One of the main challenges of designing NoCs is power management since the NoC consumes a significant portion of the total power of the SoC. Among the power-intensive components of the NoC, routers stand out. We observe that some power-intensive components of routers, responsible for implementing turn in the mesh topology, are underutilized compared to others. Therefore, we propose Tulip, a turn-free low-power network-in-chip, that avoids within-router turns by removing the corresponding components from the router structure. On a turn (e.g., at the end of the current dimension), Tulip forces the packet to be ejected and then reinjects it to the next dimension channel (i.e., the beginning of the path along the next dimension). Due to its deadlock-free nature, Tulip's scheme may be used orthogonally with any deterministic, partially-adaptive, and fully-adaptive routing algorithms, and can easily be extended for any n-dimensional mesh topology. Our analysis reveals that Tulip can reduce the static power and area by 24%−50% and 25%-55%, respectively, for 2D-5D mesh routers. [ABSTRACT FROM AUTHOR]

An oscillatory process of a rod system of arbitrary shape is considered in the course of impact interaction with a falling load. The system may consist of a large number of rods rigidly or hingedly connected to each other, the impact occurring on one of the rod elements, thus causing a complex oscillatory process. As an example, vibrations of a rigidly embedded statically indeterminate flat twin-pillar frame are simulated, which experiences a drop of a load of a given mass and pre-shock velocity. One of the vertical frame legs has an initial curvature, the presence of which affects the maximum amplitude of transverse vibrations that occur during impact. The impact of the load on the frame crossbar is modeled taking into account the deformation in the contact area, which is justified from the point of view of the accuracy of calculations, since otherwise the impact force magnitude will be overestimated. When modeling the load impact interaction and the considered rod system, it is assumed that the falling load has the shape of a cylinder with a certain generatrix length. Linearization of the relationship between the force and deformation of cylindrical surfaces is used. The proposed technique for modeling the amplitude of transverse oscillations makes it possible to further study the oscillatory process characteristics depending on the falling load mass and its pre-impact velocity, as well as on the rod system configuration. The relevance of the work for the calculation of structural elements of various purposes that are subject to impact is emphasized, since the presented model can be used for engineering calculations of a wide class of bar systems. [ABSTRACT FROM AUTHOR]

The reliable and compact modeling of RRAM devices is crucial for supporting the development of novel technologies including them. This includes a wide range of applications, such as in-memory computing or memristive logic. A major advantage of the considered HfO $_{2}$ -based RRAM devices is their CMOS-compatibility, which allows them to already be utilized in present applications. However, one problem is that their fabrication still leads to device variabilities, which makes it challenging to test their functionality in an experimental fashion. This work is dedicated to the compact modeling and efficient emulation of 1T-1R RRAM devices. We aim to provide an enhanced model for multilevel capable RRAM devices, based on the Stanford-PKU model, that can be used on any simulation platform such as SPICE or VERILOG-A. Furthermore, we provide an algorithmic model, based on the wave digital (WD) concept, which allows for emulating the considered devices in real-time. Using the latter, we show the hysteresis of our enhanced model to exhibit astounding resemblance with real device measurements. Finally, we extend the WD model to describe an array composed of RRAM devices for performing vector-matrix multiplication. [ABSTRACT FROM AUTHOR]

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Phase-change photonics integrated circuits (PICs) have most recently attained considerable attention due to their broad bandwidth, superfast processing speed, and multiplexing function. However, their poor scalability adversely limited current PICs into single cell or simple architectures. To overcome this issue, for the first time we modelled the write and readout performances of Ge2Sb2Te5-based nanophotonic architecture with integrated indium-Tin-oxide (ITO) heater and crossbar platinum (Pt) electrodes. The updated architecture, when compared with other reported prototypes, exhibited better scalability and smaller energy consumptions. Its ability to achieve random access and multilevel functions at system level was also demonstrated by simulations, implying its bright prospect for in-memory computing and neuromorphic computing applications. [ABSTRACT FROM AUTHOR]

In-memory computing is a promising solution strategy for data-intensive applications to circumvent the von Neumann bottleneck. Flow-based computing is the concept of performing in-memory computing using sneak paths in nanoscale crossbar arrays. The limitation of the previous work is that the resulting crossbar representations have large size. In this article, we present a framework called COMPACT for mapping Boolean functions to crossbar representations with a minimal semiperimeter (the number of wordlines plus bitlines) and/or maximum dimension (the maximum of the wordlines or bitlines). The COMPACT framework is based on an analogy between binary decision diagrams (BDDs) and nanoscale memristor crossbar arrays. More specifically, nodes and edges in a BDD correspond to wordlines/bitlines and memristors in a crossbar array, respectively. The relation enables a Boolean function represented by a BDD with $n$ nodes and an odd cycle transversal of size $k$ to be mapped to a crossbar with a semiperimeter of $n+k$. The $k$ extra wordlines/bitlines are introduced due to crossbar connection constraints, i.e., wordlines (bitlines) cannot directly be connected to wordlines (bitlines). Moreover, there exists a tradeoff between the semiperimeter and maximum dimension. Consequently, COMPACT can sometimes reduce the maximum dimension by slightly increasing the length of the semiperimeter. We also extend COMPACT to handle multioutput functions using shared BDD (SBDDs) and alignment constraints on the inputs and outputs. Compared with the state-of-the-art mapping technique, the semiperimeter and maximum dimension are reduced by 55% and 85%, respectively. The area, power consumption, and computation delay are reduced by 89%, 19%, 56%, respectively. [ABSTRACT FROM AUTHOR]

We are developing field-programmable gate arrays (FPGAs) with a new non-volatile switch called via-switch. In via-switch FPGAs (VS-FPGAs), the via-switches required for reconfiguration are placed in the routing layer so that the entire transistor layer can be utilized for computing, and higher implementation density can be achieved compared to conventional SRAM FPGAs. Furthermore, since arithmetic units and memories for computing can be placed under the via-switch crossbar for routing, large-scale parallel operations can be realized where the memory and the arithmetic unit are adjacent to each other. These features enable operation with high energy efficiency. This article reports 65 nm prototype fabrication results and predicted the performance of the VS-FPGA designed for AI applications. We also present the developed application mapping flow and crossbar programming method. The VS-FPGA closes the gap between FPGA and application-specific integrated circuits (ASIC) with the performance advantage of the via-switch and via-switch copy scheme for FPGA-to-ASIC migration, contributing to the expansion of the FPGA usage. [ABSTRACT FROM AUTHOR]

Neuromorphic computing chips consisting of crossbar arrays of emergent nonvolatile memory (NVM) have the potential of achieving both high energy efficiency and throughput as the low-power implementation of convolutional neural network (CNN) inference engines. However, such hardware has design constraints, such as its limited fan-in/fan-out and resource-inefficient mapping, that make the design and deployment of CNN on them challenging. As a result, the user has to design the CNN model with intricate knowledge of the hardware architecture and even cannot fit the models in the hardware for CNN with high resolution image input. In this article, we propose the use of aggregated subnets, NC-net, which is a constrained form of the traditional layer structure, to solve these issues. With our method, we put forward an energy-efficient buffer- and analogue-to-digital converter and digital-to-analogue converter (ADC/DAC)-free architecture and a scalable end-to-end solution that automatically satisfies the hardware constraints of crossbar architectures, while optimizing the resource usage. In our solution, the exploration and deployment of a CNN for a neuromorphic crossbar hardware start with a design front end based on TensorFlow. Our automated design flow maps the NC-net network from TensorFlow to the crossbar architecture. We tested our designs on both a simulator and a field-programmable gate array (FPGA) emulator with various benchmarks. In addition to general benchmarks, including MNIST, SVHN, CIFAR-10, and CIFAR-100, we tested our system on a real-world application, human detection with high resolution (224 $\times $ 224) images as the input. Our system achieves the state-of-the-art accuracy for these benchmarks on the crossbar-based neuromorphic hardware, with an accuracy of more than 90% for the latter. It also yielded up to $4.25\times $ improvement in the efficiency of spiking core usage compared to TrueNorth. [ABSTRACT FROM AUTHOR]

Single memristor crossbar arrays are a very promising approach to reduce the power consumption of deep learning accelerators. In parallel, the emerging bio‐inspired spiking neural networks (SNNs) offer very low power consumption with satisfactory performance on complex artificial intelligence tasks. In such neural networks, synaptic weights can be stored in nonvolatile memories. The latter are massively read during inference, which can lead to device failure. In this context, a 1S1R (1 Selector 1 Resistor) device composed of a HfO2‐based OxRAM memory stacked on a Ge‐Se‐Sb‐N‐based ovonic threshold switch (OTS) back‐end selector is proposed for high‐density binarized SNNs (BSNNs) synaptic weight hardware implementation. An extensive experimental statistical study combined with a novel Monte Carlo model allows to deeply analyze the OTS switching dynamics based on field‐driven stochastic nucleation of conductive dots in the layer. This allows quantifying the occurrence frequency of OTS erratic switching as a function of the applied voltages and 1S1R reading frequency. The associated 1S1R reading error rate is calculated. Focusing on the standard machine learning MNIST image recognition task, BSNN figures of merit (footprint, electrical consumption during inference, frequency of inference, accuracy, and tolerance to errors) are optimized by engineering the network topology, training procedure, and activations sparsity. [ABSTRACT FROM AUTHOR]

The von Neumann bottleneck has significantly increased the energy consumption of processing units and memory systems, especially in data-intensive computations such as the correlation parameter, which is being used in medical research, financial market analysis, biometrics, etc. Recently, memristor-enabled in-memory processing has gained tremendous research attraction to extenuate the von Neumann bottleneck as it processes operands at the location of storage, which obviates the need to transfer data between memory and the processing units. Hence, in this article, an innovative memristor crossbar-based architecture computing correlation parameter in-memory (CoCoPIM) has been proposed to accelerate correlation coefficient computations. Three different applications such as computing correlation between electrocardiogram (ECG) signals, faces, and H1N1 models were implemented based on the architecture. To evaluate the architecture, Neurosim was modified to support data mapping and computation steps, whereas Micro Architectural and System Simulator (MARSS) and multicore power, area, and timing (McPAT) were used to evaluate the von Neumann machine. In these applications, it was found that CoCoPIM was $41.04\times $ , $66.5\times $ , $67\times $ , and $33.2\times $ times energy-efficient against a four-core out-of-order processor in performing the respective tasks. It also achieved a speedup of $143.5\times $ , $52.5\times $ , $52.5\times $ , and $597\times $ times against the same von Neumann machine (multicore processor) for the respective tasks. [ABSTRACT FROM AUTHOR]

The formation feasibility for a neural network based on crossbar-array architecture on a silicon substrate has been demonstrated. The possibility of neural network implementation in the form of crossbar-array architecture on a silicon substrate has been shown. It is suggested that the crossbar-array architecture (a set of orthogonal nanometer conductors with a titanium oxide layer in between, the conductivity of which is sensitive to applied voltage) be configured using local anodic oxidation. Test results for process parameters used in local anodic oxidation of silicon and titanium to create elements of a memristor-based neural matrix are presented. [ABSTRACT FROM AUTHOR]

In recent years, compute-in-memory (CIM) has been extensively studied to improve the energy efficiency of computing by reducing data movement. At present, CIM is frequently used in data-intensive computing. Data-intensive computing applications, such as all kinds of neural networks (NNs) in machine learning (ML), are regarded as 'soft' computing tasks. The 'soft' computing tasks are computations that can tolerate low computing precision with little accuracy degradation. However, 'hard' tasks aimed at numerical computations require high-precision computing and are also accompanied by energy efficiency problems. Numerical computations exist in lots of applications, including partial differential equations (PDEs) and large-scale matrix multiplication. Therefore, it is necessary to study CIM for numerical computations. This article reviews the recent developments of CIM for numerical computations. The different kinds of numerical methods solving partial differential equations and the transformation of matrixes are deduced in detail. This paper also discusses the iterative computation of a large-scale matrix, which tremendously affects the efficiency of numerical computations. The working procedure of the ReRAM-based partial differential equation solver is emphatically introduced. Moreover, other PDEs solvers, and other research about CIM for numerical computations, are also summarized. Finally, prospects and the future of CIM for numerical computations with high accuracy are discussed. [ABSTRACT FROM AUTHOR]

We perform a simulation-based analysis on the potential of emerging ferroelectric tunnel junctions (FTJs) as a memory device for crossbar arrays. Though FTJs are promising due to their low power switching characteristics compared to other emerging technologies, the greatest challenge for FTJs is the tradeoff between integration density and read performance. Our analysis highlights the need to co-optimize the ferroelectric thickness of the FTJ and read/write voltages to achieve proper functionality at large array sizes. Our analysis shows that FTJ-based crossbar achieves 93% higher sense margin at isoread power of 116 nW (per bit), but this FTJ design comes at a cost of $9.28\times $ higher write power at isowrite time of 250 ns. In response, we study the potential tradeoffs of design points outside the feasible region to understand what device characteristics are desired to overcome such challenges.

Memristors offer the possibility of implementing multilevel cells in Resistive RAMs providing high-density non-volatile data storage solutions. However the writing and reading processes when these devices are integrated into a crossbar is a problem that has not yet been fully solved. Process and temperature variations must be carefully handled when designing reliable interface circuits for RRAM cells. In this work we present a time-domain reading circuit for multilevel RRAM cells. The sensing operation is performed based on the well-known RC circuit that generates a pulse whose width depends on the state of the cell, providing excellent results in terms of area, energy per bit and scalability. Temperature and process variations have been analysed in depth to validate the effective number of levels a cell may store to be read accurately.

Memristor has been widely explored in digital logic circuits where most of the works are focused on basic gate circuits, such as OR and AND logic gates or full adders while few involve flip‐flops. In fact, flip‐flops are also basic logic units with memory function for various digital systems. In this paper, we present circuit designs for Delay (D) and Jump‐Key (JK) flip‐flops based on memristor ratioed logic (MRL). The proposed circuit for D flip‐flop only needs five memristors and one NMOS transistor, and circuit for JK flip‐flop needs seven memristors and two NMOS transistors. Furthermore, the proposed circuits have been mapped into a hybrid memristor‐CMOS crossbar array. Compared with previous approaches, the quantity of MOSFET for each proposed circuit has been greatly reduced. Thus, the proposed designs have achieved simpler structure, smaller area, and lower power consumption benefiting from the memristor's nanoscale size and low power consumption. The circuit verification based on PSpice simulation is also provided. [ABSTRACT FROM AUTHOR]

Neural network (NN) computing contains a large number of multiply-and-accumulate (MAC) operations. The performance of NN accelerator is limited with the traditional von Neumann architecture due to the tremendous off-chip memory accesses. Resistive random-access memory (ReRAM)-based crossbars can naturally perform matrix–vector multiplication (MVM) operations and are well suitable for NN accelerators. In the existing ReRAM-based NN accelerators, the synaptic weights represented by the conductances of ReRAMs are mainly based on the binary coding. However, the imperfect fabrication process combined with stochastic filament-based switching leads to resistance variations of ReRAMs, which can significantly alter the weights in binary synapses and degrade the NN accuracy. Moreover, the NN accuracy further deteriorates with multilevel cells (MLCs) used for reducing hardware overhead. In this article, a novel unary coding of synaptic weights is proposed to overcome the resistance variations of MLCs and achieve reliable ReRAM-based neuromorphic computing. A variation-aware optimal mapping scheme is also proposed in compliance with the unary coding to guarantee high accuracy by leveraging a unique feature of unary coding—the existence of multiple ways to represent the same value. The optimal mapping obtains very small errors for weights with resistance variations of MLCs. Our simulation results show that under resistance variations, the proposed method achieves less than 0.08% and 3.43% accuracy loss on CIFAR10 and ImageNet, respectively, compared to the ideal accuracy. With each synaptic weight represented by four 2-b MLCs, the proposed method improves the accuracy over the traditional binary coding scheme by 83.39% and 87.6% for CIFAR10 and ImageNet, respectively. [ABSTRACT FROM AUTHOR]

Quantum‐dot cellular automata (QCA) is a promising nanoelectronic technology having the characteristics of stable operation, breakneck speed, and ultralow energy consumption in theory. However, no scalable and modular architecture can facilitate circuit implementation, restricting the overall development of this technology. Different from the traditional programmable logic array (PLA) using AND‐OR arrays, this paper proposes a design method of PLA using crossbar structure in QCA. The PLA consists of multiple programmable units in which the majority gates can be programmed as AND/OR gates, and an inverter following each majority gate will invert the output as needed. To flexibly adjust the logic states of each programmable unit, a programmable clock scheme and N‐bit latch are then proposed. Therefore, a circuit can arbitrarily be achieved by programming the PLA. Four circuits, including full adder, 2–1 MUX, D flip‐flop, and 1‐bit memory, are designed, implemented, and simulated in QCA, by using this PLA. Experimental results show that the designed circuits realize logic functions correctly and stably. [ABSTRACT FROM AUTHOR]

In-memory computing with emerging non-volatile memory devices (eNVMs) has shown promising results in accelerating matrix-vector multiplications. However, activation function calculations are still being implemented with general processors or large and complex neuron peripheral circuits. Here, we present the integration of Ag-based conductive bridge random access memory (Ag-CBRAM) crossbar arrays with Mott rectified linear unit (ReLU) activation neurons for scalable, energy and area-efficient hardware (HW) implementation of deep neural networks. We develop Ag-CBRAM devices that can achieve a high ON/OFF ratio and multi-level programmability. Compact and energy-efficient Mott ReLU neuron devices implementing ReLU activation function are directly connected to the columns of Ag-CBRAM crossbars to compute the output from the weighted sum current. We implement convolution filters and activations for VGG-16 using our integrated HW and demonstrate the successful generation of feature maps for CIFAR-10 images in HW. Our approach paves a new way toward building a highly compact and energy-efficient eNVMs-based in-memory computing system.

The human brain can be considered as a complex dynamic and recurrent neural network. There are several models for neural networks of the human brain, that cover sensory to cortical information processing. Large majority models include feedback mechanisms that are hard to formalise to realistic applications. Recurrent neural networks and Long short-term memory (LSTM) inspire from the neuronal feedback networks. Long short-term memory (LSTM) prevent vanishing and exploding gradients problems faced by simple recurrent neural networks and has the ability to process order-dependent data. Such recurrent neural units can be replicated in hardware and interfaced with analog sensors for efficient and miniaturised implementation of intelligent processing. Implementation of analog memristive LSTM hardware is an open research problem and can offer the advantages of continuous domain analog computing with relatively low on-chip area compared with a digital-only implementation. Designed for solving time-series prediction problems, overall architectures and circuits were tested with TSMC 0.18 μm CMOS technology and hafnium-oxide (HfO2) based memristor crossbars. Extensive circuit based SPICE simulations with over 3,500 (inference only) and 300 system-level simulations (training and inference) were performed for benchmarking the system performance of the proposed implementations. The analysis includes Monte Carlo simulations for the variability of memristors' conductance, and crossbar parasitic, where non-idealities of hybrid CMOS-memristor circuits are taken into the account.

The human brain can be considered as a complex dynamic and recurrent neural network. There are several models for neural networks of the human brain, that cover sensory to cortical information processing. Large majority models include feedback mechanisms that are hard to formalise to realistic applications. Recurrent neural networks and Long short-term memory (LSTM) inspire from the neuronal feedback networks. Long short-term memory (LSTM) prevent vanishing and exploding gradients problems faced by simple recurrent neural networks and has the ability to process order-dependent data. Such recurrent neural units can be replicated in hardware and interfaced with analog sensors for efficient and miniaturised implementation of intelligent processing. Implementation of analog memristive LSTM hardware is an open research problem and can offer the advantages of continuous domain analog computing with relatively low on-chip area compared with a digital-only implementation. Designed for solving time-series prediction problems, overall architectures and circuits were tested with TSMC 0.18 μm CMOS technology and hafnium-oxide (HfO 2) based memristor crossbars. Extensive circuit based SPICE simulations with over 3,500 (inference only) and 300 system-level simulations (training and inference) were performed for benchmarking the system performance of the proposed implementations. The analysis includes Monte Carlo simulations for the variability of memristors' conductance, and crossbar parasitic, where non-idealities of hybrid CMOS-memristor circuits are taken into the account. [ABSTRACT FROM AUTHOR]