Search

OUTLINE Introduction QPZD nonlinear model Statistical model and yield optimization MMIC IP model Conculsion

A multi-nanosheet field-effect transistor (mNS-FET) device was developed to maximize gate controllability while making the channel in the form of a sheet. The mNS-FET has superior gate controllability for the stacked channels, consequently, it can significantly reduce the short-channel effect (SCE), however, punch-through inevitably occurs in the bottom channel portion that is not surrounded by gates, resulting in a large leakage current. Moreover, as the size of the semiconductor device decreases to several nanometers, the influence of the parasitic resistance and parasitic capacitance increases. Therefore, it is essential to apply design&ndash, technology co-optimization, which analyzes not only the characteristics from the perspective of the device but also the performance from the circuit perspective. In this study, we used Technology Computer Aided Design (TCAD) simulation to analyze the characteristics of the device and directly fabricated a model that describes the current&ndash, voltage and gate capacitance characteristics of the device by using Berkeley short-channel insulated-gate field-effect transistor&ndash, common multi-gate (BSIM&ndash, CMG) parameters. Through this model, we completed the Simulation Program with Integrated Circuit Emphasis (SPICE) simulation for circuit analysis and analyzed it from the viewpoint of devices and circuits. When comparing the characteristics according to the presence or absence of bottom oxide by conducting the above research method, it was confirmed that subthreshold slope (SS) and drain-induced barrier lowering (DIBL) are improved, and power and performance in circuit characteristics are increased.

Nowadays, Microelectronics industry must handle a real “data deluge” and a growing demand of added functionalities due to the new market sector of Internet Of Things, 5G but also Artificial Intelligence... At the same time, energy becomes a major issue and new computation paradigms emerge to break the traditional Von-Neumann architecture. In this context, this PhD manuscript explores both 3D monolithic integration and nano-electronic devices for In-Memory Computing. First, 3D monolithic integration is not seen only as an alternative to Moore’s law historic scaling but also to leverage circuit diversification. The advantages of this integration are analysed in depth and in particular an original top-tier Static Random Access Memories (SRAM) assist is proposed, improving significantly SRAM stability and performances without area overhead. In a second time, an original transistor architecture, called junctionless, suitable for 3D-monolithic integration is studied in detail. Devices are simulated, fabricated and electrically characterised for mixed digital/analog applications. In particular, the impact of channel doping density on mismatch is tackled. Also, low temperature (, De nos jours, l’industrie microélectronique doit maitriser un véritable « déluge de données » et une demande toujours en croissance de fonctionnalités ajoutées pour les nouveaux secteurs de marchés tels que la 5G, l’internet des objets, l’intelligence artificielle… Par ailleurs, l’énergie et sa gestion est un enjeu majeur au sein des architectures Von-Neumann traditionnelles. Dans ce cadre, ce travail de thèse explore l’intégration 3D monolithique ainsi que des dispositifs pour le calcul dans la mémoire. Premièrement, l’intégration 3D monolithique n’est pas perçue uniquement comme une alternative à la loi de Moore mais permet de diversifier les circuits. Les avantages de cette intégration sont analysés en détails et en particulier, une aide à la stabilité des mémoires SRAM (Static Random Access Memory) est proposée. Cette aide améliore significativement la stabilité ainsi que les performances des SRAM de l’étage supérieur, sans dégrader l’empreinte silicium. Secondement, des transistors sans jonctions (junctionless), compatibles avec une intégration 3D séquentielle sont étudiés. Les dispositifs sont simulés, fabriqués et caractérisés électriquement pour des applications digitales et analogiques. En particulier, l’impact du dopage canal sur la variabilité est analysée. Egalement des briques à basse température (

In this paper, we present a layout and performance analysis of logic and SRAM circuits for vertical and lateral GAA FETs using 5nm (iN5) design rules. Extreme ultra-violet lithography (EUVL) processes are exploited to print the critical features: 32 nm gate pitch and 24 nm metal pitch. Layout architectures and patterning compromises for enabling the 5nm node will be discussed in details. A distinct standard-cell template for vertical FETs is proposed and elaborated for the first time. To assess electrical performances, a BSIM-CMG model has been developed and calibrated with TCAD simulations, which accounts for the quasi-ballistic transport in the nanowire channel. The results show that the inbound power rail layout construct for vertical devices could achieve the highest density while the interleaving diffusion template can maximize the port accessibility. By using a representative critical path circuit of a generic low power SoCs, it is shown that the VFET-based circuit is 40% more energy efficient than LFET designs at iso-performance. Regarding SRAMs, benefits given by vertical channel orientation in VFETs has reduced the SRAM area by 20%~30% compared to lateral SRAMs. A double exposures with EUV canner is needed to reach a minimum tip-to-tip (T2T) of 16 nm for middle-of-line (MOL) layers. To enable HD SRAMs with two metal layers, a fully self-aligned gate contact for LFETs and 2D routing of the top electrode for VFETs are required. The standby leakage of vertical SRAMs is 4~6X lower than LFET-based SRAMs at iso-performance and iso-area. The minimum operating voltage (Vmin) of vertical SRAMs is 170 mV lower than lateral SRAMs. A high-density SRAM bitcell of 0.014 um2 can be obtained for the iN5 technology node, which fully follows the SRAM scaling trend for the 45nm nodes and beyond.

In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device $V_{T}$ retargeting has been proposed for improving the minimum operating voltage ( $V_{\min }$ ) of SRAMs. The isoperformance and isoyield have been performed to assess and determine the benefits provided by LFET and VFET architectures, respectively. Our results show that the VFET bitcells are denser than the LFET bitcells by 20%–30%. The SRAM read stability (read static noise margin) is significantly improved using the NW channel. For a $6\sigma $ yield target and an isoarea of SRAM bitcells, $V_{\min }$ of the VFET bitcell is 80 mV lower than LFET designs. Applying the proposed $V_{T}$ retargeting technique can allow the VFET 122 bitcell to operate at 0.57 V without using assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At isoperformance, the standby leakage of VFET bitcells is $2.6\times $ lower than LFET bitcells.

This paper presents a comprehensive benchmarking and co-optimization of 6T SRAM bitcells designed with 5nm vertical and lateral gate-all-around nanowire FET technology for the first time. A variety of 6T SRAM bitcells configurations combined with different device integration scenarios will be discussed. Our results show that an ultra-dense SRAM bitcell (0.01 um2) can be achieved with vertical FET architecture. The bitcell designed with vertical FET are preferably targeted for low power applications while the lateral FET-based SRAM bitcells could provide 4.5x higher in performance, but resulting in a penalty of 17x increasing in the leakage current compared to the vertical designs. A Vmin of 0.45 V could be obtained for 122 SRAM bitcells implemented with vertical devices.

This paper presents a vertical gate-all-around nanowire FET (VFET) architecture targeting 5nm and beyond technologies, and a new standard-cell construct for digital flow implementation. VFET technology circuits and parasitics for processes and design features aligned with 5nm CMOS are systematically assessed for the first time. Self-aligned quadruple pattering (SAQP) is implemented to achieve required 12nm half-pitch interconnects, and the worst case RC delay corner is 1.4X slower than best case corner. Our work shows that interconnect delay variability of a wire of average length in SoCs can overwhelm device variability. Consequently, a new device architecture with a smaller footprint as VFET would effectively lower the BEOL variability by shortening the wirelength and help SRAM bit cells to follow 50% area scaling trend. It is shown that a VFET-based D Flip-Flop (DFF) and 6T-SRAM cell can offer 30% smaller layout area than FinFET (or equivalent lateral 2D) based designs. Furthermore, we obtain a 19% reduction in routing area of a 32-bit multiplier implemented with a VFET-based standard-cell library w.r.t. the FinFET design.