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The iterative property of inverse butterfly permutation network makes it possible to implement shift operation with simple routing algorithm, which has high application value in cryptography, digital image processing and other fields. Based on the inverse butterfly network, this paper proposes a subword shift unit, which integrates the operations of subword rotation shift, subword logical shift and subword arithmetic shift, extends the function of the shift unit. In this paper, the generation process of routing-bits and mask-selecting-bits is unified into the same algorithm and hardware structure, which reduces the hardware area effectively. The algorithm also implements the unification of bidirectional shift, and solves the problem that the scheme of calculating the complement can not generate the mask-selecting-bits in two directions. The unit increases the area and latency by only 5.1% and 3.3% in the case that the implemented shift operation types are extended by 37.5%, thus achieving an efficient extension of the shift function.

In this paper, to solve the problem that there are shortage of united frameworks or the frameworks do not match very well with the process for NBFs in sequence cryptograms, we analyzed the processing of sequence cryptograms, describe the abstract model and devise a reconfigurable framework for the existing NBFs. In particular, in order to get excellent area utilization, we firstly study on the proposed model about the influence of LUT (look-up table) and cluster on FPGA (field programmable gate array), which is widely accepted by industry. With the features of sequence cryptograms in mind, we focus on the critical component named ACLM (adaptive cryptographic logic module) in proposed structure after analyzing the effect of LUT size and cluster size on the area utilization. Having researched the specific features of NBFs, we determine the LUT size, ACLM size and ACLM input ports are 4, 4 and 10. Finally, our results show that the designed framework can clock the data path at 241MHz, and the area utilization of ACLM exceeds 90% mostly and can even achieve 100% for some NBFs or cryptograms.

With the incredible development of network technology in communication devices, medical equipment, consume electronics, home appliances, transportation systems, and even weapons systems, data security becomes a major concern in information technology environment. However, existing protection solutions often require significant overhead to achieve adequate protection. Furthermore, as progress in computing ability and attack technology never stop, the protective ability also faces great challenges. This issue proposes a security management, IMSet-SHA3-Tree, which guarantees data integrity strongly through an integrity checking module based on SHA3-TAH and incremental multiset hash tree with a reduced overhead in area, memory footprint, and performance. Hardware implementation is designed and synthesized with a 0.18μm process. The experiment area is about 0.7mm2 while frequency reaches 563 MHz. Attack complexity of ours is more than 2224, which is overwhelmingly higher than that of existing solutions. Additional storage consumption of ours is limited in about 26.6%. Moreover, latency of our management is extraordinary short. The IMSet-SHA3-Tree proposed can provide extraordinary higher integrity protection with a reasonable overhead of memory footprint and latency, making it a significative and promising solution to data integrity verification.

NAND Flash is widely used in modern digital products and it has become a trend to integrate NAND Flash controller into SoC. This paper discussed the implementation scheme of the NAND Flash controller in detial, including the design of state machine, ECC module and so on. In order to improve the data access speed of NAND Flash Controller, this paper proposed two technologies which increase little area but improve the performance of the controller effectively. The test results based on FPGA showed that this design had high practical value. Based on SMIC 0.18µm standard CMOS technology, this design can work at the frequency of 121MHz.