49 results on '"Dandapat, Anup"'
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2. SMS-CAM: Shared matchline scheme for content addressable memory
3. Design of a Stack Based Compressor for High Speed Computation
4. Low-power content addressable memory design using two-layer P-N match-line control and sensing
5. Analysis and Proposal of a Flash Subranging ADC Architecture
6. Analysis of Analog Comparators Using a 6-Bit Flash ADC Architecture
7. Low discharge precharge free matchline structure for energy-efficient search using CAM
8. A 10-bit 2.33 fJ/conv. SAR-ADC with high speed capacitive DAC switching using a novel effective asynchronous control circuitry
9. Methodologies for CAM and ADC design
10. Vedic algorithm for cubic computation and VLSI implementation
11. Low Power Sense Amplifier For A 64×32 Bit Sram Array For IOT Application
12. Design of Low Power and High Speed Carry Look Ahead Adder (CLAA) Based on Hybrid CMOS Logic Style
13. Analysis of Analog Comparators Using a 6-Bit Flash ADC Architecture
14. A 10-bit 2.5 GS/s low power hybrid subranging flash-SAR ADC for high data rate communication
15. Design of High Speed Vedic Multiplier for Decimal Number System
16. Design of a 1.29–1.61GHz LC-VCO with Improved Phase Noise and Figure-of-Merit (FoMT) for GPS and Satellite Navigation
17. Design of Low Power and High Speed Carry Look Ahead Adder (CLAA) Based on Hybrid CMOS Logic Style
18. Analysis of the Universal Gates based on the Comparative Factors of Delay Propagation, Average Power Dissipation and Logical Effort
19. Modified Baugh Wooley Multiplier using Low Power Compressors
20. Design of High Speed Vedic Multiplier for Decimal Number System
21. Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications
22. The analogy of matchline sensing techniques for content addressable memory (CAM)
23. Pseudo-Static Master-Slave Match-Line Scheme for Sustainable-Performance and Energy-Efficient Content Addressable Memory
24. A Quasi-Static Storage and Decision Block for Performance-Efficient Content Addressable Memory
25. A Low-Power Split-Controlled Single Ended Storage Content Addressable Memory
26. Design and Implementation of Drivers and Selectors for Content Addressable Memory (CAM)
27. Efficient Matchline Controller for Hybrid Content Addressable Memory
28. Match‐line control unit for power and delay reduction in hybrid CAM.
29. Low Power 10-Bit Flash ADC with Divide and Collate Subranging Conversion Scheme
30. Low Match-Line Voltage Swing Technique for Content Addressable Memory
31. Performance Analysis of N-CAM, P-CAM and TG-CAM Using 45-nm Technology
32. Match-Line Division and Control to Reduce Power Dissipation in Content Addressable Memory
33. A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme
34. Self-Controlled High-Performance Precharge-Free Content-Addressable Memory
35. Energy-Efficient Adaptive Match-Line Controller for Large-Scale Associative Storage
36. A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access
37. A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications
38. Design Methodology for Multiple Output Combinational Circuits Using Cyclic Combinational Technique
39. A Novel Methodology for Design of Cyclic Combinational Circuits
40. Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
41. EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control
42. DESIGN OF 64-BIT SQUARER BASED ON VEDIC MATHEMATICS
43. Vedic division methodology for high‐speed very large scale integration applications
44. Improved matrix multiplier design for high‐speed digital signal processing applications
45. EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control.
46. Vedic Divider: Novel Architecture (ASIC) for High Speed VLSI Applications
47. Leakage Control of Digital Circuits Using McCMOS Technique
48. Low Power and High Speed Factorial Design in 22 nm Technology
49. Leakage Control of Digital Circuits Using McCMOS Technique.
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