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This work presents a bi-directional brain-computer interface (BD-BCI) including a high-dynamic-range (HDR) two-step time-domain neural acquisition (TTNA) system and a high-voltage (HV) multipolar neural stimulation system incorporating dual-mode time-based charge balancing (DTCB) technique. The proposed TTNA includes four independent recording modules that can sense microvolt neural signals while tolerating large stimulation artifacts. In addition, it exhibits an integrated input-referred noise of 2.3 $\mu$Vrms from 0.1- to 250-Hz and can handle a linear input-signal swing of up to 340 mVPP. The multipolar stimulator is composed of four standalone stimulators each with a maximum current of up to 14 mA ($\pm$20-V of voltage compliance) and 8-bit resolution. An inter-channel interference cancellation circuitry is introduced to preserve the accuracy and effectiveness of the DTCB method in the multipolar-stimulation configuration. Fabricated in an HV 180-nm CMOS technology, the BD-BCI chipset undergoes extensive in-vitro and in-vivo evaluations. The recording system achieves a measured SNDR, SFDR, and CMRR of 84.8 dB, 89.6 dB, and $>$105 dB, respectively. The measurement results verify that the stimulation system is capable of performing high-precision charge balancing with $\pm$2 mV and $\pm$7.5 mV accuracy in the interpulse-bounded time-based charge balancing (TCB) and artifactless TCB modes, respectively.

This brief presents a novel isolated frequency compensation (IFC) technique for ultra-low-power (ULP) low-noise two-stage operational transconductance amplifiers (OTAs) with high gain-bandwidth (GBW) products. The IFC technique stabilizes the OTA in two steps. First, it pushes the first non-dominant pole of the OTA to higher frequencies using an isolated Miller capacitor. Second, it employs a local feed-forward path to create a zero and nullify the first non-dominant pole through pole-zero cancellation. This allows the compensated OTA to reach higher GBW for a given bias current compared to conventional frequency-compensation methods. Fabricated in a standard 180-nm CMOS technology, the proposed circuit operates in sub-threshold and achieves 3 MHz of GBW and 2.3 V/ $\mu s$ of average slew rate for a 45 pF capacitive load, while consuming a total current of $1.8 ~\mu \text{A}$ from a 1.8-V supply. In addition, the proposed circuit achieves a measured common-mode rejection ratio (CMRR) of ≥ 70 dB for a bandwidth of up to 100 kHz.

This article presents a current-adjusting auto-zeroing (CAAZ) scheme that overcomes the critical shortcomings of state-of-the-art auto-zero-based offset and low-frequency noise cancellation methods. The proposed technique appropriately adjusts the bias current of individual branches within the amplifier to cancel dc offset and low-frequency noise. The CAAZ method does not suffer from thermal-noise increase due to input signal division and stability issues encountered in input auto-zero (IAZ) or limited allowable gain and input swing experienced in the output auto-zero (OAZ) method. Moreover, it does not create any feedback loop during its operation phases and, thus, does not impose additional stability restrictions on the amplifier within which it is being used. Two differential amplifiers, a single-stage differential amplifier (SSDA) and a folded-cascode amplifier (FCA), employing the proposed CAAZ technique, are designed and simulated in a standard 180-nm CMOS process. Simulation results verify the higher performance of the proposed CAAZ compared to the conventional counterparts.