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In this article, we present a crystal-less Bluetooth low-energy (BLE) transmitter using RF reference recovery directly from GFSK-modulated BLE packets. In order to achieve fast frequency calibration from modulated signals and reduce interference from other BLE users, the transceiver consists of a back-channel wake-up receiver, a clock-recovery receiver, a transmitter, and a dual-all-digital phase-locked loop (ADPLL) frequency synthesizer for system wake-up, clock-recovery, packet transmission, and frequency calibration. An embedded averaging processing unit in the loop filter of the ADPLL is proposed to retrieve accurate frequency information from GFSK-modulated signals. A prototype chip is fabricated in 40-nm CMOS for verification. The crystal-less transmitter with clock recovery meets all BLE requirements for SIR, making this a robust solution for removing the crystal even in densely populated networks.

This article presents the first demonstration of a sub-100 nW CMOS wakeup receiver (WuRx) with envelope detector (ED)-first architecture that operates at multigigahertz frequencies. The 2.2 GHz S-band WuRx can operate in two modes that show a tradeoff between power consumption and RF sensitivity. In the low-power mode, the WuRx consumes 11.3 nW and achieves an RF sensitivity of -65 dBm. In the high-sensitivity mode, the WuRx consumes 28.2 nW and achieves a sensitivity of -68 dBm. Measurement results indicate that the WuRx architecture is robust to continuous-wave in-band interferers, with as large as -20 dB carrier-to-interferer ratio.

Energy efficiency in digital circuits is limited by the subthreshold swing (SS), which defines how abruptly a transistor switches between its ON and OFF-states. The SS is particularly important for circuits targeting minimum-energy computation which operate in the subthreshold region between the ON and OFF-states of the transistor. The SS of MOSFET devices is fundamentally limited by thermionic emission, which has inspired a search for new devices whose SS can reach below the Boltzmann thermal limit. Tunnel field-effect transistors (TFETs) have emerged as a post-CMOS candidate with low (steep) SS and have been investigated using an evolving selection of geometries and materials that yield continuously improving device performance and circuit performance estimates. To unify previous works and guide future TFET iterations, this article provides a comprehensive theory on minimum-energy operation in the subthreshold region for steep-SS devices. We show that the optimal supply voltage for energy minimization and minimum obtainable energy are both proportional to the SS, and that a fundamental limit exists for the required $I_{\mathrm{\scriptstyle {ON}}}/I_{\mathrm{\scriptstyle {OFF}}}$ to achieve operation at the minimum-energy point. We explore how device knobs affect the optimization space for minimum-energy operation, and analyze how common TFET nonidealities affect the potential for minimum-energy operation.

This letter presents a reconfigurable wake-up receiver, which obtains −106-dBm sensitivity with power consumption as low as 33 nW. Bit-level duty cycling provides 68-dB RF gain at sub- $\mu \text{W}$ average power consumption, improving sensitivity over other sub- $\mu \text{W}$ receivers. The receiver rejects interference using a compact RF MEMS filter and a fully automatic gain and offset control loop. Digital tuning of dc power, latency, and sensitivity provides high levels of flexibility to enable a wide variety of applications, spanning latency from 240 ms to 5 s, dc power consumption from 288 nW to 33 nW, and sensitivity from −106 dBm to −103 dBm. Three example modes are presented to highlight the range of this tuning.

This letter presents an energy efficient, temperature-compensated frequency-locked loop (FLL) for use as an on-chip clock source. We first present a fully integrated FLL architecture that significantly improves energy efficiency by using a loop divider to boost the output frequency without requiring increased static power dissipation. We develop models for the FLL energy-per-cycle and temperature stability and use them to implement an energy-optimized and highly temperature-stable FLL design in 65-nm CMOS that achieves 20.3-ppm/°C temperature stability from −20 °C to 60 °C and an energy efficiency of 44.6-fJ/cycle at 23 °C (45.3 nW at 1.016 MHz), which is the highest energy efficiency reported to date for a fully on-chip oscillator, regardless of architecture, operating frequency, or temperature stability.

This letter presents an RISC-V microprocessor implemented using a proposed scalable dynamic leakage suppression (SDLS) logic style. Together with a custom adaptive clock generator and voltage scaling controller, the SDLS RISC-V microprocessor realizes a fully integrated modified dynamic voltage and frequency scaling (DVFS) scheme that enables nW-level performance flexibility for battery-less IoT sensing nodes in energy-scarce environments. At the nominal core VDD of 0.6 V, the core can scale its performance from 6 nW at 11-Hz operating frequency to 140 nW at 8.2-kHz operating frequency. Across the supply voltage range, the core is capable of delivering minimum power of 840 pW, maximum frequency of 41.5 kHz, and a minimum energy of 13.4 pJ/cycle.

This paper presents a 1.05 MHz, on-chip RC relaxation oscillator (ROSC) with a temperature coefficient (TC) of 2.5 ppm/°C and an absolute variation of 100 ppm over the body-compatible range of 0–40°C. The TC increases to 4.3 ppm/°C over the range from −15 °C to 55 °C. The high temperature stability is achieved using a PTAT current reference and a TC-tunable resistor bank for first-order frequency error compensation along with a digital frequency compensation (DFC) block using a single-bit temperature sensor for second-order compensation. A measured RMS period jitter of 160 ps is achieved with a high-speed comparator. The active power consumption of the ROSC is $69~\mu \text{W}$ with a 1-V supply, and the leakage power consumption is 110 nW, while power gated. The ROSC achieves a fast startup time of $8~\mu \text{s}$ by employing a voltage buffer to quickly stabilize the voltage reference.

Not all computing problems are created equal. The inherent complexity of processing certain classes of problems using digital computers has inspired the exploration of alternate computing paradigms. Coupled oscillators exhibiting rich spatio-temporal dynamics have been proposed for solving hard optimization problems. However, the physical implementation of such systems has been constrained to small prototypes. Consequently, the computational properties of this paradigm remain inadequately explored. Here, we demonstrate an integrated circuit of thirty oscillators with highly reconfigurable coupling to compute optimal/near-optimal solutions to the archetypally hard Maximum Independent Set problem with over 90% accuracy. This platform uniquely enables us to characterize the dynamical and computational properties of this hardware approach. We show that the Maximum Independent Set is more challenging to compute in sparser graphs than in denser ones. Finally, using simulations we evaluate the scalability of the proposed approach. Our work marks an important step towards enabling application-specific analog computing platforms to solve computationally hard problems., Designing efficient analog dynamical systems for solving hard optimization problems remains a challenge. Here, the authors demonstrate a dynamical system of thirty oscillators with reconfigurable coupling to compute optimal/near-optimal solutions to the hard Maximum Independent Set problem with over 90% accuracy.

This work presents an on-chip oscillator for energy-efficient IoT applications based on a duty-cycled digital frequency-locked loop (DFLL). The digital implementation allows low-voltage operation at 0.5V to reduce energy and enable voltage rail integration with low-energy digital logic, while the duty-cycled operation further improves energy efficiency to a record value of 18.8fJ/cycle (10.5nW @ 560kHz) while maintaining a high temperature stability of 96.1ppm/°C from 0°C to 100°C.

A -108dBm sensitivity, 430MHz, 130nW-41µW, 6.25bps-4.2kbps, digitally tunable wake-up and data receiver in 65nm CMOS is presented. Employing 2-tone RF OOK modulation and an AlN MEMS resonator, the receiver attains close-in SIR of -25dB at 0.12% and far-out SIR of -28dB at 0.7% frequency offset from the carrier. Digitally configurable dynamic ranges of 11dB, 410X, 672X are achieved for sensitivity, power, and latency, respectively. The design receives data at a 4.2kbps bit-rate at - 108dBm sensitivity while consuming 41µW. The proposed WuRx is a highly reconfigurable and interference robust candidate for emerging ultra-long range IoT LPWAN applications.

Wireless transceivers traditionally perform local-oscillator (LO) calibration using an external crystal oscillator (XTAL) that adds significant size and cost to a system. Removing the XTAL enables a true single-chip radio, but an alternate means for calibrating the LO is required. Integrated references like on-chip LC [1] or relaxation [2] oscillators are either high power or have PVT sensitivity too high for wireless standards. Multiple crystal-less radios address this challenge [3]–[6]. [3] replaces the XTAL with an FBAR resonator, which is still not fully integrated. [4]–[5] recover a reference clock from a received signal but take hundreds of milliseconds to lock and are thus highly susceptible to interference. [6] uses an open-loop LC oscillator to reduce power but has insufficient frequency accuracy for wireless standards.

This paper investigates the effect of body biasing on the leakage and delay of dynamic leakage suppression (DLS) logic. We present a brief theoretical analysis of the impact of body biasing on DLS logic as well as measurements from a test chip in 65nm CMOS. Results show that forward body biasing can reduce delay by up to 41X with negligible impacts on leakage.

This work presents a 33 nW wake-up receiver with -106 dBm sensitivity at 428 MHz. Within-bit duty cycling allows RF gain at nano-watt DC power levels providing 26 dB sensitivity improvement over prior art at iso-power. An RF MEMS filter and an automatic gain and offset control loop suppress noise and reject interference. The receiver can be digitally tuned across DC power, latency, and sensitivity to provide flexible functionality from indoor short range to outdoor long-range applications.

Tunnel Field Effect Transistors (TFETs) are known to be compromised by higher order processes that downgrade their performance compared to ballistic projections. Using a quasi-analytical model that extends the chemistry based Simmons equation to include finite temperature effects, potential variations and scattering, we exhibit that non-idealities like trap-assisted tunneling and Auger generation can explain the observed performance discrepancy. In particular, Auger generation is the dominant leakage mechanism in TFETs at low trap densities. Our studies suggest that possible ways of reducing Auger generation rate are reducing source carrier concentration and increasing the valence band transport effective mass of the source material. In this paper, we specifically investigate the impact of variations of these factors on device performance of staggered bandgap planar III-V heterojunction Tunnel FETs.

This work presents a 1.05 MHz on-chip RC relaxation oscillator (ROSC) design with a temperature coefficient (TC) of 2.5 ppm/°C and an absolute variation of 100 ppm over the body-compatible range of 0 to 40°C (the TC increases to 4.3 ppm/°C over the range from −15 to 55°C). The high temperature stability is achieved using a PTAT current reference and a TC-tunable resistor bank for first-order frequency error compensation along with a digital frequency compensation (DFC) block using a single-bit temperature sensor for second-order compensation. A measured RMS period jitter of 160 ps is achieved with a high-speed comparator. The active power consumption of the ROSC is 69 µW with a 1 V supply, and the leakage power consumption is 110 nW while power-gated. The ROSC achieves a fast startup time of 8 µs by employing a voltage buffer to quickly stabilize the voltage reference.

We present a quasi-analytical model for Tunnel Field Effect Transistors (TFETs) that includes the microscopic physics and chemistry of interfaces and non-idealities. The ballistic band-to-band tunneling current is calculated by modifying the well known Simmons equation for oxide tunneling, where we integrate the Wentzel-Kramers-Brillouin tunneling current over the transverse modes. We extend the Simmons equation to finite temperature and non-rectangular barriers using a two-band model for the channel material and an analytical channel potential profile obtained from Poisson’s equation. The two-band model is parametrized first principles by calibrating with hybrid Density Functional Theory calculations and extended to random alloys with a band unfolding technique. Our quasi-analytical model shows quantitative agreement with ballistic quantum transport calculations. On top of the ballistic tunnel current, we incorporate higher order processes arising at junctions coupling the bands, specifically interface trap assisted tunneling and Auger generation processes. Our results suggest that both processes significantly impact the off-state characteristics of the TFETs—Auger, in particular, being present even for perfect interfaces. We show that our microscopic model can be used to quantify the TFET performance on the atomistic interface quality. Finally, we use our simulations to quantify circuit level metrics such as energy consumption.We present a quasi-analytical model for Tunnel Field Effect Transistors (TFETs) that includes the microscopic physics and chemistry of interfaces and non-idealities. The ballistic band-to-band tunneling current is calculated by modifying the well known Simmons equation for oxide tunneling, where we integrate the Wentzel-Kramers-Brillouin tunneling current over the transverse modes. We extend the Simmons equation to finite temperature and non-rectangular barriers using a two-band model for the channel material and an analytical channel potential profile obtained from Poisson’s equation. The two-band model is parametrized first principles by calibrating with hybrid Density Functional Theory calculations and extended to random alloys with a band unfolding technique. Our quasi-analytical model shows quantitative agreement with ballistic quantum transport calculations. On top of the ballistic tunnel current, we incorporate higher order processes arising at junctions coupling the bands, specifically interface t...

Tunnel field-effect-transistors (TFETs) are promising candidates for next generation transistors for low power applications, as the TFETs promise low subthreshold swing (SS). Different from traditional MOSFET, the TFETs rely on energy-efficient switching of band-to-band tunneling (BTBT), therefore the SS in TFETs is not limited by the 60 mV/decade Boltzmann limit. This reduction in energy consumption makes TFETs suitable candidates to replace standard MOSFETs in low power applications. However, most experimentally demonstrated TFETs suffer from low on current[1], and the theoretical low SS is compromised by impurities and Auger generation. To understand the underlying physics and predict the device characteristics of TFETs, sophisticated numerical simulations can be used. On the other hand, physics based compact models are also required to provide fast predictions for existing and new device concepts. Furthermore, a physics based compact model is more efficient to model the effects like Auger generation which could be time-consuming for numerical calculations. In this work, we introduce a physics based compact model for homojunction TFETs with Auger generation effect considered. This compact model is based on the modified Simmons' equation at finite temperature[2]. With our compact model, the possible impact of Auger generation effect to off-current and SS is explored.