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Abstract This paper proposes a nanoparticle‐based atomic switch network memristive device, capable of both volatile and nonvolatile switching operations, which have not been previously reported for this material. The operational modes can be determined by altering the compliance current, demonstrating high stability over 100 cycles. Analysis of the conduction mechanism using I–V curves reveals switching characteristics consistent with space‐charge‐limited current conduction during the set process and ohmic behavior in the reset state. Furthermore, this study analyzes these dual‐operational modes in devices with varying electrode spacings. The results indicate that a wider spacing necessitated a higher compliance current for the volatile‐to‐nonvolatile transition, underscoring the significance of interconnection. These findings facilitate the integration of neuron and synapse functions within a single atomic switch network device, thereby advancing neuromorphic systems.

Abstract To reach the energy efficiency and the computing capability of biological neural networks, novel hardware systems and paradigms are required where the information needs to be processed in both spatial and temporal domains. Resistive switching memory (RRAM) devices appear as key enablers for the implementation of large-scale neuromorphic computing systems with high energy efficiency and extended scalability. Demonstrating a full set of spatiotemporal primitives with RRAM-based circuits remains an open challenge. By taking inspiration from the neurobiological processes in the human auditory systems, we develop neuromorphic circuits for memristive tonotopic mapping via volatile RRAM devices. Based on a generalized stochastic device-level approach, we demonstrate the main features of signal processing of cochlea, namely logarithmic integration and tonotopic mapping of signals. We also show that our tonotopic classification is suitable for speech recognition. These results support memristive devices for physical processing of temporal signals, thus paving the way for energy efficient, high density neuromorphic systems.

Abstract Binocular stereo vision relies on imaging disparity between two hemispherical retinas, which is essential to acquire image information in three dimensional environment. Therefore, retinomorphic electronics with structural and functional similarities to biological eyes are always highly desired to develop stereo vision perception system. In this work, a hemispherical optoelectronic memristor array based on Ag‐TiO2 nanoclusters/sodium alginate film is developed to realize binocular stereo vision. All‐optical modulation induced by plasmonic thermal effect and optical excitation in Ag‐TiO2 nanoclusters is exploited to realize in‐pixel image sensing and storage. Wide field of view (FOV) and spatial angle detection are experimentally demonstrated owing to the device arrangement and incident‐angle‐dependent characteristics in hemispherical geometry. Furthermore, depth perception and motion detection based on binocular disparity have been realized by constructing two retinomorphic memristive arrays. The results demonstrated in this work provide a promising strategy to develop all‐optically controlled memristor and promote the future development of binocular vision system with in‐sensor architecture.

Abstract Artificial Intelligence (AI) is currently experiencing a bloom driven by deep learning (DL) techniques, which rely on networks of connected simple computing units operating in parallel. The low communication bandwidth between memory and processing units in conventional von Neumann machines does not support the requirements of emerging applications that rely extensively on large sets of data. More recent computing paradigms, such as high parallelization and near-memory computing, help alleviate the data communication bottleneck to some extent, but paradigm- shifting concepts are required. Memristors, a novel beyond-complementary metal-oxide-semiconductor (CMOS) technology, are a promising choice for memory devices due to their unique intrinsic device-level properties, enabling both storing and computing with a small, massively-parallel footprint at low power. Theoretically, this directly translates to a major boost in energy efficiency and computational throughput, but various practical challenges remain. In this work we review the latest efforts for achieving hardware-based memristive artificial neural networks (ANNs), describing with detail the working principia of each block and the different design alternatives with their own advantages and disadvantages, as well as the tools required for accurate estimation of performance metrics. Ultimately, we aim to provide a comprehensive protocol of the materials and methods involved in memristive neural networks to those aiming to start working in this field and the experts looking for a holistic approach.

In this work, the requirement of using high‐precision (HP) signals is lifted and the circuits for implementing deep learning algorithms in memristor‐based hardware are simplified. The use of HP signals is required by the backpropagation learning algorithm since the gradient descent learning rule relies on the chain product of partial derivatives. However, it is both challenging and biologically implausible to implement such an HP algorithm in noisy and analog memristor‐based hardware systems. Herein, it is demonstrated that the requirement for HP signals handling is not necessary and more efficient deep learning can be achieved when using a binary stochastic learning algorithm. The new algorithm proposed in this work modifies elementary neural network operations, which improves energy efficiency by two orders of magnitude compared to traditional memristor‐based hardware and three orders of magnitude compared to complementary metal–oxide–semiconductor‐based hardware. It also provides better accuracy in pattern recognition tasks than the HP learning algorithm benchmarks.

Matrix-based computing is ubiquitous in an increasing number of present-day machine learning applications such as neural networks, regression, and 5G communications. Conventional systems based on von-Neumann architecture are limited by the energy and latency bottleneck induced by the physical separation of the processing and memory units. In-memory computing (IMC) is a novel paradigm where computation is performed directly within the memory, thus eliminating the need for constant data transfer. IMC has shown exceptional throughput and energy efficiency when coupled with crosspoint arrays of resistive memory devices in open-loop matrix-vector-multiplication and closed-loop inverse-matrix-vector multiplication (IMVM) accelerators. However, each application results in a different circuit topology, thus complicating the development of reconfigurable, general-purpose IMC systems. In this article, we present a generalized closed-loop IMVM circuit capable of performing any linear matrix operation by proper memory remapping. We derive closed-form equations for the ideal input-output transfer functions, static error, and dynamic behavior, introducing a novel continuous-time analytical model allowing for orders-of-magnitude simulation speedup with respect to SPICE-based solvers. The proposed circuit represents an ideal candidate for general-purpose accelerators of machine learning.

Abstract An ovonic threshold switch (OTS) based on chalcogenide glasses finds application as a selecting device in storage class memory (SCM) arrays. The OTS operation relies on the threshold switching, where the device switches from the off to the on state without phase transition, then the device turns off almost immediately as the voltage is reduced below a certain holding value. The physics behind the switching phenomenon has attracted wide interest due to the complicated interplay between electronic transport, joule heating and phase transition. In this work, it is shown that the current‐voltage characteristic close to the switching point carries the fingerprint of carrier multiplication. The physical mechanism of threshold switching is then explained by bipolar impact ionization leading to avalanche multiplication, which in turn gives rise to the typical S‐shaped characteristic. Numerical simulations by this physics‐based model account for the measured switching properties, namely threshold voltage and current, at various chalcogenide thicknesses and compositions. These results provide the theoretical framework for future design and optimization of OTS in memory and computing applications.

The spiking neural network (SNN), closely inspired by the human brain, is one of the most powerful platforms to enable highly efficient, low cost, and robust neuromorphic computations in hardware using traditional or emerging electron devices within an integrated system. In the hardware implementation, the building of artificial spiking neurons is fundamental for constructing the whole system. However, with the slowing down of Moore's Law, the traditional complementary metal-oxide-semiconductor (CMOS) technology is gradually fading and is unable to meet the growing needs of neuromorphic computing. Besides, the existing artificial neuron circuits are complex owing to the limited bio-plausibility of CMOS devices. Memristors with volatile threshold switching (TS) behaviors and rich dynamics are promising candidates to emulate the biological spiking neurons beyond the CMOS technology and build high-efficient neuromorphic systems. Herein, the state-of-the-art about the fundamental knowledge of SNNs is reviewed. Moreover, we review the implementation of TS memristor-based neurons, and their systems, and point out the challenges that should be further considered from devices to circuits in the system demonstrations. We hope that this review could provide clues and be helpful for the future development of neuromorphic computing with memristors.

In‐memory computing (IMC) with crosspoint arrays of resistive switching memory (RRAM) has gained wide attention for accelerating machine learning, data analysis, and deep neural networks. By IMC, matrix‐vector multiplication (MVM) can be executed in the crosspoint array in just one step, thus accelerating a broad range of tasks in machine learning and data analytics. However, a key issue for RRAM crosspoint arrays is the forming operation of the memories which limits the stability and accuracy of the conductance state in the memory device. In this work, a hardware implementation of crosspoint array of forming‐free devices for fast, energy‐efficient accelerators of MVM is reported. RRAM devices with a 1.5 nm‐thick HfO2 layer show an initial low resistance without forming and an analogue‐mode programming behavior for high‐accuracy IMC. Accurate hardware MVM is demonstrated by experimental eigenvalue/eigenvector calculation according to the power‐iteration algorithm, with a fast convergence within about ten iterations to the correct solution. Deflation technique and principal component analysis (PCA) enable the classification of the Iris dataset with 98% accuracy compared with floating‐point implementation. These results support forming‐free crosspoint arrays for accelerating advanced machine learning with IMC.

One of the objectives fostered in medical science is the so-called precision medicine, which requires the analysis of a large amount of survival data from patients to deeply understand treatment options. Tools like machine learning (ML) and deep neural networks are becoming a de-facto standard. Nowadays, computing facilities based on the Von Neumann architecture are devoted to these tasks, yet rapidly hitting a bottleneck in performance and energy efficiency. The in-memory computing (IMC) architecture emerged as a revolutionary approach to overcome that issue. In this work, we propose an IMC architecture based on resistive switching memory (RRAM) crossbar arrays to provide a convenient primitive for matrix-vector multiplication in a single computational step. This opens massive performance improvement in the acceleration of a neural network that is frequently used in survival analysis of biomedical records, namely the DeepSurv. We explored how the synaptic weights mapping strategy and the programming algorithms developed to counter RRAM non-idealities expose a performance/energy trade-off. Finally, we discussed how this application is tailored for the IMC architecture rather than being executed on commodity systems.

Nowadays, artificial neural networks (ANNs) can outperform the human brain’s ability in specific tasks. However, ANNs cannot replicate the efficient and low-power learning, adaptation, and consolidation typical of biological organisms. Here, we present a hardware design based on arrays of SiOx resistive switching random-access memory (RRAM), which allows combining the accuracy of convolutional neural networks with the flexibility of bio-inspired neuronal plasticity. In order to enable the combination of the stable and the plastic attributes of the network, we exploit the spike-frequency adaptation of the neurons relying on the multilevel programming of the RRAM devices. This procedure enhances the efficiency and accuracy of the network for MNIST, noisy MNIST (N-MNIST), Fashion-MNIST, and CIFAR-10 datasets, with inference accuracies of about 99%–89%, respectively. We also demonstrate that the hardware is capable of asynchronous self-adaptation of its operative frequency according to the fire rate of the spiking neuron, thus optimizing the whole behavior of the network. We finally show that the system enables fast and accurate filter retraining to overcome catastrophic forgetting, showing high efficiency in terms of operations per second and robustness against device non-idealities. This work paves the way for the theoretical modeling and hardware realization of resilient autonomous systems in dynamic environments.

Designing reliable and energy efficient neuromorphic computing systems for spatiotemporal coding remains a challenge. Here, the authors demonstrate a type of spike-rate-dependent plasticity based on a triplet learning scheme in a WO3−x-based second-order memristor network for spatiotemporal patterns.

Data-intensive computing applications, such as object recognition, time series prediction, and optimization tasks, are becoming increasingly important in several fields, including smart mobility, health, and industry. Because of the large amount of data involved in the computation, the conventional von Neumann architecture suffers from excessive latency and energy consumption due to the memory bottleneck. A more efficient approach consists of in-memory computing (IMC), where computational operations are directly carried out within the data. IMC can take advantage of the rich physics of memory devices, such as their ability to store analog values to be used in matrix-vector multiplication (MVM) and their stochasticity that is highly valuable in the frame of optimization and constraint satisfaction problems (CSPs). This article presents a stochastic spiking neuron based on a phase-change memory (PCM) device for the solution of CSPs within a Hopfield recurrent neural network (RNN). In the RNN, the PCM cell is used as the integrating element of a stochastic neuron, supporting the solution of a typical CSP, namely a Sudoku puzzle in hardware. Finally, the ability to solve Sudoku puzzles using RNNs with PCM-based neurons is studied for increasing size of Sudoku puzzles by a compact simulation model, thus supporting our PCM-based RNN for data-intensive computing.

Different real-world cognitive tasks evolve on different relevant timescales. Processing these tasks requires memory mechanisms able to match their specific time constants. In particular, the working memory (WM) utilizes mechanisms that span orders of magnitudes of timescales, from milliseconds to seconds or even minutes. This plentitude of timescales is an essential ingredient of WM tasks like visual or language processing. This degree of flexibility is challenging in analog computing hardware because it requires the integration of several reconfigurable capacitors of different size. Emerging volatile memristive devices present a compact and appealing solution to reproduce reconfigurable temporal dynamics in a neuromorphic network. We present a demonstration of WM using a silver-based memristive device whose key parameters, retention time and switching probability, can be electrically tuned and adapted to the task at hand. First, we demonstrate the principles of WM in a small scale hardware to execute an associative memory task. Then, we use the experimental data in two larger scale simulations, the first featuring WM in a biological environment, the second demonstrating associative symbolic WM.

One of the main goals of neuromorphic computing is the implementation and design of systems capable of dynamic evolution with respect to their own experience. In biology, synaptic scaling is the homeostatic mechanism which controls the frequency of neural spikes within stable boundaries for improved learning activity. To introduce such control mechanism in a hardware spiking neural network (SNN), we present here a novel artificial neuron based on phase change memory (PCM) devices capable of internal regulation via homeostatic and plastic phenomena. We experimentally show that this mechanism increases the robustness of the system thus optimizing the multi-pattern learning under spike-timing-dependent plasticity (STDP). It also improves the continual learning capability of hybrid supervised-unsupervised convolutional neural networks (CNNs), in terms of both resilience and accuracy. Furthermore, the use of neurons capable of self-regulating their fire responsivity as a function of the PCM internal state enables the design of dynamic networks. In this scenario, we propose to use the PCM-based neurons to design bio-inspired recurrent networks for autonomous decision making in navigation tasks. The agent relies on neuronal spike-frequency adaptation (SFA) to explore the environment via penalties and rewards. Finally, we show that the conductance drift of the PCM devices, contrarily to the applications in neural network accelerators, can improve the overall energy efficiency of neuromorphic computing by implementing bio-plausible active forgetting.

Continual learning is the ability to acquire a new task or knowledge without losing any previously collected information. Achieving continual learning in artificial intelligence (AI) is currently prevented by catastrophic forgetting, where training of a new task deletes all previously learned tasks. Here, we present a new concept of a neural network capable of combining supervised convolutional learning with bio-inspired unsupervised learning. Brain-inspired concepts such as spike-timing-dependent plasticity (STDP) and neural redundancy are shown to enable continual learning and prevent catastrophic forgetting without compromising standard accuracy achievable with state-of-the-art neural networks. Unsupervised learning by STDP is demonstrated by hardware experiments with a one-layer perceptron adopting phase-change memory (PCM) synapses. Finally, we demonstrate full testing classification of Modified National Institute of Standards and Technology (MNIST) database with an accuracy of 98% and continual learning of up to 30% non-trained classes with 83% average accuracy.

Resistive random-access memory is operated based on the formation and disruption of nanoscale conductive filaments, but a mechanistic understanding of this process remains unclear. Here, Wang et al. develop a surface-diffusion model to describe lifetime of filaments ranging from microseconds to years.

Motion detection is a primary visual function, crucial for the survival of animals in nature. Direction‐selective (DS) neurons can be found in multiple locations in the visual neural system, both in the retina and in the visual cortex. For instance, the DS ganglion cell in the retina provides a real‐time response to moving objects, which is much faster than the image recognition executed in the visual cortex. Such in‐retina biological signal processing capability is enabled by the spatiotemporal correlation within different receptive fields of the DS ganglion cells. Taking inspiration from the biological DS ganglion cells in the retina, the motion detection is demonstrated in an artificial neural network made of volatile resistive switching devices with short‐term memory effects. The motion detection arises from the spatiotemporal correlation between the adjacent excitatory and inhibitory receptive fields with short‐term memory synapses, closely resembling the physiological response of DS ganglion cells in the retina. The work supports real‐time neuromorphic processing of sensor data by exploiting the unique physics of innovative memory devices.

Summary: Memristive devices share remarkable similarities to biological synapses, dendrites, and neurons at both the physical mechanism level and unit functionality level, making the memristive approach to neuromorphic computing a promising technology for future artificial intelligence. However, these similarities do not directly transfer to the success of efficient computation without device and algorithm co-designs and optimizations. Contemporary deep learning algorithms demand the memristive artificial synapses to ideally possess analog weighting and linear weight-update behavior, requiring substantial device-level and circuit-level optimization. Such co-design and optimization have been the main focus of memristive neuromorphic engineering, which often abandons the “non-ideal” behaviors of memristive devices, although many of them resemble what have been observed in biological components. Novel brain-inspired algorithms are being proposed to utilize such behaviors as unique features to further enhance the efficiency and intelligence of neuromorphic computing, which calls for collaborations among electrical engineers, computing scientists, and neuroscientists.

In‐memory computing with cross‐point resistive memory arrays has gained enormous attention to accelerate the matrix‐vector multiplication in the computation of data‐centric applications. By combining a cross‐point array and feedback amplifiers, it is possible to compute matrix eigenvectors in one step without algorithmic iterations. Herein, time complexity of the eigenvector computation is investigated, based on the feedback analysis of the cross‐point circuit. The results show that the computing time of the circuit is determined by the mismatch degree of the eigenvalues implemented in the circuit, which controls the rising speed of output voltages. For a dataset of random matrices, the time for computing the dominant eigenvector in the circuit is constant for various matrix sizes; namely, the time complexity is O(1). The O(1) time complexity is also supported by simulations of PageRank of real‐world datasets. This work paves the way for fast, energy‐efficient accelerators for eigenvector computation in a wide range of practical applications.

Acting as artificial synapses, two‐terminal memristive devices are considered fundamental building blocks for the realization of artificial neural networks. Current memristive crossbar architectures demonstrate the implementation of neuromorphic computing paradigms, although they are unable to emulate typical features of biological neural networks such as high connectivity, adaptability through reconnection and rewiring, and long‐range spatio‐temporal correlation. Herein, self‐organizing memristive random nanowire (NW) networks with functional connectivity able to display homo‐ and heterosynaptic plasticity is reported thanks to the mutual electrochemical interaction among memristive NWs and NW junctions. In particular, it is shown that rewiring and reweighting effects observed in single NWs and single NW junctions, respectively, are responsible for structural plasticity of the network under electrical stimulation. Such biologically inspired systems allow a low‐cost realization of neural networks that can learn and adapt when subjected to multiple external stimuli, emulating the experience‐dependent synaptic plasticity that shape the connectivity and functionalities of the nervous system that can be exploited for hardware implementation of unconventional computing paradigms.

With the rise in artificial intelligence (AI), computing systems are facing new challenges related to the large amount of data and the increasing burden of communication between the memory and the processing unit. In‐memory computing (IMC) appears as a promising approach to suppress the memory bottleneck and enable higher parallelism of data processing, thanks to the memory array architecture. As a result, IMC shows a better throughput and lower energy consumption with respect to the conventional digital approach, not only for typical AI tasks, but also for general‐purpose problems such as constraint satisfaction problems (CSPs) and linear algebra. Herein, an overview of IMC is provided in terms of memory devices and circuit architectures. First, the memory device technologies adopted for IMC are summarized, focusing on both charge‐based memories and emerging devices relying on electrically induced material modification at the chemical or physical level. Then, the computational memory programming and the corresponding device nonidealities are described with reference to offline and online training of IMC circuits. Finally, array architectures for computing are reviewed, including typical architectures for neural network accelerators, content addressable memory (CAM), and novel circuit topologies for general‐purpose computing with low complexity.

Lifelong learning has deeply underpinned the resilience of biological organisms respect to a constantly changing environment. This flexibility has allowed the evolution of parallel-distributed systems able to merge past information with new stimulus for accurate and efficient brain-computation. Nowadays, there is a strong attempt to reproduce such intelligent systems in standard artificial neural networks (ANNs). However, despite some great results in specific tasks, ANNs still appear too rigid and static in real life respect to the biological systems. Thus, it is necessary to define a new neural paradigm capable of merging the lifelong resilience of biological organisms with the great accuracy of ANNs. Here, we present a digital implementation of a novel mixed supervised-unsupervised neural network capable of performing lifelong learning. The network uses a set of convolutional filters to extract features from the input images of the MNIST and the Fashion-MNIST training datasets. This information defines an original combination of responses of both trained classes and non-trained classes by transfer learning. The responses are then used in the subsequent unsupervised learning based on spike-timing dependent plasticity (STDP). This procedure allows the clustering of non-trained information thanks to bio-inspired algorithms such as neuronal redundancy and spike-frequency adaptation. We demonstrate the implementation of the neural network in a fully digital environment, such as the Xilinx Zynq-7000 System on Chip (SoC). We illustrate a user-friendly interface to test the network by choosing the number and the type of the non-trained classes, or drawing a custom pattern on a tablet. Finally, we propose a comparison of this work with networks based on memristive synaptic devices capable of continual learning, highlighting the main differences and capabilities respect to a fully digital approach.