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Since the challenges of maintaining the Moore's law - through traditional dimensional scaling or exploiting new materials properties - are becoming increasingly difficult, 3D integration technologies are gaining more and more attention and importance. At system level 3D-SOC solutions are of great interest, in particular those obtained through Wafer-to-Wafer (W2W) bonding due to superior overlay performance. In this paper we present the development of etch process modules for fine pitch via last interconnects realized on wafers with dielectric bonding and their integration in a packaging test chip, followed by electrical characterization.

An industry-friendly approach to fabricate III-V vertical FETs is demonstrated, focusing on n+/i/n + InGaAs stacks grown inside wide-field trenches defined in an oxide layer (field oxide) on 300 mm Si wafers. Two concepts of vertical nanowire patterning are evaluated here, namely: “III-V etch first” and “III-V etch last”. The latter approach is shown to have some key advantages, providing not only a superior profile for the nanowires but also enabling a simplified integration flow. A cyclic methane/hydrogen-based dry etch recipe run in combination with wet clean has been developed to obtain 160–170 nm tall InGaAs nanowires with CDs of about 30–35 nm. Oxygen-based passivation applied in plasma steps is shown to provide a better profile control compared to an ozone-based passivation utilized during wet cleaning. Finally, an optimization of the field oxide recess step is proposed and demonstrated in order to improve the flatness and control of the layers surrounding the vertical wires structure and simplify the further vertical flow processing.

Over the past few years, extreme wafer thinning has acquired more interest due to its importance in 3D stacked system architecture. This technique facilitates multi-wafer stacking for via last advanced packaging. From a cost and wafer integrity point of view, it has been demonstrated that the best process flow combines grinding with fast Si removal using Reactive Ion Etching (RIE). For this integration scheme, final thickness, and global flatness are key for subsequent steps. The wafer thinning performances are driven by several steps and can lead to lot, wafer to wafer and within wafer variations especially at the extreme edge. The first part of this study is to demonstrate stable wafer thinning with good control of the remaining Si (up to 5 μm) during the RIE process. This uses an innovative in-situ endpoint system (Near Infra-Red reflectometry) where the Si thickness is monitored whilst etching. The second part will focus on adjustment of the etch profile to compensate for incoming non-uniformity. This has been investigated from three different perspectives: Hardware modification where the ceramic ring surrounding the wafer is modified, process modification to change the etch front through changing the gas flow and plasma shape and changing the edge trim to introduce additional loading at the edge.

Enhanced EUV lithography (EUVL) resist performance, combined with optimized post processing techniques, are vital to ensure continued scaling and meet the requirements for the industry N5 node and beyond. Sequential infiltration synthesis (SIS) is a post lithography technique that has the potential to significantly improve the EUVL patterning process for stochastic nano-failures and line roughness, both major topics in EUV lithography research. SIS is an ALD-like technique that infiltrates polymeric photoresists, forming a metal framework using the lithography pattern as a template. Hardening of the photoresist improves the pattern quality and gives more flexibility to subsequent pattern transfer steps. We have evaluated the performance of SIS for an EUV Chemically Amplified Resist (CAR) platform printing 32 nm pitch line/space patterns and ultimately structures that are representative of standard semiconductor manufacturing. A combined lithography-SIS-etch process and a standard lithography-etch process were optimized for an industry relevant stack with pattern transfer into a TiN layer. This allows for the first time a justified comparison between a EUVL-SIS and a standard EUVL patterning process, showing the benefits of SIS regarding roughness, exposure latitude and nano-failure mitigation. Power Spectral Density (PSD) analysis accurately demonstrates and explains the type of roughness improvement. Nano-failure analysis is done by measuring large areas at different exposure doses and shows the improvement of the nano-failure free window when applying a EUVL-SIS patterning process. We conclude by examining to which extent combining the best lithography process with an optimized SIS step will lead to a better roughness and nano-failure performance, essential to meeting industry requirements.

The semiconductor industry has been pushing the limits of scalability by combining 193nm immersion lithography with multi-patterning techniques for several years. Those integrations have been declined in a wide variety of options to lower their cost but retain their inherent variability and process complexity. EUV lithography offers a much desired path that allows for direct print of line and space at 36nm pitch and below and effectively addresses issues like cycle time, intra-level overlay and mask count costs associated with multi-patterning. However it also brings its own sets of challenges. One of the major barrier to high volume manufacturing implementation has been hitting the 250W power exposure required for adequate throughput [1]. Enabling patterning using a lower dose resist could help move us closer to the HVM throughput targets assuming required performance for roughness and pattern transfer can be met. As plasma etching is known to reduce line edge roughness on 193nm lithography printed features [2], we investigate in this paper the level of roughness that can be achieved on EUV photoresist exposed at a lower dose through etch process optimization into a typical back end of line film stack. We will study 16nm lines printed at 32 and 34nm pitch. MOX and CAR photoresist performance will be compared. We will review step by step etch chemistry development to reach adequate selectivity and roughness reduction to successfully pattern the target layer.

Year after year, the semiconductor industry overcomes a tremendous amount of technical challenges to satisfy Moore’s law. Through innovative device architectures, smart design, new integration and patterning concepts, better tools and new materials, the industry has successfully reached the 7nm technology node. Both design and patterning options are identified and the high volume manufacturing readiness is expected end of 2018. Today, the industry is preparing for the 5nm technology node (N5) while research centers start identifying and exploring the different patterning options for the 3nm technology node. The former targets a Metal 2 Pitch (M2P) of 32nm and a Contacted Poly Pitch (CPP) of 42nm while the latter aims for a M2P of 24nm and a CPP of 32nm. At such tight metal pitches and in view of the continuous progress in EUV tool performance, a single print EUV lithography is considered as a potential patterning option for N5 to pattern critical Back-End-Of-Line (BEOL) layers such as block, via and unidirectional metal lines. However, without the emergence of improved EUV photoresist (PR) platform that meets requirements for resolution, line edge roughness and sensitivity, we can expect a very limited available PR budget for pattern transfer (between 12nm and 30nm), an increase of defects such as bridging or line interruptions and finally a degradation of the sidewall roughness. These will contribute to the total CD variation and consume an important part of the overall Edge Placement Error (EPE) budget. Hence, actual patterning methods used to smooth and transfer down the PR pattern must be significantly improved and new solutions must be explored to enable the emergence of advanced technologies. In this work, we explore different post-lithography methods to overcome challenges related to EUV-based patterning at tight pitches. Both chemically amplified PR and metal-based PR are considered and the performance of the different approaches are evaluated step-by-step using top down SEM imaging, cross-section SEM and 3D-AFM. Finally, we complete the study showing Power Spectral Density (PSD) analysis that help to understand how the roughness is distributed in the frequency domain for the different studied methods.

There is a growing interest in new spin on metal oxide hard mask materials for advanced patterning solutions both in BEOL and FEOL processing. Understanding how these materials respond to plasma conditions may create a competitive advantage. In this study patterning development was done for two challenging FEOL applications where the traditional Si based films were replaced by EMD spin on metal oxides, which acted as highly selective hard masks. The biggest advantage of metal oxide hard masks for advanced patterning lays in the process window improvement at lower or similar cost compared to other existing solutions.

Inpria metal-oxide photoresist (PR) serves as a thin spin-on patternable hard mask for EUV lithography. Compared to traditional organic photoresists, the ultrathin metal-oxide photoresist (~12nm after development) effectively mitigates pattern collapse. Because of the high etch resistance of the metal-oxide resist, this may open up significant scope for more aggressive etches, new chemistries, and novel integration schemes. We have previously shown that metal-oxide PR can be successfully used to pattern the block layer for the imec 7-nm technology node[1] and advantageously replace a multiple patterning approach, which significantly reduces the process complexity and effectively decreases the cost. We also demonstrated the formation of 16nm half pitch 1:1 line/space with EUV single print[2], which corresponds to a metal 2 layer for the imec 7-nm technology node. In this paper, we investigate the feasibility of using Inpria’s metal-oxide PR for 16nm line/space patterning. In meanwhile, we also explore the different etch process for LWR smoothing, resist trimming and resist stripping.

In this work, we explore the performances of a low-temperature PEALD technology used to trim/clean/smooth and reshape ArF photoresist lines that could subsequently receive an in-situ spacer deposition required to build up any SAxP grating. Different gas mixtures (O2, N2, H2, Ar and combinations) are evaluated on both blanket and patterned wafers. Trim rate, line profile, surface roughness and chemical modification are characterized using ellipsometry, Fourier transform infrared spectroscopy and atomic force microscopy. The photoresist line roughness is measured from top down SEM imaging and the different contributors to the roughness determined from a Power Spectral Density (PSD) analysis. Few results obtained on EUV photoresist blanket wafers using similar plasma treatments will also be briefly presented.

In this work, we present and compare two integration approaches to enable self-alignment of the block suitable for the 5- nm technology node. The first approach is exploring the insertion of a spin-on metal-based material to memorize the first block and act as an etch stop layer in the overall integration. The second approach is evaluating the self-aligned block technology employing widely used organic materials and well-known processes. The concept and the motivation are discussed considering the effects on design and mask count as well as the impact on process complexity and EPE budget. We show the integration schemes and discuss the requirements to enable self-alignment. We present the details of materials and processes selection to allow optimal selective etches and we demonstrate the proof of concept using a 16- nm half-pitch BEOL vehicle. Finally, a study on technology insertion and cost estimation is presented.

Si FinFET scaling is getting more difficult due to extremely narrow fin width control and power dissipation. Nanowire FETs and high mobility channel are attractive options for CMOS scaling. Nanowire FETs can maintain good electrostatics with relaxed nanowire diameter. High mobility channel can provide good performance at low power operation. However their fin patterning is challenging due to fins consisted of different materials or fragile high mobility material. Controlled etch and strip are necessary for good fin cd and profile control. Fin height increase is a general trend of scaled FinFETs and nanowire FETs, which makes patterning difficult not only in fin, but also in gate, spacer and replacement metal gate. It is important that gate and spacer etch have high selectivity to fins and good cd and profile control even with high aspect ratio of fin and gate. Work function metal gate patterning in scaled replacement metal gate module needs controlled isotropic etch without damaging gate dielectric. SF6 based etch provides sharp N-P boundary and improved gate reliability.

In this work, Ru wires patterning by direct etch are evaluated for a potential 5 nm technology node. The characteristics of Ru etching by varying the bias voltage, total flow rate and Cl2/(O2+Cl2) gas flow ratio are studied in an inductively couple plasma etching chamber. Ru sidewalls profile with a tapering angle of 90° and Ru to SiO2 hard mask etch selectivity of 6 are achieved. The authors show the feasibility of patterning lines with an aspect ratio up to 3.5 and lines with a critical dimension down to 10.5 nm (with a 3σ line width roughness of 4.2 nm), which paves the way to further scaling of this approach. Finally, the authors present a study on Ru line roughness after patterning on 300 mm wafers. Here, they compare line roughness results of wafers where Ru is deposited with different deposition techniques, such as atomic layer deposition and plasma vapor deposition, and it is annealed after deposition at various temperatures.In this work, Ru wires patterning by direct etch are evaluated for a potential 5 nm technology node. The characteristics of Ru etching by varying the bias voltage, total flow rate and Cl2/(O2+Cl2) gas flow ratio are studied in an inductively couple plasma etching chamber. Ru sidewalls profile with a tapering angle of 90° and Ru to SiO2 hard mask etch selectivity of 6 are achieved. The authors show the feasibility of patterning lines with an aspect ratio up to 3.5 and lines with a critical dimension down to 10.5 nm (with a 3σ line width roughness of 4.2 nm), which paves the way to further scaling of this approach. Finally, the authors present a study on Ru line roughness after patterning on 300 mm wafers. Here, they compare line roughness results of wafers where Ru is deposited with different deposition techniques, such as atomic layer deposition and plasma vapor deposition, and it is annealed after deposition at various temperatures.

Self-Aligned-Source (SAS) technology is a process option commonly used in process integration for Flash NOR. This approach is realized by removing the field oxide from the source lines of the array, which is implanted with N-type dopant, so two adjacent word lines can be fully driven by the same source contact. Since field oxide removal is demanded to a RIE, a polymer layer on cell sidewall is expected after this step. The presence of this thin organic layer during the subsequent implantation step is supposed to act as a spacer, hence modulating the effective channel length (Leff). According to the continuous shrink of memory cell, this spacer becomes relevant compared with cell dimension and can not be neglected as second order effect. It is known that polymer deposition during etching step is not a perfectly controllable phenomenon. As a consequence, fluctuations in polymer thickness yield to fluctuations in cell characteristics. So, poor run-to-run, intra-wafer and even intra-sector repeatabilities often are the results. TEM analysis and electrical validations have been reported to demonstrate the relationships between deposited polymer presence and cell parameters spread. Figure 1 below is an example of TEM data.

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