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Global thinning is a technique that enables backside failure analysis and radiation testing. In some devices, it can also lead to increased thresholds for single-event latchup and upset. In this study, we examine the impacts of global thinning on 28 nm node FPGAs. Test devices are thinned to 50, 10, and 3 μm via CNC milling. Lattice damage, in the form of dislocations, extends about 1 μm below the surface, but is removed by polishing with colloidal SiO2. As shown by finite-element modeling, thinning increases compressive global stress in the Si while solder bumps (in flip-chip packages) increase stress locally. The results are confirmed by stress measurements obtained through Raman spectroscopy, although more complex models are needed to account for nonlinear effects in devices thinned to 3 μm and heated to 125°C. Thermal imaging shows that increased local heating occurs with increased thinning, but the maximum temperature difference across the 3-μm die is less than 2°C. Ring oscillators throughout the FPGA fabric slow about 0.5% after thinning and another 0.5% when heated to 125°C, which is attributed to stress changes in the Si.

Studies of size effects on thermal conductivity typically necessitate the fabrication of a comprehensive film thickness series. In this Letter, we demonstrate how material fabricated in a wedged geometry can enable similar, yet higher-throughput measurements to accelerate experimental analysis. Frequency domain thermoreflectance (FDTR) is used to simultaneously determine the thermal conductivity and thickness of a wedged silicon film for thicknesses between 100 nm and 17 μm by considering these features as fitting parameters in a thermal model. FDTR-deduced thicknesses are compared to values obtained from cross-sectional scanning electron microscopy, and corresponding thermal conductivity measurements are compared against several thickness-dependent analytical models based upon solutions to the Boltzmann transport equation. Our results demonstrate how the insight gained from a series of thin films can be obtained via fabrication of a single sample.

This paper investigates and models the dc behavior of thin-film-based switching devices. The devices are based on sputtered vanadium dioxide thin films that transition from 200 kΩ/□ at room temperature to 390 Ω/□ at temperatures above 68°C, with the transition occurring over a narrow temperature range. The device resistance is characterized over temperature and under current- and voltage-sourced electrical bias. The finite-element model predicts the device's nonuniform switching behavior. Electrothermally heated devices show the same transition ratio and switching behavior as externally heated devices suggesting a purely electrothermal switching mechanism.

The fidelity of a Tersoff-based empirical potential model for the Ge–Si–O ternary atomic system is studied in detail, with the ultimate aim of validating the potential for later use in large-scale simulations of Ge selective epitaxial growth. Several comparisons are presented between the predictions of atomistic simulations based on the empirical potential studied here and prior experimental measurements and electronic structure calculations. The points of comparison include the structure and thermodynamics of bulk amorphous silica (a-SiO2), the a-SiO2 free surface, the c-Si/a-SiO2 interface, the c-Ge/a-SiO2 interface, and the desorption, wetting, and diffusion behavior of Ge atoms on a-SiO2 surfaces. A single fitting parameter, which describes the strength of the Ge–O interaction, is used to establish good agreement between the empirical potential predictions and experimental measurements across all points of comparison. We conclude that a Tersoff-based empirical potential, while it neglects explicit Coulombic interactions and is highly simplified, is a reasonable basis for probing certain features of the Ge/SiO2/Si material system.

We demonstrate the implementation of air-gapped SiO2 nanotemplates embedded in epitaxially grown Ge on Si for relieving stress caused by the thermal expansion coefficient mismatch between Ge and Si. The air-gap is formed around the SiO2 template during growth and eventual coalescence of adjacent Ge islands merging over the template. The stress map obtained from finite element modeling corroborates the experimental observation, suggesting that the thermal stress can be reduced nearly by half. The templates also filter threading dislocations propagating from the underlying Ge-Si interface, reducing the defect density from 9.8×108 to 4.4×107 cm-2 in the demonstration case. We further investigate the influence of threading dislocation density on the effective hole mobility in undoped Ge between substrates grown with the template and without the template. Using the Hall mobility measurements, we have obtained a peak effective hole mobility of 925 cm2/V-s at room temperature for Ge grown with the template, compared to 297 cm2/V-s for Ge grown without the template.

We study coalescence defects and their possible origins for Ge growth within parallel SiO 2 trenches created on (001) Si along [110] and [100] directions and (001) Ge substrates along [110]. Prior to coalescence, defects are not observed at the top of Ge, emerging from within trenches during lateral growth over the SiO 2 template. However, for Ge on Si growth, coalescence of Ge growing from adjacent trenches leads to twin defects and threading dislocations that originate from the top center and top corners of the SiO 2 walls, respectively. For Ge-on-Ge homoepitaxy, twins and threading dislocations are observed in Ge above the top center of the SiO 2 , but dislocations are not observed at the top corners of the SiO 2 walls. The twin defects are preferentially aligned along the same direction as channels patterned along [110] (twin density of 1.5×10 7 cm −2 ), but not for channels patterned along [100] (twin density of 2.5×10 7 cm −2 ). Finite element modeling is used to calculate the thermal stresses occurring in Ge and reveals that maximum thermal stress occurs near the top corners of the SiO 2 walls, where the threading dislocations (density of 7.2×10 7 cm −2 ) are experimentally observed in Ge grown on Si.

Nucleation and eventual coalescence of Ge islands, grown out of 5 to 7 nm diameter openings in chemical SiO 2 template and epitaxially registered to the underlying Si substrate, have been shown to generate a low density of threading dislocations (≪10 6 cm − 2 ). This result compares favorably to a threading dislocation density exceeding 10 8 cm − 2 in Ge films grown directly on Si. However, the coalesced Ge film contains a relatively high density of stacking faults (5 × 10 7 cm − 2 ), and subsequent growth of GaAs leads to an adverse root-mean-square roughness of 36 nm and a reduced photoluminescence intensity at 20% compared to GaAs grown on Ge or GaAs substrates. Herein, we find that annealing the Ge islands at 1073 K for 30 min before their coalescence into a contiguous film completely removes the stacking faults. However, the anneal step undesirably desorbs any SiO 2 not covered by existing Ge islands. Further Ge growth results in a threading dislocation density of 5 × 10 7 cm − 2 , but without any stacking faults. Threading dislocations are believed to result from the later Ge growth on the newly exposed Si where the SiO 2 has desorbed from areas uncovered by Ge islands. The morphology and photoluminescence intensity of GaAs grown on the annealed Ge is comparable to films grown on GaAs or Ge substrates. Despite this improvement, the GaAs films grown on the annealed Ge/Si exhibit a threading dislocation density of 2 × 10 7 cm − 2 and a minority carrier lifetime of 67 ps compared to 4 to 5 ns for GaAs on Ge or GaAs substrates. A second oxidation step after the high temperature anneal of the Ge islands is proposed to reconstitute the SiO 2 template and subsequently improve the quality of Ge film.

We have demonstrated the scalability of a process previously dubbed as Ge “touchdown” on Si to substantially reduce threading dislocations below 10 7 /cm 2 in a Ge film grown on a 2 inch-diameter chemically oxidized Si substrate. This study also elucidates the overall mechanism of the touchdown process. The 1.4 nm thick chemical oxide is first formed by immersing Si substrates in a solution of H 2 O 2 and H 2 SO 4 . Subsequent exposure to Ge flux creates 3 to 7 nm-diameter voids in the oxide at a density greater than 10 11 /cm 2 . Comparison of data taken from many previous studies and ours shows an exponential dependence between oxide thickness and inverse temperature of void formation. Additionally, exposure to a Ge or Si atom flux decreases the temperature at which voids begin to form in the oxide. These results strongly suggest that Ge actively participates in the reaction with SiO 2 in the void formation process. Once voids are created in the oxide under a Ge flux, Ge islands selectively nucleate within the void openings on the newly exposed Si. Island nucleation and growth then compete with the void growth reaction. At substrate temperatures between 823 and 1053 K, nanometer size Ge islands that nucleate within the voids continue to grow and coalesce into a continuous film over the remaining oxide. Coalescence of the Ge islands is believed to result in the creation of stacking faults in the Ge film at a density of 5 × 10 7 /cm 2 . Additionally, coalescence results in films of 3 µm thickness having a root-mean-square roughness of 8 to 10 nm. We have found that polishing the films with dilute H 2 O 2 results in roughness values below 0.5 nm. However, stacking faults originating at the Ge–SiO 2 interface and terminating at the Ge surface are polished at a slightly reduced rate, and show up as 1 to 2 nm raised lines on the polished Ge surface. These lines are then transferred into the subsequent growth morphology of GaAs deposited by metal-organic chemical vapor deposition. Room temperature photoluminescence shows that films of GaAs grown on Ge-on-oxidized Si have an intensity that is 20 to 25% compared to the intensity from GaAs grown on commercial Ge or GaAs substrates. Cathodoluminescence shows that nonradiative defects occur in the GaAs that spatially correspond to the stacking faults terminating at the Ge surface. The exact nature of these nonradiative defects in the GaAs is unknown, however, GaAs grown on annealed samples of Ge-on-oxidized Si, whereby annealing removes the stacking faults, have photoluminescence intensity that is comparable to GaAs grown on a GaAs substrate.

We describe efforts to epitaxially integrate GaAs with Si, using thin, relaxed Ge layers. The Ge films are deposited by molecular beam epitaxy using a self-assembled, selective-area growth technique, where atomic Ge etches an SiO 2 mask layer and then grows from pores extending to the Si substrate. The resulting Ge film coalesces over the SiO 2 mask and is planarized, using H 2 O 2 -based chemical–mechanical polishing. We subsequently deposit a GaAs/AlAs heterostructure on the polished Ge on Si substrate by metal-organic vapor phase epitaxy. While the initial Ge films were completely relaxed and dislocation-free, they contain a high density of stacking faults that propagate through the GaAs/AlAs heterostructure. These stacking faults create phase domains that appear as non-radiative recombination centers in cathodoluminescence images. Further development of two-step Ge epitaxy with an anneal near the Ge melting point eliminates stacking faults in the Ge, but decomposes the SiO 2 mask allowing threading dislocations to form and propagate through the GaAs/AlAs heterostructure. We discuss our strategy to prevent the loss of the SiO 2 mask and thus reduce threading dislocations.

We have measured the time evolution of Ge nucleation density on SiO 2 over a temperature range of 673–973 K and deposition rates from 5.1 × 10 13 atoms/cm 2 s (5 ML/min) to 6.9 × 10 14 atoms/cm 2 s (65 ML/min) during molecular beam epitaxy. The governing equations from mean-field theory that describe surface energetics and saturation nucleation density are used to determine the size and binding energy of the critical Ge nucleus and the activation energy for Ge surface diffusion on SiO 2 . The critical nucleus size is found to be a single Ge atom over substrate temperatures from 673 to 773 K, whereas a three-atom nucleus is found to be the critical size over substrate temperatures from 773 to 973 K. We have previously reported 0.44 ± 0.03 eV for the Ge desorption activation energy from SiO 2 . This value, in conjunction with the saturation nucleation density as a function of substrate temperature, is used to determine that the activation energy for surface diffusion is 0.24 ± 0.05 eV, and the binding energy of the three-atom nucleus is 3.7 ± 0.1 eV. The values of the activation energy for desorption and surface diffusion are in good agreement with previous experiments of metals and semiconductors on insulating substrates. The small desorption and surface diffusion activation barriers predict that selective growth occurring on window-patterned samples is by direct impingement of Ge onto Si and ready desorption of Ge from SiO 2 . This prediction is confirmed by the small integral condensation coefficient for Ge on SiO 2 and two key observations of nucleation behavior on the window-patterned samples. The first observation is the lack of nucleation exclusion zones around the windows, and second is the independence of the random Ge nucleation density on patterned versus unpatterned oxide surfaces. We also present the Ge nucleation density as a function of substrate temperature and deposition rate to demarcate selective growth conditions for Ge on Si with a window-patterned SiO 2 mask.

Conversion of plane waves to surface waves prior to detection allows key advantages in changes to the architecture of the detector pixels in a focal plane array. We have integrated subwavelength patterned metal nanoantennas with various detector materials to incorporate these advantages: midwave infrared indium gallium arsenide antimonide detectors and longwave infrared graphene detectors. Nanoantennas offer a means to make infrared detectors much thinner by converting incoming plane waves to more tightly bound and concentrated surface waves. Thinner architectures reduce both dark current and crosstalk for improved performance. For graphene detectors, which are only one or two atomic layers thick, such field concentration is a necessity for usable device performance, as single pass plane wave absorption is insufficient. Using III-V detector material, we reduced thickness by over an order of magnitude compared to traditional devices. We will discuss Sandia’s motivation for these devices, which go beyond simple improvement in traditional performance metrics. The simulation methodology and design rules will be discussed in detail. We will also offer an overview of the fabrication processes required to make these subwavelength structures on at times complex underlying devices based on III-V detector material or graphene on silicon or silicon carbide. Finally, we will present our latest infrared detector characterization results for both III-V and graphene structures.

The effect of defects on the dark current characteristics of MWIR, III-V nBn detectors has been studied. Two different types of defects are compared, those produced by lattice mismatch and by proton irradiation. It is shown that the introduction of defects always elevates dark currents; however the effect on dark current is different for nBn detectors and conventional photodiodes. The dark currents of nBn detectors are found to be more tolerant of defects compared to pn-junction based devices. Defects more weakly increase dark currents, and cooling reduces the defect-produced dark currents more rapidly in nBn detectors than in conventional photodiodes.

We show simulation results of the integration of a nanoantenna in close proximity to the active material of a photodetector. The nanoantenna allows a much thinner active layer to be used for the same amount of incident light absorption. This is accomplished through the nanoantenna coupling incoming radiation to surface plasmon modes bound to the metal surface. These modes are tightly bound and only require a thin layer of active material to allow complete absorption. Moreover, the nanoantenna impedance matches the incoming radiation to the surface waves without the need for an antireflection coating. While the nanoantenna concept may be applied to any active photodetector material, we chose to integrate the nanoantenna with an InAsSb photodiode. The addition of the nanoantenna to the photodiode requires changes to the geometry of the stack beyond the simple addition of the nanoantenna and thinning the active layer. We will show simulations of the electric fields in the nanoantenna and the active region and optimized designs to maximize absorption in the active layer as opposed to absorption in the metal of the nanoantenna. We will review the fabrication processes.

We have fabricated low-dark-current InGaAs photodetectors utilizing an epitaxial structure incorporating an InAlGaAs passivation layer and a simple mesa isolation process, and requiring no implant or diffusion steps. At 295 K, areal and perimeter dark current contributions are 15 nA/cm 2 and 9 pA/cm, respectively, in devices with large aspect ratios biased at -0.1 V. High responsivity was achieved even at zero bias in these devices. Devices were modeled using a commercial drift-diffusion simulator. Good fits to reverse dark current-voltage measurements were obtained using a model that included both bulk and interfacial generation mechanisms. Assuming similar electron and hole Shockley-Read-Hall lifetimes, dark current under small reverse bias are consistent with generation at the interface between the absorber and underlying layers. With increasing negative bias a large increase in dark current is associated with depletion near the InAlGaAs/absorber interface, while small increases in current at large reverse bias suggest long Shockley-Read-Hall lifetimes in the absorber. Forward biasing of these devices results in efficient injection of minority carrier holes into the absorber region, mimicking photogeneration and providing a method to predict the performance of illuminated detector arrays.

The concept for a new, frequency-selective limiting filter is presented. This is accomplished by placing a phase change vanadium dioxide (VO2) film at the proper node of the filter. When the high-powered microwave signal reaches a certain threshold, the VO2 undergoes a phase transition from the monoclinic “insulator state” to the tetragonal “metallic state”. This crystallographic change is accompanied by a 3 order of magnitude drop in the film's resistivity, and creates a short circuit at a section of the filter, changing a pole to a zero, and rejecting further undesirable high-powered signals from damaging sensitive receiver components. This paper details the design and simulation of the filter, along with measurement results from VO2 films and the filter element. This filter element begins rejecting at about 2 W input power, with isolation of over 16 dB to over 23 W input power, and is unaffected by an out-of band interferer of over 25 W. The architecture presented allows for filter banks capable of automatically-rejecting interferers, yet allowing signals of interest to pass.

We demonstrate the effects of integrating a nanoantenna to a midwave infrared (MWIR) focal plane array (FPA). We model an antenna-coupled photodetector with a nanoantenna fabricated in close proximity to the active material of a photodetector. This proximity allows us to take advantage of the concentrated plasmonic fields of the nanoantenna. The role of the nanoantenna is to convert free-space plane waves into surface plasmons bound to a patterned metal surface. These plasmonic fields are concentrated in a small volume near the metal surface. Field concentration allows for a thinner layer of absorbing material to be used in the photodetector design and promises improvements in cutoff wavelength and dark current (higher operating temperature). While the nanoantenna concept may be applied to any active photodetector material, we chose to integrate the nanoantenna with an InAsSb photodiode. The geometry of the nanoantenna-coupled detector is optimized to give maximal carrier generation in the active region of the photodiode, and fabrication processes must be altered to accommodate the nanoantenna structure. The intensity profiles and the carrier generation rates in the photodetector active layers are determined by finite element method simulations, and iteration between optical nanoantenna simulation and detector modeling is used to optimize the device structure.

Carrier lifetime and dark current measurements are reported for a mid-wavelength infrared InAs0.91Sb0.09 alloy nBn photodetector. Minority carrier lifetimes are measured using a non-contact time-resolved microwave technique on unprocessed portions of the nBn wafer and the Auger recombination Bloch function parameter is determined to be |F1F2|=0.292. The measured lifetimes are also used to calculate the expected diffusion dark current of the nBn devices and are compared with the experimental dark current measured in processed photodetector pixels from the same wafer. Excellent agreement is found between the two, highlighting the important relationship between lifetimes and diffusion currents in nBn photodetectors.

We report the electrical characteristics of Schottky contacts and high-hole-mobility, enhancement-mode, p-channel metal semiconductor field effect transistors (MESFETs) fabricated on Ge epitaxially grown on Si substrates. The Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. The device performance is characterized primarily as a function of threading dislocation density in the epitaxial Ge film (2 × 107, 5 × 107, 7 × 107, and 2 × 108 cm−2) and dielectric layers (SiO2, Al2O3, and HfO2) inserted between gate metal and Ge. The thin dielectric layers (∼1.3 nm) are used to unpin the Fermi level. The device performance improves with decreasing threading dislocation density and the use of HfO2. The hole mobility in the Ge film with 2 × 107 cm−2 dislocation density, obtained from Hall measurements, is 1020 cm2/V-s. Capacitance-voltage measurements on Schottky contacts provide the energy-dependent interfacial trap density of 6 × 1011 cm−2 eV−1, while current...

High-quality Ge-on-Si heterostructures have been explored for many applications, including near infrared photodetectors and integration with III–V films for multijunction photovoltaics. However, the lattice mismatch between Ge and Si often leads to a high density of defects. Introducing annealing steps prior to and after full Ge island coalescence is found to reduce the defect density. The defect density in Ge is also found to decrease with increasing dopant density in Si substrates, likely due to the defect pinning near the Ge-Si interface by dopants. The authors establish an empirical correlation between the minority carrier lifetime (τG) and the defect density in the Ge film (ρD) as a function of distance from the Ge-Si interface: τGe = C/ρD, where C is a proportionality constant and a fitting parameter which is determined to be 0.17 and 0.22 s/cm2 for Ge films grown on low-doped, high-resistivity Si substrates and high-doped, low-resistivity Si substrates, respectively. The effective minority carrier ...

The effect of Cr doping on electrical and optical properties of CrxV1−xO2 thin films across the metal-insulator transition has been studied. Resistance, Hall effect, and infrared reflectance show that Cr doping systematically increases the transition temperature Tc from 59 °C at x = 0 to 70 °C at x = 0.11 with similar transition width and hysteresis from DC to infrared, but the effect appears to saturate. The conductance contrast between insulating and metallic phases decreases with Cr doping. The effects of carrier density and mobility changes across Tc will be discussed.

InPSb and InAsPSb have been investigated for use as absorber materials in GaSb-based n-type/barrier/n-type (nBn) detectors with cutoff wavelengths shorter than 4.2 μm. The growth temperature window for high-quality InPSb lattice-matched to GaSb by molecular beam epitaxy is approximately 440–460 °C. InPSb films with thicknesses greater than approximately 1 μm or films grown outside this temperature window have high densities of large defects, with films grown at lower temperatures exhibiting evidence of significant phase separation. In contrast, InAsPSb films can be grown with excellent surface morphologies and no apparent phase separation over a wide temperature range. InAsPSb samples with low-temperature photoluminescence between 3.0 and 3.4 μm and lattice mismatch of less than 1 × 10−3 have been grown, although both photoluminescence and x-ray diffraction data exhibit peak splitting indicative of compositional nonuniformity. AlAsSb-barrier nBn detectors with InPSb and InAsPSb absorbers have been fabrica...

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We have developed a unique method of reducing the threading dislocation density in Ge epitaxially grown on Si. A heteroepitaxial layer of Ge is initially grown on Si substrate in which the threading dislocation density is 2.6 x 108 cm-2. The Ge film is etched to produce pits on the surface that correspond to the location of threading dislocations. The Ge surface with etch pits is processed further to produce a 15 nm thick layer of SiO2 within the etch pits, but not on the top planar Ge film surface. Further lateral and selective epitaxial Ge growth results in a Ge film that forms and coalesces over the SiO2 lined etch pits. The SiO2 blocks the threading dislocations from propagating into the subsequent Ge epilayer. Etching the subsequent Ge epilayer reveals a density of 1.7 x 106 cm-2 threading dislocations. This corresponds to a decrease in the overall defect density by a factor of 31 compared to the initial Ge on Si layer. The threading dislocations likely result from shallow etch pits in which SiO2 is inadvertently removed from the pit during one of the processing steps. The dislocations in pits without SiO2 continue to propagate into the subsequent Ge epilayer. Reducing the dislocation density in the initial Ge layer should result in fewer defects in the subsequent Ge layer, making the layer suitable for electronic device fabrication.

We demonstrate that SiO2 nanotemplates embedded in epitaxial Ge grown on Si relieve the stress caused by the thermal expansion mismatch between Ge and Si. The templates also filter threading dislocations propagating from the underlying Ge-Si interface, reducing the density from 9.8 × 108 to 1.6 × 107 cm−2. However, we observe that twin defects form upon Ge coalescence over the template, and the density is approximately 2.8 × 107 cm−2. The coalescence occurs without direct contact with SiO2, leaving a void between Ge and SiO2 that further reduces the thermal stress. The stress obtained from finite element modeling corroborates the experimental observation.

We have previously reported that Ge films formed after nucleation of Ge islands within nanometer size openings in SiO2 and their subsequent coalescence over the SiO2 template exhibit threading dislocation densities below 106 cm−2. However, these films contain a density of twin/stacking fault defects on the order of 5 × 1010 cm−2 that emanate primarily from the Ge-SiO2 interface. Most of these faults self-terminate within 200 nm of the interface; however, a total of 5 × 107 cm−2 propagate to the Ge surface. These defects are found to be detrimental to the morphology and minority carrier lifetime in III-V films integrated onto the Ge-on-Si virtual substrates. We have found that annealing the Ge islands during the initial stage of coalescence eliminates stacking faults, but further Ge growth leads to a film containing a threading dislocation density of 5 × 107 cm−2. To explain the origin of the twin/stacking fault defects in the Ge films and their removal after annealing Ge islands, we have studied the Ge is...

We report a technique that significantly reduces threading dislocations in Ge on Si heteroepitaxy. Germanium is first grown on Si and etched to produce pits in the surface where threading dislocations terminate. Further processing leaves a layer of SiO2 only within etch pits. Subsequent selective epitaxial Ge growth results in coalescence above the SiO2. The SiO2 blocks the threading dislocations from propagating into the upper Ge epilayer. With annealed Ge films grown on Si, the said method reduces the defect density from 2.6 × 108 to 1.7 × 106 cm−2, potentially making the layer suitable for electronic and photovoltaic devices.

Tantalum oxide films were deposited by pulsed and continuous wave (CW) plasma-enhanced chemical vapor deposition (PECVD). The pulsed films were stoichiometric and free of impurities as measured by X-ray photoelectron spectroscopy and Fourier transform infrared spectroscopy. CW films contained significant amounts of hydroxyl impurities, resulting in a nonstoichiometric composition with an O/Ta ratio of ∼2.8. Impedance spectroscopy was used to quantify ion transport through electrochromic half-cells formed by depositing tantalum oxide on both tungsten and vanadium oxides. Logarithmic plots of the imaginary component of impedance vs frequency were employed to extract equivalent circuit parameters. Despite the differences in composition the pulsed and CW films displayed similar ionic conductivities, with values of ∼ 6 X 10- 10 and 2 × 10 -10 S/cm for H + and Li + , respectively. However, the pulsed PECVD films displayed dramatically reduced electrical leakage. The ratio of ion/ electron conductivity exceeded 100 for pulsed PECVD films, while σ ion /σ e was < 1 in CW material.