Search

This paper presents a fully MOSFET DC voltage limiter with low current consumption. In the proposed voltage reference structure to reduce power consumption, transistors are biased in the sub-threshold region. To generate complementary to absolute temperature (CTAT) voltage in the voltage reference circuit, only a PMOS transistor is used, in which its drain, gate, and source terminals are connected together and acts as a diode that reduces the layout area occupation. To further reduce power consumption, a part of the rectifier output voltage is compared with the reference voltage by the sampling circuit. Also, four stage inverters are used as buffers to provide the I-V limiting characteristic closer to the ideal situation. The use of series pass-gate transistors in the first inverter also reduces power consumption as much as possible. The results of post-layout simulation based on 0.18μm CMOS technology depict that the suggested voltage reference circuit has a reference voltage equivalent to 0.579 V with a TC of 37.2 ppm/°C in the temperature range of -50°C to 50°C. LR and PSRR attained 0.008%/V and 45 dB, respectively. The output voltage and current consumption of the limiter circuit are 2 V and 32.13 nA, respectively. The total layout area of the proposed limiter is 3249 μm2. [ABSTRACT FROM AUTHOR]

Real-time monitoring solution is essential for the perishable food to estimate the food quality and to predict its shelf life. In this paper an on-chip temperature sensor which is applicable for UHF RFID passive tag is proposed. MOSFET is used as the sensitive element to the temperature. Since the transistors are biased in sub-threshold region, the power consumption is decreased. To converting proportional-to-absolute-temperature (PTAT) and complimentary-to-absolute-temperature (CTAT) voltages to the digital code, the delay generator and 8-bit ripple counter are utilized. For designing binary counter, a low power and high speed D-flip flap (D-FF) based on gate diffusion input (GDI) technique is employed. The proposed temperature sensor dissipates 110 nW power while the supply voltage is 0.5 V. Simulated in TSMC 0.18 µm CMOS technology, the total chip area is 0.0104 mm² and the error is –0.3/0.7°C in the temperature range of –20°C to 10°C. [ABSTRACT FROM AUTHOR]

In this paper, an amplitude shift keying (ASK) demodulator with 100% modulation depth is proposed. In order to achieve the higher power and wider reading range the designed ASK demodulator works in the ultra-high frequency. In this design, the average detector and voltage divider are used in order to define the appropriate threshold voltage level for the radio frequency input signal which leads to the accurate data detecting even at long distances between the tag and reader. In addition, for diminishing the power dissipation of the proposed demodulator, an enable input is used in the buffer and comparator. This circuit is simulated in 0.18 μm complementary metal–oxide–semiconductor (CMOS) technology with Cadence software. Its power dissipation and chip area are 3.9 nW and 0.0025 mm2, respectively. [ABSTRACT FROM PUBLISHER]

In this paper a low power and low output ripple regulator is designed with teaching-learning-based optimization (TLBO) for radio frequency identification applications. In order to decrease the power consumption the voltage of regulator sub-blocks is supplied from elementary stages. In the proposed operational amplifier employed to the regulator, adaptive biasing is used and bandgap reference of the regulator is totally designed by MOSFET. To optimize the proposed regulator after modeling the regulator with the help of neural network, TLBO algorithm is used. The outputs of TLBO are output voltage, ripple value and power consumption. By using this algorithm the output voltage is 0.8 V with 2.78 mV ripple and $$115\,\upmu \hbox {W}$$ power consumption. Also the quiescent current of this design is decreased to 290 nA. The chip area of the layout design in Cadence software is about $$0.00124\,\hbox {mm}^2$$ . The operation frequency of this circuit is 960 MHz and the simulation is done in $$0.18\,\upmu \hbox {m}$$ CMOS technology. [ABSTRACT FROM AUTHOR]