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A comprehensive physics-based modeling framework for electromigration (EM) in copper nano-interconnects is presented. It combines the three stages of stress evolution, void nucleation, and void dynamics in a single fully coupled and consolidated platform. Mechanical stress evolution, pre- and post-void nucleation, and its impact on void dynamics are deciphered, which enables accurate predictions of EM aging processes as validated by dedicated EM experiments. Subsequently, the experimentally validated model is utilized to shed light on the impact of a number of manufacturing variables, namely, line extension, via taper angle, and the effectiveness of the via bottom flux divergence point. A linear correlation between the ion leakage through the via bottom barrier and the peak tensile stress at the cathode was observed in long lines. In short lines, a blocked cathode end with atomic leakage through the anode end weakens the back-stress effect and threatens the Blech effect induced interconnect immortality. Increasing the line extension length was shown to increase the EM lifetime by about 40%. This impact was saturated beyond 1 critical dimension of line extension. On the other hand, the via taper angle increased the upstream EM lifetime by about twofold when the taper angle was increased from 0° to 30°, which indicates that the change of via taper angle has a stronger impact on EM lifetime compared to the line extension. [ABSTRACT FROM AUTHOR]

A recent development in educational accountability is a risk-based approach, in which intensity and frequency of school inspections vary across schools to make educational accountability more efficient and effective by enabling inspectorates to focus on organizations at risk. Characteristics relevant in predicting which schools are "at risk on adverse effects" and robustness of results of risk-based analyses over multiple cohorts were assessed by an empirical analysis of Dutch primary schools. Adverse effects were defined as below average final achievement and/or below average value added. School composition, previous underperformance, insufficient judgments on having a systematic evaluation approach, evaluation of support, and monitoring student performance appeared as factors related to subsequent underperformance of schools. Although a rich set of possible risk factors was available, further investigation of a large number of schools is required in order to find nearly all underperforming schools. However, a group of about 40% of the schools showed very small risk on underperformance, which represents the efficiency gain when risk-based school accountability would be applied. Furthermore, whether schools are (in)accurately classified in the risk analysis as "at-risk" schools depends heavily on the chosen caesura.

Continuous scaling of integrated circuits has led to the introduction of highly porous low dielectric constant (low-k) materials, whose inferior mechanical properties raise concerns regarding the reliability of integrated circuits. Nanoindentation is proven to be a straightforward method to study mechanical properties of films. However, in the case of low-k, the measurement and analysis are complex due to the porous nature of the films and reduced film thicknesses which give rise to substrate effects. A methodology that combines nanoindentation experiments with finite-element simulations is proposed and validated in this study to extract the substrate-free elastic modulus of porous ultra-thin low-k films. Furthermore, it is shown that imperfections of the nanoindentation probe significantly affect the finite-element results. An effective analytical method that captures the actual nanoindenter behavior upon indentation is proposed by taking both tip radius and conical imperfections into account. Using this method combined with finite element modeling, the elastic modulus of sub-100 nm thick low-k films is successfully extracted. Standard indentation tests clearly overestimated the actual modulus for such thin films, which emphasizes the importance of the proposed methodology. [ABSTRACT FROM AUTHOR]

Stress-Induced Leakage Current (SILC) behavior during the dielectric degradation of ultra-porous SiOCH low-k materials was investigated. Under high voltage stress, SILC increases to a critical value before final hard breakdown. This SILC increase rate is mainly driven by the injected charges and is negligibly influenced by temperature and voltage. SILC is found to be transient and shows a t-1 relaxation behavior, where t is the storage time at low voltages. This t-1 transient behavior, described by the tunneling front model, is caused by both electron charging of neutral defects in the dielectric close to the cathode interface and discharging of donor defects close to the anode interface. These defects have a uniform density distribution within the probed depth range, which is confirmed by the observed flat band voltage shift results collected during the low voltage storage. By applying an additional discharging step after the low voltage storage, the trap energies and spatial distributions are derived. In a highly degraded low-k dielectric, the majority of defects have a trap depth between 3.4 eV and 3.6 eV and a density level of 1×1018 eV-1 cm-3. The relation between the defect density N and the total amount of the injected charges Q is measured to be sub-linear, N~Q0.45±0.07. The physical nature of these stress-induced defects is suggested to be caused by the degradation of the Si- O based skeleton in the low-k dielectric. [ABSTRACT FROM AUTHOR]

The degradation and breakdown mechanisms of a SiOCH low-k material with k=2.3 (25% porosity) and thicknesses ranging from 90 nm to 20 nm were investigated. By combining the time dependent dielectric breakdown data at positive/negative bias stress with the thickness scaling results, dielectric failure is proven to be intrinsic and not influenced by copper drift or metal barrier deposition induced dielectric damage. It is shown that stress induced leakage current (SILC) can be used as a measure of dielectric degradation. Therefore, low field lifetimes can be safely estimated using SILC extrapolation. Based on our results, both the impact damage model and the power law model have a good accuracy for low field lifetime prediction. Recovery and anneal experiments are used to study the physical nature causing the observed negative flatband voltage shifts in our metal-insulator-semiconductor planar capacitor structures, where hydrogen induced unstable fast and slow donor type interface states are hypothesized to be the root cause of the observed shifts. We suggest that atomic hydrogen is released from the dielectric during electron injection and migrates to the interfacial region. Our model is further supported by an observed irreversible SILC change during the recovery and anneal studies. The degradation mechanism proposed in this work, supported by the low field lifetime data, provides a feasible explanation for intrinsic low-k dielectric failure. [ABSTRACT FROM AUTHOR]