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Focusing on the motion control problem of two link manipulator, three deep reinforcement learning models named the deep deterministic policy gradient (DDPG), asynchronous advantage actor-critic(A3C) and distributed proximal policy optimization (DPPO) are established for training according to the target setting, state variables and reward & punishment mechanism of the environment model. And then the motion control of two link manipulator is realized. After comparing and analyzing the three models, the traditional DDPG approach based on action noise converges faster and has a higher average reward compared to the other two algorithms. So, DDPG approach based on parameter noise is designed for further research to improve its applicability, so as to cut down the debugging time of the manipulator model and reach the goal smoothly. The experimental results indicate that the DDPG approach based on parameter noise can control the motion of two link manipulator effectively. The convergence speed of the control model is significantly promoted and the stability after convergence is improved. In comparison with the traditional control approach, the DDPG control approach based on parameter noise has higher efficiency and stronger applicability. [ABSTRACT FROM AUTHOR]

This paper introduces an innovative approach aimed at enhancing software reliability by integrating testing coverage within a nonhomogeneous Poisson process (NHPP). The reliability of software holds paramount significance for both developers and users, hinging on precise reliability estimations. In this paper, three real-world datasets are used to examine goodness-of-fit of the proposed model and the performance is compared with 11 other existing NHPP models. The performance of all the models is evaluated using five goodness-of-fit criteria including mean square error (MSE), Akaike's information criterion (AIC), Bayesian information criterion (BIC), predictive risk ratio (PRR) and Pham's criterion (PC). The results reveal that, when it comes to predictive power and goodness-of-fit, our proposed model surpasses the other models. [ABSTRACT FROM AUTHOR]

The Sc2.0 global consortium to design and construct a synthetic genome based on the Saccharomyces cerevisiae genome commenced in 2006, comprising 16 synthetic chromosomes and a new-to-nature tRNA neochromosome. In this paper we describe assembly and debugging of the 902,994-bp synthetic Saccharomyces cerevisiae chromosome synXVI of the Sc2.0 project. Application of the CRISPR D-BUGS protocol identified defective loci, which were modified to improve sporulation and recover wild-type like growth when grown on glycerol as a sole carbon source when grown at 37˚C. LoxPsym sites inserted downstream of dubious open reading frames impacted the 5' UTR of genes required for optimal growth and were identified as a systematic cause of defective growth. Based on lessons learned from analysis of Sc2.0 defects and synXVI, an in-silico redesign of the synXVI chromosome was performed, which can be used as a blueprint for future synthetic yeast genome designs. The in-silico redesign of synXVI includes reduced PCR tag frequency, modified chunk and megachunk termini, and adjustments to allocation of loxPsym sites and TAA stop codons to dubious ORFs. This redesign provides a roadmap into applications of Sc2.0 strategies in non-yeast organisms. The Sc2.0 project involved synthesis and debugging of 16 chromosomes, and a tRNA neochromosome. Here the authors descript the SynXVI project, accompanied by an analysis of how similar projects could operate with hindsight and newly available technologies, and lessons learned from Sc2.0. [ABSTRACT FROM AUTHOR]

When developing general-purpose robot software components, we often lack complete knowledge of the specific contexts in which they will be executed. This limits our ability to make predictions, including our ability to detect program bugs statically. Since running a robot is an expensive task, finding errors at runtime can prolong the debugging loop or even cause safety hazards. This paper proposes an approach to help developers catch these errors as soon as we have some context (typically at pre-launch time) with minimal additional efforts. We use embedded domain-specific language (DSL) techniques to enforce early checks. We describe design patterns suitable for robot programming and show how to use these design patterns for DSL embedding in Python, using two case studies on an open-source robot skill platform SkiROS2, designed for the composition of robot skills. These two case studies help us understand how to use DSL embedding on two abstraction levels: the high-level skill description that focuses on what the robot can do and under what circumstances and the lower-level decision-making and execution flow of tasks. Using our DSL EzSkiROS, we show how our design patterns enable robotics software platforms to detect bugs in the high-level contracts between the robot's capabilities and the robot's understanding of the world. We also apply the same techniques to detect bugs in the lower-level implementation code, such as writing behavior trees (BTs), to control the robot's behavior based on its capabilities. We perform consistency checks during the code deployment phase, significantly earlier than the typical runtime checks. This enhances the overall safety by identifying potential issues with the skill execution before they can impact robot behavior. An initial study with SkiROS2 developers shows that our DSL-based approach is useful for finding bugs early and thus improving the maintainability of the code. [ABSTRACT FROM AUTHOR]

This paper highlights the most significant enhancements made to PaRSEC, a scalable task-based runtime system designed for hybrid machines, during the Exascale Computing Project (ECP). The enhancements focus on expanding the capabilities of PaRSEC to address the evolving landscape of parallel computing. Notable achievements include the integration of support for three major types of accelerators (NVIDIA, AMD, and Intel GPUs), the refinement and increased flexibility of the communication subsystem, and the introduction of new programming interfaces tailored for irregular applications. Additionally, the project resulted in the development of powerful debugging and performance analysis tools aimed at assisting users in understanding and optimizing their applications. We present a comprehensive demonstration of these advancements through a series of benchmarks and applications within ECP and beyond, thereby showcasing the enhanced capabilities of PaRSEC across the diverse architectures within the ECP, providing valuable insights into the runtime system's adaptability and performance across varied computing environments. [ABSTRACT FROM AUTHOR]

In recent years, automation has become a key focus in software development as organizations seek to improve efficiency and reduce time-to-market. The integration of artificial intelligence (AI) tools, particularly those using natural language processing (NLP) like ChatGPT, has opened new possibilities for automating various stages of the development lifecycle. The primary objective of this study is to evaluate the effectiveness of ChatGPT in automating various phases of software development. An artificial intelligence (AI) tool was developed using the OpenAI—Application Programming Interface (API), incorporating two key functionalities: 1) generating user stories based on case or process inputs, and 2) estimating the effort required to execute each user story. Additionally, ChatGPT was employed to generate application code. The AI tool was tested in three case studies, each explored under two different development strategies: a semi-automated process utilizing the AI tools and a traditional manual approach. The results demonstrated a significant reduction in total development time, ranging from 40% to 51%. However, it was observed that the generated content could be inaccurate and incomplete, necessitating review and debugging before being applied to projects. In conclusion, given the increasing shift towards automation in software engineering, further research is critical to enhance the efficiency and reliability of AI tools, particularly those that leverage natural language processing (NLP) technologies. [ABSTRACT FROM AUTHOR]

Debugging is essential for identifying and rectifying errors in programming, yet time constraints and students' trivialization of errors often hinder progress. This study examines differences in debugging challenges and strategies among students with varying computational thinking (CT) competencies using weekly coding journals from an online undergraduate CT course. Participants used Scratch, a block-based programming language, and their journals from five assignments were analyzed using Term Frequency-Inverse Document Frequency and Structural Topic Modeling. High-performing students engaged with diverse topics and specific blocks tied to their weekly projects while low-performing students faced repetitive and broad challenges, such as understanding motion blocks and broadcast concepts. These patterns reveal that low-performing students struggle particularly during the 'diagnose the fault' phase of debugging, often hindering their progress in the final stage. Such challenges highlight the necessity for targeted educational interventions to improve the debugging proficiency and overall CT skills. The study underscores the importance of further research into students' logical thinking processes during code review and debugging, suggesting the use of think-aloud protocols and detailed tracking of debugging practices for deeper insights. This research contributes to the field by showing that differentiated instruction and strategic support can enhance debugging skills across different student performance levels. [ABSTRACT FROM AUTHOR]

Copyright of Biology Teaching is the property of East China Normal University and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Background: Large Language Models (LLMs) are emerging as promising tools in hardware design and verification, with recent advancements suggesting they could fundamentally reshape conventional practices. Objective: This study examines the significance of LLMs in shaping the future of hardware design and verification. It offers an extensive literature review, addresses key challenges, and highlights open research questions in this field. Design: in this scoping review, we survey over 360 papers most of the published between 2022 and 2024, including 71 directly relevant ones to the topic, to evaluate the current role of LLMs in advancing automation, optimization, and innovation in hardware design and verification workflows. Results: Our review highlights LLM applications across synthesis, simulation, and formal verification, emphasizing their potential to streamline development processes while upholding high standards of accuracy and performance. We identify critical challenges, such as scalability, model interpretability, and the alignment of LLMs with domain-specific languages and methodologies. Furthermore, we discuss open issues, including the necessity for tailored model fine-tuning, integration with existing Electronic Design Automation (EDA) tools, and effective handling of complex data structures typical of hardware projects. Conclusions: this survey not only consolidates existing knowledge but also outlines prospective research directions, underscoring the transformative role LLMs could play in the future of hardware design and verification. [ABSTRACT FROM AUTHOR]

Programming education is becoming increasingly popular in universities. However, due to a lack of debugging experience, novices often encounter numerous difficulties in the programming process. Automatic fault localization techniques have emerged as a promising solution to address this issue. Among these techniques, Spectrum-Based Fault Localization (SBFL) and Mutation-Based Fault Localization (MBFL) have been widely used in industrial programs. However, there is a significant difference between industrial and novice programs and the performance of these methods on novice programs has not been extensively studied. To fill this gap, we conducted an empirical study to evaluate the fault localization performance and execution overhead of SBFL and MBFL in a typical novice programming environment. Our study specifically examined how different program characteristics, including code coverage and mutation score, affect the accuracy of these localization methods. Additionally, during the study, we identified the tie problem in both methods and further investigated its impact on fault localization techniques in novice programs. To remove the impact of the tie problem, we proposed using PageRank scores as weights for the suspiciousness, sorting, and locating faults based on the weighted suspiciousness. The PageRank algorithm is based on statement coverage information and constructs a directed graph. From the directed graph, a transition matrix generates the weight scores (PageRank scores) for each statement. Our research demonstrates that both SBFL and MBFL are effective for fault localization in novice programs, with MBFL showing significantly better performance in our tests. In TOP- N (N = 1 , 3 , 5) , MBFL accurately locates 67, 96 and 114 faults, respectively, indicating superior performance. Additionally, calculating weighted suspiciousness significantly alleviates the tie problem. [ABSTRACT FROM AUTHOR]

As academic libraries continue to invest in electronic resources, batch processing of vendor-supplied MARC records has become a major aspect of cataloging procedures. As the scale of records increases, methods for efficient editing and loading become more important. This article uses the development of a workflow for handling records from EBSCO's HLM service as a study for finding a balance between timeliness and discoverability when processing and troubleshooting large numbers of vendor-supplied records with a focus on scalability, automation, and coordination. [ABSTRACT FROM AUTHOR]

In recent years, significant progress has been made in testing methods for deep neural networks (DNNs) to ensure their correctness and robustness. Coverage-guided criteria, such as neuron-wise, layer-wise, and path-/trace-wise, have been proposed for DNN fuzzing. However, existing coverage-based criteria encounter performance bottlenecks for several reasons: ❶ Testing Adequacy: Partial neural coverage criteria have been observed to achieve full coverage using only a small number of test inputs. In this case, increasing the number of test inputs does not consistently improve the quality of models. ❷ Interpretability: The current coverage criteria lack interpretability. Consequently, testers are unable to identify and understand which incorrect attributes or patterns of the model are triggered by the test inputs. This lack of interpretability hampers the subsequent debugging and fixing process. Therefore, there is an urgent need for a novel fuzzing criterion that offers improved testing adequacy, better interpretability, and more effective failure detection capabilities for DNNs. To alleviate these limitations, we propose NSGen, an approach for DNN fuzzing that utilizes neuron semantics as guidance during test generation. NSGen identifies critical neurons, translates their high-level semantic features into natural language descriptions, and then assembles them into human-readable DNN decision paths (representing the internal decision of the DNN). With these decision paths, we can generate more fault-revealing test inputs by quantifying the similarity between original test inputs and mutated test inputs for fuzzing. We evaluate NSGen on popular DNN models (VGG16_BN, ResNet50, and MobileNet_v2) using CIFAR10, CIFAR100, Oxford 102 Flower, and ImageNet datasets. Compared to 12 existing coverage-guided fuzzing criteria, NSGen outperforms all baselines, increasing the number of triggered faults by 21.4% to 61.2% compared to the state-of-the-art coverage-guided fuzzing criterion. This demonstrates NSGen's effectiveness in generating fault-revealing test inputs through guided input mutation, highlighting its potential to enhance DNN testing and interpretability. [ABSTRACT FROM AUTHOR]

Featured Application: The method proposed in this work can be applied to various scenarios, such as model debugging and medical image diagnosis, to interpret the behavior of convolutional neural network models, enhance trust in the models, and support better decision making. The interpretability of neural networks has garnered significant attention. In the domain of computer vision, gradient-based feature attribution techniques like RectGrad have been proposed to utilize saliency maps to demonstrate feature contributions to predictions. Despite advancements, RectGrad falls short in category discrimination, producing similar saliency maps across categories. This paper pinpoints the ineffectiveness of threshold-based strategies in RectGrad for distinguishing feature gradients and introduces Class activation map Guided BackPropagation (CGBP) to tackle the issue. CGBP leverages class activation maps during backpropagation to enhance gradient selection, achieving consistent improvements across four models (VGG16, VGG19, ResNet50, and ResNet101) on ImageNet's validation set. Notably, on VGG16, CGBP improves SIC, AIC, and IS scores by 10.3%, 11.5%, and 4.5%, respectively, compared to RectGrad while maintaining competitive DS performance. Moreover, CGBP demonstrates greater sensitivity to model parameter changes than RectGrad, as confirmed by a sanity check. The proposed method has broad applicability in scenarios like model debugging, where it identifies causes of misclassification, and medical image diagnosis, where it enhances user trust by aligning visual explanations with clinical insights. [ABSTRACT FROM AUTHOR]

Fault localization (FL) aims to automatically find the location of bugs in a software program. In the family of FL approaches, spectrum‐based fault localization (SBFL) is the most widely used and has been extensively studied, which computes the suspicious scores of a code element to be buggy via test coverage information. Mutation‐based fault localization (MBFL) further analyses the relationship between mutants and test results. Although MBFL involves more information, it also faces the following limitations. (1) To precisely evaluate suspicious sources, SBFL approaches proposed dozens of formulae based on coverage, while only a few of them have been adopted by MBFL. (2) The current MBFL approaches are based on the assumption that the capability in localizing bugs of each mutant is the same, so they assign the same weight to the mutants that change the test outputs and consider the mutant from the same code element equivalent. In this paper, we intend to enrich the MBFL family by the following two approaches. First, we collect 25 typical SBFL formulae and transform them into MBFL versions. Second, we propose new assumptions that the mutants should have different weights in computing suspicious sources and propose BLMu, a novel MBFL approach that treats mutants differently. We also propose novel metrics for MBFL by considering the high cost of mutation analysis. We perform large‐scale experiments by evaluating all the MBFL approaches against 395 real‐world Java bugs of the Defects4J benchmark. Our evaluation results reveal that BLMu demonstrates a substantial improvement over both MUSE and Metallaxis, the most popular MBFL approaches, at both the statement level and the method level. Specifically, in terms of Top‐1, BLMu improves by 106% at the statement level and 69% at the method level. When compared with other types of FL approaches, MBFL outperforms typical SBFL approaches while still far behind the state‐of‐the‐art learning‐based FL approaches. [ABSTRACT FROM AUTHOR]

ABSTRACT Software reliability is a critical metric for determining the readiness and quality of software products before release. In this study, a software reliability growth model (SRGM) is proposed that integrates imperfect debugging and fault removal efficiency to better reflect real‐world testing environments. The model accounts for the possibility of introducing new faults during debugging and adjusts the fault removal process based on the testing team's efficiency and learning progression of the testing team. Furthermore, an optimal software release time is derived by considering various costs, including testing, debugging, warranty, and reputation, with the required reliability levels. The proposed model is validated using two widely adopted datasets, demonstrating consistently superior performance compared to several existing models. This model offers a valuable tool for researchers in software reliability, providing a more accurate representation of debugging processes, and facilitating more informed decisions regarding optimal software release timing. [ABSTRACT FROM AUTHOR]

End-cloud collaborative computing framework ensures the security and privacy of edge device data, enabling collaborative training of global models without direct data exchange. However, in practical scenarios, anomalies in training or edge device data may severely degrade or disable the global model’s performance. Existing frameworks lack effective debugging and anomaly localization, hindering real-time monitoring and precise identification of abnormal edge devices in data heterogeneity scenarios. In this paper, we propose a new method named FedCheck, a debugging framework for end-cloud collaborative federated learning that enables real-time alerts and detects abnormal devices for nonindependent and identically distributed (nonIID) data without disrupting the regular training process. Specifically, we employ a model similarity-based method to quantitatively assess the degree of device anomaly in data heterogeneity scenarios, supporting real-time alerts during the end-cloud collaboration process. Furthermore, a simulation program replays the training process based on recorded telemetry data, facilitating backtracking debugging of any training round and the status of edge devices. Finally, the framework removes abnormal devices and repairs the global model. Experiments on MNIST and Fashion-MNIST datasets demonstrate that FedCheck can effectively detect and locate abnormal devices in data heterogeneity scenarios. Even in large-scale federated learning, it maintains high detection performance and exhibits good scalability. [ABSTRACT FROM AUTHOR]

Static analysis tools play a crucial role in software development by detecting bugs and vulnerabilities. However, running these tools separately from the code editing process often causes developers to switch contexts, which can reduce productivity. Previous work has shown how Reference Attribute Grammars (RAGs) can be used for declarative implementation of competitive tooling for intraprocedural control-flow and dataflow analysis of Java source code, embodied in the tool IntraJ. In this paper, we demonstrate how IntraJ can be leveraged to provide interactive analysis results directly in the editor, similar to compile-time error detection, relying on automatic on-demand evaluation of RAGs. We discuss the architecture of IntraJ, and demonstrate how it can be integrated into the development process in three different ways: in the command line, in an editor integration based on the Language Server Protocol, and in an integration with the debugging tool CodeProber. We showcase the extensibility of IntraJ by illustrating how new client analyzes and language constructs can be added to the framework through RAG specifications. Finally, we evaluate the interactive performance of IntraJ on a set of real-world Java benchmarks, demonstrating that IntraJ can provide interactive feedback to developers, achieving a response time of under 0.1 seconds for most compilation units. [ABSTRACT FROM AUTHOR]

Remote attestation (RA) is an essential feature in many security protocols to verify the memory integrity of remote embedded devices susceptible to malware infections. The attestation process needs to be consecutive and atomic to prevent a self-relocating malware from evading detection. Most of the prior attestation techniques disable interrupts during execution to prevent another process from interrupting the integrity check. This paper investigates the shortcomings of existing software-based attestation techniques and stresses the threat of debug exceptions to existing software-based attestation. We present Debug Register-based Self-relocating Attack (DRSA), a novel self-relocating malware against software-based attestation based on debug registers. DRSA gains control of the checksum function by raising debug exceptions and erasing itself before the next attestation. We further implement DRSA on commodity OSes and validate its effectiveness based on two existing software-based proposals. Our evaluation demonstrates that DRSA incurs low overhead, and it is extremely difficult for the verifier to detect it. can bypass the attestation with very little attack overhead. [ABSTRACT FROM AUTHOR]

Data races represent a class of concurrency errors when two threads access a shared memory location without proper synchronization. Data races are hard to reveal and debug. This paper presents RaceHunter, a dynamic data race detection technique, which monitors executions of shared-memory concurrent programs, discovers pairs of conflicting memory accesses, and systematically checks them for data races. RaceHunter does not report false data races when the target software exploits nonstandard synchronization primitives or unknown synchronization protocols, and it can also detect data races missed by other approaches. Dynamic data race detectors can monitor continuous, e.g., real-life, program executions or they can verify relatively short program executions, e.g., organized by system tests. The latter is the primary use case scenario for RaceHunter. [ABSTRACT FROM AUTHOR]

As the scope of artificial intelligence (AI) expands and the structure becomes more complex, the amount of data for inference and training has increased. In traditional computer architectures, the memory bandwidth limitations have intensified bottlenecks in AI systems, and processing-in-memory (PIM) architectures have been proposed to overcome this issue. PIM is an architecture that performs computations within memory, thereby reducing data movement between the CPU and memory. However, since PIM is difficult to optimize as a general-purpose architecture, it is essential to adopt an architecture suitable for the target application. While various simulators and emulators have been introduced for the design space exploration (DSE) of different PIM architectures, simulators are limited in debugging hardware operations, and emulators face challenges in flexibly modifying the system configuration, as emulators implement the entire architecture in hardware. Therefore, this paper introduces PIMCoSim, a comprehensive hardware–software co-simulator for the DSE of DRAM-PIM systems. This co-simulator partially emulates simplified hardware-implemented processing elements (PEs) and integrates software models for memory operations, facilitating the DSE of PIM systems. To validate PIMCoSim, we analyzed results for different computational workloads by varying PIM structures and operational policies, demonstrating the efficiency of DRAM-PIM systems. The co-simulation approach in PIMCoSim aims to contribute to analyzing DRAM-PIM configurations and adopting optimized structures. [ABSTRACT FROM AUTHOR]

Copyright of Bearing is the property of Bearing Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper proposes a method to control the sensitivity of a ring MEMS gyroscope by adjusting the driving control voltage via MEMS. The aim is to explore the relationship between the range of the ring MEMS gyroscope and the driving control voltage, establishing a mathematical model that correlates driving control voltage with sensitivity. By applying different driving voltages to the same gyroscope, the study evaluates the performance and range of the gyroscope. Experimental results demonstrate that lower driving voltages increase the gyroscope's range. At a driving voltage of 10.85 V, the gyroscope achieves a range of ±200°/s, a minimum resolution of 0.019°/s, and a nonlinearity of 22.37 ppm. At 1.46 V, the gyroscope range expands to ±1000°/s, with a minimum resolution of 0.05138°/s and a nonlinearity of 60.73 ppm. As the measurement range increased fivefold, the degradation in gyroscope performance was significantly less than the scale of range expansion. Compared to the gain in modulation detection circuitry, gyroscope performance was optimized across the entire operational range. [ABSTRACT FROM AUTHOR]

The document discusses the advancements in cloud computing and High-Performance Computing (HPC) that are shaping the landscape of Information and Communication Technology (ICT). It highlights breakthrough research on topics such as AI-driven optimization, dynamic orchestration of distributed systems, pricing strategies for cloud services, and performance enhancements for emerging workloads. The collection of articles addresses critical challenges in cloud computing, machine learning applications in cloud services, reliability, cost-efficiency, and performance debugging in microservice architectures, among other topics. The studies aim to inspire researchers, industry professionals, and decision-makers in the rapidly evolving field of cloud computing and related technologies. [Extracted from the article]

The study aims to investigate prospective middle school mathematics teachers’ mental actions related to debugging, which is one of the computational thinking skills in the modeling process. The study was conducted with a single-case embedded model. The collaborative working group consisted of three prospective mathematics teachers selected by criterion sampling. The data were collected from the video analysis, screen excerpts, and GeoGebra files explaining the solution process of three prospective mathematics teachers for the designed two mathematical modeling problems (experimental and theoretical). According to the results obtained from the data through content analysis based on the theoretical framework, it was identified that the prospective teachers conducted sub-activities such as recognizing/detecting the error, extracting the error, and correcting the error, which is one of the dimensions of computational thinking in technology-supported mathematical modeling. These skills as the basic steps of interpretation, verification, and revision were developed in the process of technologysupported mathematical modeling. GeoGebra was involved as an important mental trigger in the debugging process. In further studies, computational thinking studies describing all the components in the process of technology-supported mathematical modeling can be conducted, and computational thinking skills can be revealed in the process of mathematical modeling in non-computerized environments. [ABSTRACT FROM AUTHOR]

The article provides practical insights into the development of a specialized machine for automating the assembly of components based on customer-specified parameters. The initial design undergoes a risk analysis in accordance with the EN ISO 13849 standard, ensuring safety compliance. For the software aspect, we create sequences and algorithms for the machine's individual components using standardized formats within the TIA Portal software. To expedite programming and real-time debugging, a virtual commissioning approach utilising the fe.screen-sim program is employed. This allows us to address any issues or deficiencies in the virtual model, which mirrors the actual machine, optimizing the time needed for final physical adjustments. [ABSTRACT FROM AUTHOR]

Exascale supercomputers are first-of-their-kind instruments with potentially paradigm-shifting capabilities. However, enabling complex applications at scale and high performance can be difficult, requiring hard work and deep technical understanding. Specific programming models are often needed to achieve the desired performance, and, early on, systems are undergoing debugging and rapid development. This makes it challenging to run on new systems quickly following their deployment. The Application Integration (AppInt) area of the Exascale Computing Project was designed to be the integration point between applications, supporting software, system environments, high-performance computing facilities, and vendors. We describe how the AppInt team addressed these challenges while also promoting the use of portable and sustainable programming models and helping harden systems prior to general availability.

Spectrum-based fault localization (SBFL) is one of the most popular fault localization techniques that uses coverage information and test results to calculate a suspicious score for every program statement. The effectiveness of SBFL suffers from the occurrences of coincidental correctness, which occurs when a fault is executed but no failure is detected. Identifying coincidental correct (CC) test cases can be modeled as a classification problem. Except in exceptional cases, proven identification of CC tests is not possible, so instead of using 0/1 results, we propose a similarity-based approach to identify CC test cases. A strategy is suggested to manipulate CC test cases for SBFL. In the first step, a low-cost computational method is proposed to identify CC test cases based on the similarity of the passed executions to the failed ones. Then, we proposed new similarity measures based on the original ones (such as Jaccard similarity and Euclidean distance) and presented a method to identify proven CC. Finally, a weighted CC test case manipulation strategy is proposed to mitigate the negative impact of CC test cases in SBFL. We evaluated the proposed method by conducting extensive experiments on 443 faulty versions of 13 popular subject programs, containing artificial and real faults. The results show that the proposed method can improve the accuracy of SBFL techniques with a very low computational cost. [ABSTRACT FROM AUTHOR]

Failure indexing is a longstanding crux in software debugging, the goal of which is to automatically divide failures (e.g., failed test cases) into distinct groups according to the culprit root causes, as such multiple faults residing in a faulty program can be handled independently and simultaneously. The community of failure indexing has long been plagued by two challenges: (1) The effectiveness of division is still far from promising. Specifically, existing failure indexing techniques only employ a limited source of software runtime data, for example, code coverage, to be failure proximity and further divide them, which typically delivers unsatisfactory results. (2) The outcome can be hardly comprehensible. Specifically, a developer who receives the division result is just aware of how all failures are divided, without knowing why they should be divided the way they are. This leads to difficulties for developers to be convinced by the division result, which in turn affects the adoption of the results. To tackle these two problems, in this article, we propose SURE, a viSUalized failuRe indExing approach using the program memory spectrum (PMS). We first collect the runtime memory information (i.e., variables' names and values, as well as the depth of the stack frame) at several preset breakpoints during the execution of a failed test case, and transform the gathered memory information into a human-friendly image (called PMS). Then, any pair of PMS images that serve as proxies for two failures is fed to a trained Siamese convolutional neural network, to predict the likelihood of them being triggered by the same fault. Last, a clustering algorithm is adopted to divide all failures based on the mentioned likelihood. In the experiments, we use 30% of the simulated faults to train the neural network, and use 70% of the simulated faults as well as real-world faults to test. Results demonstrate the effectiveness of SURE: It achieves 101.20% and 41.38% improvements in faults number estimation, as well as 105.20% and 35.53% improvements in clustering, compared with the state-of-the-art technique in this field, in simulated and real-world environments, respectively. Moreover, we carry out a human study to quantitatively evaluate the comprehensibility of PMS, revealing that this novel type of representation can help developers better comprehend failure indexing results. [ABSTRACT FROM AUTHOR]

Writing declarative models has numerous benefits, ranging from automated reasoning and correction of design-level properties before systems are built, to automated testing and debugging of their implementations after they are built. Alloy is a declarative modeling language that is well-suited for verifying system designs. A key strength of Alloy is its scenario-finding toolset, the Analyzer, which allows users to explore all valid scenarios that adhere to the model’s constraints up to a user-provided scope. Despite the Analyzer, writing correct Alloy models remains a difficult task, partly due to Alloy’s expressive operators, which allow for succinct formulations of complex properties but can be difficult to reason over manually. To further add to the complexity, Alloy’s grammar was recently expanded to support linear temporal logic, increasing both the expressibility of Alloy and the burden for accurately expressing properties. To address this, this paper presents μ\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$$\mu $$\end{document}Alloyτ\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$$\tau $$\end{document}, an extension to Alloy’s mutation testing framework that accounts for the newly introduced temporal logic, including updating μ\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$$\mu $$\end{document}Alloyτ\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$$\tau $$\end{document}’s test generation capability to produce temporal test cases. Experimental results reveal μ\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$$\mu $$\end{document}Alloyτ\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$$\tau $$\end{document} is efficient at generating and checking mutations and μ\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$$\mu $$\end{document}Alloyτ\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$$\tau $$\end{document}’s automatically generated tests are effective at detecting faulty temporal models. [ABSTRACT FROM AUTHOR]

Background: Shapley values have been used extensively in machine learning, not only to explain black box machine learning models, but among other tasks, also to conduct model debugging, sensitivity and fairness analyses and to select important features for robust modelling and for further follow-up analyses. Shapley values satisfy certain axioms that promote fairness in distributing contributions of features toward prediction or reducing error, after accounting for non-linear relationships and interactions when complex machine learning models are employed. Recently, feature selection methods using predictive Shapley values and p-values have been introduced, including powershap. Methods: We present a novel feature selection method, LLpowershap, that takes forward these recent advances by employing loss-based Shapley values to identify informative features with minimal noise among the selected sets of features. We also enhance the calculation of p-values and power to identify informative features and to estimate number of iterations of model development and testing. Results: Our simulation results show that LLpowershap not only identifies higher number of informative features but outputs fewer noise features compared to other state-of-the-art feature selection methods. Benchmarking results on four real-world datasets demonstrate higher or comparable predictive performance of LLpowershap compared to other Shapley based wrapper methods, or filter methods. LLpowershap is also ranked the best in mean ranking among the seven feature selection methods tested on the benchmark datasets. Conclusion: Our results demonstrate that LLpowershap is a viable wrapper feature selection method that can be used for feature selection in large biomedical datasets and other settings. [ABSTRACT FROM AUTHOR]

Multimodal data enables us to capture the cognitive and affective states of students to provide a holistic understanding of learning processes in a wide variety of contexts. With the use of sensing technology, we can capture learners' states in near real-time and support learning. Moreover, multimodal data allows us to obtain early predictions of learning performance, and support learning in a timely manner. In this contribution, we utilise the notion of ‘carry forward effect’, an inferential and predictive modelling approach that utilises multimodal data measurements detrimental to learning performance to provide timely feedback suggestions. Carry forward effect can provide a way to prioritise conflicting feedback suggestions in a multimodal data-based scaffolding tool. We showcase the empirical proof of the carry forward effect with the use of three different learning scenarios: game-based learning, individual debugging, and collaborative debugging. [ABSTRACT FROM AUTHOR]

The minimizing Delta Debugging (DDMIN) was among the first algorithms designed to automate the task of reducing test cases. Its popularity is based on the characteristics that it works on any kind of input, without knowledge about the input structure. Several studies proved that smaller outputs can be produced faster with more advanced techniques (e.g., building a tree representation of the input and reducing that data structure); however, if the structure is unknown or changing frequently, maintaining the descriptors might not be resource‐efficient. Therefore, in this paper, we focus on the evaluation of the novel fixed‐point iteration of minimizing Delta Debugging (DDMIN*) on publicly available test suites related to software engineering. Our experiments show that DDMIN* can help reduce inputs further by 48.08% on average compared to DDMIN (using lines as the units of the reduction). Although the effectiveness of the algorithm improved, it comes with the cost of additional testing steps. This study shows how the characteristics of the input affect the results and when it pays off using DDMIN*. [ABSTRACT FROM AUTHOR]

The robotic arm is a complicated system with multiple inputs and outputs, strong coupling, containing uncertainties and nonlinearities. This study proposes a new practical robust control method based on the dynamics model and tracking error, including a model- and error-based proportional-differential feedback term and an error-based robust term. Specifically, the dynamics of the system are modeled using the Lagrangian method. Uncertainties are presumed to be time-varying but limited. Based on the Lyapunov method, the proposed controller has theoretically demonstrated the controlled system with uniform boundedness (UB) and uniform ultimate boundedness (UUB). Furthermore, the radius of the ultimately bounded hypersphere is arbitrarily small based on selecting appropriate design parameters. Based on the two-degree-of-freedom (2-DOF) planar robotic arm experimental platform, the self-developed rapid controller prototype CSPACE-RT is intended to eliminate tedious programming or debugging, significantly simplifying the experimental process. Finally, numerical simulation and experiment results verified the excellent control performance of the suggested controller. [ABSTRACT FROM AUTHOR]