128 results on '"Debusschere, I."'
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2. Optimization of gate stack parameters towards 3D-SONOS application
3. Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V Vt Ni-FUSI CMOS transistors
4. Ionizing radiation hardening of a CCD technology
5. A 1006 element hybrid silicon pixel detector with strobed binary output
6. A Foveated Retina-Like Sensor Using CCD Technology
7. O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory
8. A low-cost 90 nm RF-CMOS platform for record RF circuit performance
9. Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology
10. Standard cell level parasitics assessment in 20nm BPL and 14nm BFF
11. Impact of through silicon via induced mechanical stress on fully depleted Bulk FinFET technology
12. Ultra thin hybrid floating gate and high-k dielectric as IGD enabler of highly scaled planar NAND flash technology
13. Understanding of Trap-Assisted Tunneling Current - Assisted by Oxygen Vacancies in RuOx/SrTiO3/TiN MIM Capacitor for the DRAM Application
14. Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology
15. Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory
16. (Invited) Plasma Enhanced Atomic Layer Deposited Ruthenium for MIMCAP Applications
17. Process Development of ALD-Rutile-TiO2/Ru(Ox) for DRAM MIMcap Application and its Leakage Mechanism Analysis
18. Impact of bottom electrode and SrxTiyOz film formation on physical and electrical properties of metal-insulator-metal capacitors
19. Advanced Capacitor Dielectrics: Towards 2x nm DRAM
20. Novel Bi-Layer Poly-Silicon Channel Vertical Flash Cell for Ultrahigh Density 3D SONOS NAND Technology
21. High Performance THANVaS Memories for MLC Charge Trap NAND Flash
22. A PEALD Tunnel Dielectric for Three-Dimensional Non-Volatile Charge-Trapping Technology
23. DEVELOPMENT OF SILICON MICROPATTERN PIXEL DETECTORS
24. RD19: status report on 1993 development of hybrid and monolithic silicon micropattern detectors
25. Impact of crystallization behavior of SrxTiyOz films on electrical properties of metal-insulator-metal capacitors with TiN electrodes
26. Investigation of rare-earth aluminates as alternative trapping materials in Flash memories
27. Optimization of the crystallization phase of Rare-Earth aluminates For blocking dielectric application in TANOS type flash memories
28. Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance
29. Temperature dependent electrical characteristics of through-si-via (TSV) interconnections
30. RD19: status report and addendum. Development of hybrid and monolithic silicon micropattern detectors
31. 3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding
32. O2 post deposition anneal of Al2O3 blocking dielectric for higher performance and reliability of TANOS Flash memory
33. 3D stacked IC demonstration using a through Silicon Via First approach
34. RADIATION SENSITIVE SENSOR HAVING A PLURALITY OF RADIATION SENSITIVE ELEMENTS ARRANGED SUBSTANTIALLY CIRCULAR WITH RADIALLY DECREASING DENSITY
35. Optimization of HfSiON using a design of experiment (DOE) approach on 0.45V Vt Ni-FUSI CMOS transistors
36. FUSI Specific Yield Monitoring Enabling Improved Circuit Performance and Fast Feedback to Production
37. Development of hybrid and monolithic silicon micropattern detectors: status report RD19
38. Methodology for characterizing the impact of circuit layout, technology options, device engineering and temperature on the circuit power-delay characteristics
39. RADIATION-SENSITIVE MEAN OR SENSOR IN RETINA-LIKE CONFIGURATION
40. R&D proposal: development of hybrid and monolithic silicon micropattern detectors
41. An Ultra-Thin Hybrid Floating Gate Concept for Sub-20nm NAND Flash Technologies.
42. Exploration of rare earth materials for future interpoly dielectric replacement in Flash memory devices.
43. 90nm RF CMOS technology for low-power 900MHz applications [amplifier example].
44. Thin L-shaped spacers for CMOS devices.
45. Optimisation of a Pre-Metal-Dielectric with a contact etch stop layer for 0.18um and 0.13um technologies.
46. Importance of determining the polysilicon dopant profile during process development
47. Integration of CMOS-electronics and particle detector diodes in high-resistivity silicon-on-insulator wafers
48. Characterization of the ionizing radiation sensitivity of a CCD technology
49. Development of silicon micropattern (pixel) detectors
50. Characterization of the Ionizing Radiation Sensitivity of a CCD Technology.
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