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For the development of reliable vertical GaN transistors, a detailed analysis of the robustness of the gate stack is necessary, as a function of the process parameters and material properties. To this aim, we report a detailed analysis of breakdown performance of planar GaN-on-Si MOS capacitors. The analysis is carried out on capacitors processed on different GaN bulk doping (6E18 Si/cc, 6E17 Si/cc and 2.5E18 Mg/cc, p-type), different structures (planar, trench-like) and different geometries (area, perimeter and shape). We demonstrate that (i) capacitors on p-GaN have better breakdown performance; (ii) the presence of a trench structure significantly reduces breakdown capabilities; (iii) breakdown voltage is dependent on area, with a decreasing robustness for increasing dimensions; (iv) breakdown voltage is independent of shape (rectangular, circular). TCAD simulations, in agreement with the measurements, illustrate the electric field distribution near breakdown and clarify the results obtained experimentally., Comment: ["European Union (EU)" & "Horizon 2020"]["Euratom" & Euratom research & training programme 2014-2018"][Research for GaN technologies, devices, packages and applications to address the challenges of the future GaN roadmap][UltimateGaN][826392]

Developing high quality GaN/dielectric interfaces is a fundamental step for manufacturing GaN vertical power transistors. In this paper, we quantitatively investigate the effect of planar etching treatment and trench formation on the performance of GaN-based MOS (metal oxide semiconductor) stacks. The results demonstrate that (i) blanket etching the GaN surface does not degrade the robustness of the deposited dielectric layer; (ii) the addition of the trench etch, while improving reproducibility, results in a decrease of breakdown performance compared to the planar structures. (iii) for the trench structures, the voltage for a 10 years lifetime is still above 20 V, indicating a good robustness. (iv) To review the trapping performance across the metal-dielectric-GaN stack, forward-reverse capacitance-voltage measurements with and without stress and photo-assistance are performed. Overall, as-grown planar capacitors devoid of prior etching steps show lowest trapping, while trench capacitors have higher interface trapping, and bulk trapping comparable to the blanket etched capacitors. (v) The nanostructure of the GaN/dielectric interface was characterized by high resolution scanning transmission electron microscopy (HR-STEM). An increased roughness of 2-3 monolayers at the GaN surface was observed after blanket etching, which was correlated to the higher density of interface traps. The results presented in this paper give fundamental insight on how the etch and trench processing affects the trapping and robustness of trench-gate GaN-MOSFETs, and provide guidance for the optimization of device performance., Comment: ["European Union (EU)" & "Horizon 2020"]["Euratom" & Euratom research & training programme 2014-2018"][ECSEL Joint Undertaking (JU)][Grant Agreement No. 826392][UltimateGaN]

The aim of this work is to present the optimization of the gate trench module for use in vertical GaN devices in terms of cleaning process of the etched surface of the gate trench, thickness of gate dielectric and magnesium concentration of the p-GaN layer. The analysis was carried out by comparing the main DC parameters of devices that differ in surface cleaning process of the gate trench, gate dielectric thickness, and body layer doping. . On the basis of experimental results, we report that: (i) a good cleaning process of the etched GaN surface of the gate trench is a key factor to enhance the device performance, (ii) a gate dielectric >35-nm SiO2 results in a narrow distribution for DC characteristics, (iii) lowering the p-doping in the body layer improves the ON-resistance (RON). Gate capacitance measurements are performed to further confirm the results. Hypotheses on dielectric trapping/detrapping mechanisms under positive and negative gate bias are reported., Comment: 5 pages, 10 figures, submitted to Microelectronics Reliability (Special Issue: 31st European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF 2020)