219 results on '"Demarest J"'
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2. Manufacturing Yield Improvement for Advanced CMOS Technology Middle-of-Line Interconnect with Cobalt Metallization : YE: YieldEnhancement/Learning
3. Process Challenge in Analog Computing Hardware using Phase Change Memory (PCM)
4. Nanoscale characterization of stresses in semiconductor devices
5. Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology
6. Synergistic combinations of dielectrics and metallization process technology to achieve 22 nm interconnect performance targets
7. Photoconductive Semiconductor Switches for High Power Radiation
8. Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
9. Fully On-Chip MAC at 14 nm Enabled by Accurate Row-Wise Programming of PCM-Based Weights and Parallel Vector-Transport in Duration-Format
10. Failure Analysis Challenges of Phase Change Memory Test Structures with Two Case Studies
11. Low Angle Annular Dark Field Scanning Transmission Electron Microscopy Analysis of Phase Change Material
12. Selective deposition of AlOx for Fully Aligned Via in nano Cu interconnects
13. Impact of Nanosecond Laser Anneal on PVD Ru Films
14. Perspectives on the Barrier to Resistance for Dolutegravir + Lamivudine, a Two-Drug Antiretroviral Therapy for HIV-1 Infection
15. A 14 nm Embedded STT-MRAM CMOS Technology
16. Elemental TEM Tomography of Phase Change Memory Artificial Intelligence Hardware Case Study
17. Middle of Line (MOL) Process Investigation in Ring Oscillator failure
18. Selective Enablement of Dual Dipoles for near Bandedge Multi-Vt Solution in High Performance FinFET and Nanosheet Technologies
19. Interactions of Metal-Organic PEALD TaN with Ultra-Low k Dielectric Materials
20. Transmission Electron Microscopy Sample Preparation By Design Based Recipe Writing in a DBFIB Part 2
21. Technology challenges and enablers to extend Cu metallization to beyond 7 nm node
22. An evaluation of Fuchs-Sondheimer and Mayadas-Shatzkes models below 14nm node wide lines
23. Parasitic Resistance Reduction Strategies for Advanced CMOS FinFETs Beyond 7nm
24. Mechanisms of Electromigration Damage in Cu Interconnects
25. Annealing and Impurity Effects in Co Thin Films for MOL Contact and BEOL Metallization
26. Transmission Electron Microscopy Sample Preparation By Design-Based Recipe Writing in a DBFIB
27. Fully Aligned Via Integration for beyond 7 nm
28. Process Challenges in Fully Aligned Via Integration for sub 32 nm Pitch BEOL
29. Fully aligned via integration for extendibility of interconnects to beyond the 7 nm node
30. Quantitative Electron Energy Loss Spectroscopy (EELS) Analysis of Flowable CVD Oxide for Shallow Trench Isolation of finFET Integration
31. Comparison of key fine-line BEOL metallization schemes for beyond 7 nm node
32. Cobalt/copper composite interconnects for line resistance reduction in both fine and wide lines
33. Annealing and Impurity Effects in Co Thin Films for MOL Contact and BEOL Metallization.
34. A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels
35. FinFET performance with Si:P and Ge:Group-III-Metal metastable contact trench alloys
36. FINFET technology featuring high mobility SiGe channel for 10nm and beyond
37. VIH-24 - Analyse intégrée de l’émergence d’une résistance aux antirétroviraux sur 96 et 144 semaines issue des études cliniques chez des sujets naïfs de traitement contre le VIH-1 et recevant des traitements à base de dolutégravir
38. Place du diététicien dans l’amélioration des pratiques professionnelles en nutrition entérale
39. Ti and NiPt/Ti liner silicide contacts for advanced technologies
40. Interface preservation during Ge-rich source/drain contact formation
41. Population and ultra‐deep sequencing for tropism determination are correlated with Trofile ES: genotypic re‐analysis of the A4001078 maraviroc study
42. Short‐term variation of HIV tropism readouts in the absence of CCR5 antagonists
43. Bottom oxidation through STI (BOTS) — A novel approach to fabricate dielectric isolated FinFETs on bulk substrates
44. Electrodeposited Cu Film Morphology on Thin PVD Cu Seed Layers
45. ETSOI CMOS for System-on-Chip Applications Featuring 22nm Gate Length, Sub-100nm Gate Pitch, and 0.08mm2 RAM Cell
46. Electrodeposited Cu Film Morphology on Thin PVD Cu Seed Layers
47. UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below
48. Discovery Thinking - The Opening of the Deepwater Levant Basin in the Eastern Mediterranean (paper not available)
49. Synergistic combinations of dielectrics and metallization process technology to achieve 22nm interconnect performance targets
50. Electrolyte Additive Chemistry and Feature Size-Dependent Impurity Incorporation for Cu Interconnects
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