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A new polyphosphate K2Sr4(PO3)10is synthesized by a high-temperature solution method. This compound crystallizes in the triclinic space group of P1̅, consisting of the 1D infinite [PO3]∞chains and K and Sr ions between the chains. Compared with AM2(PO3)5(A = K, Rb, Cs; M = Ba, Pb), K2Sr4(PO3)10exhibits a more complex [PO3]∞chain structure and more diverse metal cationic coordination environment. More importantly, K2Sr4(PO3)10has both a deep-UV cutoff edge (<200 nm) and a significantly enlarged birefringence. First-principles calculations indicate that the birefringence of K2Sr4(PO3)10is 0.017 at 1064 nm, about 2 times that of RbBa2(PO3)5(0.008 at 1064 nm), which reaches a new height among the reported mixed alkali metal and alkaline earth metal phosphate. Theoretical calculations and structural analyses show that the enlarged birefringence of K2Sr4(PO3)10mainly originates from the [PO3]∞chains arranged in an inverted zigzag. This discovery introduces a new strategy for devising novel phosphate deep-UV optical crystals with a large birefringence.

Edge device deep neural network (DNN) training is practical to improve model adaptivity for unfamiliar datasets while avoiding privacy disclosure and huge communication cost. Nevertheless, apart from feed-forward (FF) as inference, DNN training still requires back-propagation (BP) and weight gradient (WG), introducing power-consuming floating-point computing requirements, hardware underutilization, and energy bottleneck from excessive memory access. This paper proposes a DNN training processor named PL-NPU to solve the above challenges with three innovations. First, a posit-based logarithm-domain processing element (PE) adapts to various training data requirements with a low bit-width format and reduces energy by transferring complicated arithmetics into simple logarithm domain operation. Second, a reconfigurable inter-intra-channel-reuse dataflow dynamically adjusts the PE mapping with a regrouping omega network to improve the operands reuse for higher hardware utilization. Third, a pointed-stake-shaped codec unit adaptively compresses small values to variable-length data format while compressing large values to fixed-length 8b posit format, reducing the memory access for breaking the training energy bottleneck. Simulated with 28nm CMOS technology, the proposed PL-NPU achieves a maximum frequency of 1040MHz with 343mW and 5.28mm $\mathbf {^{2}}$. The peak energy efficiency is 3.87TFLOPS/W for 0.6V at 60MHz. Compared with the state-of-the-art training processor, PL-NPU reaches $3.75\times $ higher energy efficiency and offers $1.68\times $ speedup when training ResNet18. [ABSTRACT FROM AUTHOR]