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A 600 V-rated insulated gate bipolar transistor (IGBT) with improved turn-on transient characteristics is proposed and investigated by simulation. The proposed IGBT features a built-in voltage-clamping structure. The floating ${p}$ -body adjacent to the trench gate is clamped at an appropriately high voltage before turn-on. This slows down the hole accumulation process in the floating p -body during turn-on transient, and thus the self-charging displacement current through the gate capacitance is reduced. The increasing rate for the gate voltage ( dV GE/ dt ) is then reduced. As a result, the proposed IGBT achieves a 25% decrease in collector current ( $I_C$ ) overshoot and 34% decrease in dI C/ dt , when compared with the conventional IGBT with the same turn-on loss ( E ON), at IC = 250 A/cm2 under hard-switching. Its fabrication process is compatible with conventional trench IGBT.

A novel Lateral Double-Diffused MOSFET (LDMOSFET) with ultra-low resistance is investigated by experiments. The proposed LDMOSFET features an extended gate field plate consisting of two back-to-back diodes. In the ON state, the electron accumulation layer is formed below the gate field plate and greatly reduces the resistance of the drift region. In the OFF state, the field plate assists in depleting the drift region and modulates the electric field distribution of the drift region, which ensures high breakdown voltage (BV). The key fabrication process steps for the proposed device are given. The fabricated prototype device shows specific on-resistance ( ${R} _{{\text {on},\text {sp}}}$ ) of 70 $\text{m}\Omega \cdot $ cm2 and BV of 680 V, which is superior performance for reported 600 V-rated lateral devices. The ${R} _{{\text {on},\text {sp}}}$ of the proposed LDMOSFET is decreased by 50% compared with the LDMOSFET without accumulation effect.

An accumulation-mode LDMOS with convex-shape field plate (CFP ALDMOS) is proposed and experimentally investigated. The proposed CFP ALDMOS features convex field plate structures on source and drain side, wherein the contact regions and two back-to-back diodes (D1 and D2) are formed. In the on-state, a continuous electron accumulation layer is formed in the N-drift surface to decrease the specific on-resistance (R on,sp ). In the off state to maintain the same breakdown voltage (BV) level, the CFP ALDMOS shrinks the drift length (L D ), so as to achieve a dramatical lower R on,sp . The proposed CFP ALDMOS experimentally realizes R on,sp of 22.2 mΩ•cm2 with BV of 489V. Its R on,sp is 48.4% and 51.1% lower than that of regular field plate (RFP) ALDMOS and triple-RESURF LDMOS under the same BV.

In this paper, we present a lateral injection enhanced insulated gate bipolar transistor (LIEGT) and investigate its mechanism. The LIEGT features a recessed trench at the cathode side of the drift region formed by LOCal oxidation of silicon (LOCOS) process. The recessed trench suppresses holes being extracted and enhances the electron injection, thus contributing to a very low loss in the ON-state. The ON-state voltage ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ) of the LIEGT is reduced by 24% at the current density of 200 A/cm2 and the saturation current is 40% higher than that of the conventional lateral insulated gate bipolar transistor (LIGBT). The LIEGT exhibits an improved tradeoff between ${V}_{ \mathrm{\scriptscriptstyle ON}}$ and turnoff loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ). For the same ${V}_{ \mathrm{\scriptscriptstyle ON}}$ , the ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ is decreased by 38% compared with that of the conventional LIGBT.

A novel ultrafast and low-loss lateral injection-enhanced gate transistor (LIEGT) is proposed and investigated by simulation. The device features a MOS-controlled shorted anode (MCSA) and a bias voltage ( ${V}_{{AG}}$ ) applied between the anode trench gate (ATG) and the anode electrode. The n+ anode is shorted to the N-buffer through the MOS channel around the ATG when the MCSA is activated with ${V}_{{AG}} > {V}_{{th}}$ during turn-off and blocking states, and thus the p+ anode/N-buffer junction is unactivated. The MCSA LIEGT turns off as fast as a unipolar device by optimizing the time gap to activate the MCSA before turning off the cathode trench gate (CTG). The activated MCSA would deactivate hole injection from the anode side and synchronously quickly extract the electrons from the N-drift, which improves the switching speed and dramatically decreases the turn-off energy loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ). In the blocking state, the MCSA LIEGT achieves a MOS breakdown mode instead of an open base p-n-p bipolar breakdown mode. Thus, the breakdown voltage (BV) is not only improved but also independent of the p+ anode doping concentration. In the forward conduction state with ${V}_{{AG}} = {0}$ , the MCSA is unactivated and hence the MCSA LIEGT operates like a conventional LIEGT without deteriorating the on-state voltage drop ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ). Compared with the conventional LIEGT, the proposed device decreases ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ by 88% and improves the BV by 13% at the same ${V}_{ \mathrm{\scriptscriptstyle ON}}$ . Importantly, ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ is almost independent of ${V}_{ \mathrm{\scriptscriptstyle ON}}$ .

A novel 4H-SiC superjunction trench metal oxide semiconductor field effect transistor (SJ-TMOS) is proposed in this paper. The device features a grounded P+ buried layer below the P-body, an oxide trench beneath the gate, and a P-region surrounding the oxide trench. The P-region, grounded P+ buried layer, and P-body serve as a three-level buffer (TLB) to lower the saturation current and thus improve the short-circuit ruggedness. Moreover, the P-region, P+ buried layer and N-drift form an SJ structure to decrease the specific on-resistance (Ron,sp) and increase the breakdown capability. Compared with conventional trench MOSFET (C-TMOS), the saturation current for SJ-TMOS is drastically lowered and thus the short-circuit time (tsc) extends by 175%. Meanwhile, the Ron,sp decreases by 45% and the breakdown voltage increases by 10%. In addition, the SJ-TMOS exhibits a low gate-to-drain charge (Qgd) due to the low permittivity of oxide trench and the nonlinearity in SJ capacitance characteristics.