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Modern high-tech MEMS manufacturing is not able to function without developed system of quality monitoring. Wellmanaged quality monitoring system enables to predict production risks and minimize them effectively. We devoted our research to such quality measurement tool as monitoring of product’s geometrical parameters between different MEMS manufacturing stages. This paper presents an example of automated approach to the analysis of optical images with the aim to control critical dimensions (CD) of MEMS products. For the purpose of CD monitoring, the special software has been developed. It executes several algorithms, such as image segmentation and Deriche edge detection, which allow to process one or several of images in a resource-saving manner. These algorithms were tested on both the interprocess control of critical dimensions and the control of kerf width and chipping after dicing technological process. As the result of their applying, huge-sized images (2 GB) are being processed in time less than 2 minutes and full optical inspection takes less than 10 minutes per wafer.

This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20 nm wide fins are fabricated using 193 nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300 nm and the electrically active fin height is 40 nm.

An improved fundamental understanding of the megasonic cleaning process is necessary to optimize cleaning efficiency and minimize the unwanted damage to fragile structures. Argon sonoluminescence (SL) measurements are done to achieve an improved insight in the collapse threshold and behavior of microbubbles. This paper reports on acoustic cavitation by means of Ar Sonoluminescence (SL) investigation achieved with a dedicated test cell, a photomultiplier tube (PMT) and a gasification system. The results show an increase in SL signal as a function of the applied acoustic power density. An increase in Ar concentration results in a decrease in SL signal. Furthermore, a clear hysteretic behavior in the SL signal is identified when ramping the acoustic power up and down. This hysteresis effect can be attributed to the nucleation of bubbles during the increasing branch of the power loop. Finally the time evolution of SL light after the switching on of the acoustic transducers revealed the existence of a delay time.

All-wet processes are gaining a renewed interest for the removal of post-etch photoresist (PR) and Bottom AntiReflective Coating (BARC) in the back-end-of-line (BEOL) semiconductor manufacturing, as plasma ash, traditionally used to remove the PR and BARC layer after etch, cause damage to the low-k dielectric. This study investigates the modification of 193 nm post-etch PR and BARC layer by UV irradiation, that can be used as an intermediate step to enhance PR and BARC wet strip by O3/H2O.

This work proposes an extended model that describes the propagation of damage in porous low-k material exposed to a plasma. Recent work has indicated that recombination and diffusion play a more dominant role than VUV light [1-5] in oxygen plasma induced damage. Especially at low depths, the radical concentration is determined by the number of radicals that disappear back into the plasma while the final depth of damage is defined by recombination of oxygen atoms. A logarithmic equation has been proposed to describe the behavior as a function of time. In this work this equation is extended to take diffusion into account, next to recombination. The results are in agreement with experimental data and one-dimensional random walk theory calculations. (C) 2010 Elsevier B.V. All rights reserved. ispartof: Microelectronic Engineering vol:88 issue:5 pages:631-634 ispartof: location:BELGIUM, Mechelen status: published

In this article, surface processes occurring during the etching of Si with a Cl2/O2/Ar plasma are investigated by means of experiments and modeling. Cl2-based plasmas are commonly used to etch silicon, while a small fraction of O2 is added to protect the sidewalls from lateral etching during the shallow trench isolation process. When the oxygen fraction exceeds a critical value, the wafer surface process changes from an etching regime to a deposition regime, drastically reducing the etch rate. This effect is commonly referred to as the etch stop phenomenon. To gain better understanding of this mechanism, the oxygen fraction is varied in the gas mixture and special attention is paid to the effects of oxygen and of the redeposition of non-volatile etched species on the overall etch/deposition process. It is found that, when the O2 flow is increased, the etch process changes from successful etching to the formation of a rough surface, and eventually to the actual growth of an oxide layer which completely blocks the etching of the underlying Si. The size of this etch stop island was found to increase as a function of oxygen flow, while its thickness was dependent on the amount of Si etched. This suggests that the growth of the oxide layer mainly depends on the redeposition of non-volatile etch products. The abrupt change in the etch rate as a function of oxygen fraction was not found back in the oxygen content of the plasma, suggesting the competitive nature between oxidation and chlorination at the wafer. Finally, the wafer and reactor wall compositions were investigated by modeling and it was found that the surface rapidly consisted mainly of SiO2 when the O2 flow was increased above about 15 sccm.

Continuous downscaling of integrated circuits brought an end to the era of SiO2. In gate dielectrics, it is being replaced by materials with high dielectric constant, so-called high-k dielectrics. One of the challenges in the integration of the high-k material is removal of those materials selectively over the substrate. This work is one of the first attempts to review current state of the art of the high-k removal. Two main approaches are discussed: dry (plasma) removal and wet removal. The best results could be achieved by combination of both.

During shallow trench isolation etching it was found that etch stop appears at the center of a 300 mm wafer as the temperature of the top quartz window of the etch chamber exceeds 85°C. We attributed the etch stop to redeposition of some low-volatile SiOxCly etch products. At low quartz window temperature part of the products are deposited on it, but as the window temperature rises well above the wafer temperature (which is constant at 60°C), the products primarily are deposited on the wafer causing the etch stop.

Spectroscopic ellipsometry could be used as a fast and accurate method to measure Si loss resulting from post ion implantation strip. It was found that upon implantation, even at low energies (around 1keV), the implanted layer has different optical properties from the crystalline Si. That allows ellipsometry to distinguish between Si substrate, implanted Si and SiO"2 on top. The ellipsometric measurements are confirmed by transmission electron microscopy (TEM). TEM shows that even if the Si is not amorphized at low energies, it is damaged (the lattice is strained) which is apparently enough to change the optical properties of Si. The exposure of implanted Si to an ash plasma at elevated temperatures (280^oC) results in SiO"2 growth and a decrease of the damaged Si thickness. The decrease is attributed partially to oxidation (Si loss) and partially to restoration of the strained lattice.

A model that combines the Monte Carlo method for calculating electron and ion trajectories in three-dimensional geometry and an analytic approach developed for calculating an electric field in two-dimensional geometry is used to simulate the charging of the surface of periodic submicron SiO2 structures by electron and ion fluxes in the plasma of a one- and a two-frequency capacitive RF discharge. The energy distribution function of the electrons and ions that come to the bottom of a submicron structure in an argon and an argon-containing plasma is calculated for structures with a width of 11–45 nm and an aspect ratio of d/w = 1–10 (where d and w are the depth and width of the structure). It is shown that secondary electronelectron emission plays an important role in the redistribution of the electric charge and, accordingly, of the electric potential in a submicron structure. It is demonstrated that, when the secondary electron-electron emission mechanism is taken into account, the ion energy spectrum at the bottom of a submicron structure is shifted toward lower energies and becomes broader in comparison with the spectrum of an ion flux from an RF discharge plasma. Moreover, the shift and broadening depend only on the secondary electron-electron emission coefficient, the energy of the charged particles, and the aspect ratio.

Uniformity and wafer-to-wafer reproducibility of plasma etch processes are often related to the conditioning of the plasma etch chamber walls. For advanced complementary metal-oxide semiconductor fabrication, numerous metals are used which might deposit on the chamber walls during etch processes and as these metals are not always straightforward to remove, process instabilities can occur. This happens because recombination of atomic species on the chamber walls determines to a certain degree the plasma composition. Therefore, in this article, the impact of metal etch residues, especially titanium and tantalum residues, on plasma composition and uniformity is studied. The chamber walls are analyzed by x-ray photoelectron spectroscopy analysis of so-called floating samples and the densities of Cl, Br, O and F in Cl2, HBr, O2, and SF6 plasmas are monitored by optical emission spectroscopy. Plasma uniformity is checked by measuring etch rates across 300 mm silicon wafers. It is found that chlorine and bromine...

Plasma damage of SiCOH low-k films in an oxygen plasma is studied using a transformer coupled plasma reactor. The concentration of oxygen atoms and O2+ ions is varied by using three different conditions: (1) bottom power only, (2) bottom and top power, and (3) top power only. After plasma exposure, the low-k samples are characterized by various experimental techniques. It is shown that the ion bombardment induced by the bottom power minimizes the plasma damage by increasing the recombination coefficient of oxygen radicals. Contrary to the expectations, the densification of the top surface by ion radiation was limited. The increase in the recombination coefficient is mainly provided by modification of the pore wall surface and creation of chemically active sites stimulating the recombination of oxygen atoms. The results show that a reduction in plasma damage can be achieved without sealing of low-k top surface. ispartof: Journal of Vacuum Science and Technology B vol:28 issue:3 pages:450-459 status: published

TaN is a potential candidate for metal gates. BCl3-based plasma is used to pattern metal gates because it has a high selectivity over Si substrate and capable of etching metal oxides (native oxides on metal gates and high-k dielectrics). During metal gate etch in inductively coupled plasma reactor, the authors found that the TaN metal gate profile depends on the composition of BCl3-based plasma. Pure BCl3 results in an undercut of TaN. The undercut can be avoided by addition of 5% O2, further increase in O2 concentration (until 10%) does not change the TaN profile. When N2 is added to BCl3 plasma, first the undercut disappears (at about 6% of N2) and then a slope appears as N2 concentration increases further (toward 10%). It was found that the profile is controlled by a film deposited from BCl3-based plasma. In the case of pure BCl3 plasma, the film consists of B (50%), Cl (30%), and O (20%). When 5% of O2 is added, no film is observed, but strong BO and BO2 peaks appear in the plasma emission spectra. Wh...

The modification of a SiOCH based low-k by oxygen plasma in a transformer coupled plasma (TCP) is reported. Modification of the film is studied as function of TCP power and time. Spectroscopic ellipsometry (SE) and Fourier transformed infrared absorption spectroscopy (FTIR) measurements are used for characterization. Both techniques show that the modification (damage) depth increases with increasing TCP power. Optical emission spectroscopy (OES) indicates that adding TCP power increases the O/O"2^+ ratio in the plasma. By means of FTIR and OES, evidence is found for the removal of hydrogen and carbon from the low-k during plasma exposure. Using a two-layer SE fitting model, and no TCP power a refractive index (RI) of 1.44 for the chemically altered top layer was found. This RI decreases with TCP power. Presumably, at increased TCP power, relatively more radicals are generated and they penetrate more easily because of a less dense top layer.

Spectroscopic ellipsometry (SE) model was developed to study substrate loss of shallow implanted silicon substrate following photoresist strip. Model is based on different optical properties of silicon oxide (SiO2) and implanted silicon (i-Si) layers and silicon substrate, and is used to characterize relevant layers, i-Si and SiO2, before and after plasma treatment. The increase in SiO2 and decrease in i-Si layer was observed after plasma exposure. Changes in i-Si layer are the result of two phenomena, oxidation and heating induced re-growth of i-Si layer, while changes in SiO2 thickness represent direct measure of substrate loss due to oxidation. Good agreement between TEM and SE measurements confirms that SE model can distinguish between crystalline (c-Si) substrate and i-Si, regardless if i-Si is only damaged, d-Si (crystalline) or amorphized, a-Si after implantation. We have also found consistency in SIMS dopant profiles and substrate losses extracted from SE measurements for plasma processes studied.

Continuous downscaling of integrated circuits brought an end to the era of SiO2. In gate dielectrics, it is being replaced by materials with high dielectric constant, so-called high-k dielectrics. One of the challenges in the integration of the high-k material is removal of those materials selectively over the substrate. This work is one of the first attempts to review current state of the art of the high-k removal. Two main approaches are discussed: dry (plasma) removal and wet removal. First, the fundamentals and limitations of both approaches are presented, then an overview of the existing experimental data is given. It is concluded that the best results could be obtained by combining the dry and wet approaches.

The role of plasma etching in the semiconductor technology upon switching from the microscale to the nanoscale dimensions is discussed. The continuing miniaturization has led to impossibility of simple scaling and further use of the conventional materials of silicon microelectronics. New materials and functional elements of integrated circuits call for revision of the existing plasma etching processes and development of novel processes. This situation brings plasma etching along with photolithography to the forefront of nanoelectronics technology.

The most advanced technology nodes require ultra shallow extension implants (low energy) which are very vulnerable to ash related substrate oxidation, silicon and dopant loss, which can result in a dramatic increase of the source/drain resistance and shifted transistor threshold voltages. A robust post extension ion implant ash process is required in order to meet cleanliness, near zero Si loss and dopant loss specifications. This paper discusses a performance comparison between fluorine-free, reducing and oxidizing, ash chemistries and “as implanted – no strip” process conditions, for both state-of-the-art nMOS and pMOS implanted fin resistors. Fluorine-free processes were chosen since earlier experiments with fluorine containing plasma strips exhibited almost a 10x increase in sheet resistance in the worse case.

In this paper we demonstrate the successful integration of in-situ doped embedded Si:C stressors epitaxially grown in the source and drain areas of nMOS devices using a novel Cyclic Deposition Etch (CDE) process. These layers have substitutional C content ranging between 1% and 2% with potential of achieving even higher substitutional carbon concentration. Another distinctive feature of this process is that it allows for high in-situ P doping for ease of integration within a CMOS platform. We demonstrate superior performance of strained nMOS devices with embedded Si:C showing up to 12.5% on-state current improvement over the unstrained reference process. We report on material characterization results of embedded Si:C stressors, in particular, strain retention properties as a function of subsequent post-epitaxy processing.

We propose a method for evaluating the hydrophilisation degree of low-k films upon plasma damage. The evaluation is based on optical emission spectroscopy analysis of O^* emission during He plasma exposure of sample in question. The O^* is presumably desorbed from damaged low-k film by vacuum-ultraviolet radiation from He plasma. The new method correlates well with other methods for plasma damage characterization such as Fourier Transform Infrared Spectroscopy and Water-Vapor Ellipsometric Porosimetry. The presented method gives a unique opportunity to assess the degree of hydrophilisation of low-k films immediately after processing.

Porous films are used nowadays as dielectrics with low dielectric constant (so-called low-k dielectrics). Knowing the porous structure of such films is important for successful integration in the semiconductor manufacturing technology. We developed a simple characterization method based on diffusion of solvents inside a porous film. In our experiments toluene as a non-polar solvent and ethanol as a polar solvent were used. A porous film is covered with a barrier impermeable for solvent so the solvent only can enter the film from the side. The barrier is transparent that allows observation of diffusion as a color change of the film. Measuring diffused distance as a function of diffusion time, diffusion coefficients can be calculated. It was found that the diffusion coefficients strongly depend on the porous structure of the films. Small pores (with the size comparable with the solvent molecule size) show low diffusion coefficients with high activation energies comparable with the enthalpy of evaporation. Bigger pores exhibit high diffusion coefficients with low activation energies corresponding to the activation energy of the solvent viscosity. Measuring diffusion coefficients as functions of porosity/pore size it is possible to evaluate the interconnectivity of the porous structure of a film in question.

We present a method to obtain Si-fins with a critical dimension (CD) below 20nm, separated by a minimum distance of 25nm and connected by a common source/drain (S/D) pad. The method comprises of recursive spacer defined patterning to quadruple the line density of a 350nm pitch resist pattern defined by 193nm lithography. Spacer defined patterning is combined with resist based patterning to simultaneously define fins and S/D pads in a Silicon on Insulator (SOI) film. CD and Line Width Roughness (LWR) analysis was done on top down SEM images taken in a center die and in an edge die of a 200mm wafer. The average CD is 17nm in the center of the wafer and 18nm at the edge. The LWR is 3nm for both center and edge. Additional process steps to remove etch damage and round the top corner of the fin (i.e. oxidation followed by H"2 anneal) further reduce the CD to 13nm.

Alternative high-k materials are being researched as a replacement for SiON. At present HfSiON is the most popular material because of good transistor performance. Still, issues such as threshold voltage control and a limited k-value improvement encourage continuing material screening. In this paper, we give a short overview of some of the work done in this field, where we focus on DyxSc2-xO3 as potential candidate. In addition, we discuss the use of the aqueous chemical solution-gel deposition technique as potential technique to facilitate high-k screening.

Selective Epitaxial Growth of SiGe and/or Si-cap/SiGe heterostructures offer an elegant way to improve pMOS device performance. This paper discusses some important challenges and characteristics of the corresponding epi process. Loading effects are strongly reduced by choosing the growth conditions away from the mass transport regime, i.e. by reducing the growth pressure and/or increasing the gas velocity. Anomalous SiGe thickening at convex corners of recessed areas and the impact of the underlying SiGe on the growth behavior during Si- capping are discussed as well. The limits of the chemical and thermal budgets during pre-epi treatments as defined by the device concepts require some process optimization but are not a show stopper.

Using strain to boost transistor performance and the use of metal gate electrodes are both considered to be key enablers for further improvements in device performance. This paper discusses the combination of Si1-xGex S/D, used as a pMOS stressor, with two metal gate options: inserted metal gates and FUSI

The etch properties of PVD TaN used as a metal gate electrode have been found to be dependent on its crystalline microstructure. As found by XRD, the initially amorphous TaN crystallizes at temperatures above 500C. The crystallization results in lower resistivity (decreased by 13%), and lower etch rate in BCl3 plasma (decreased by 24%). The different crystalline microstructure can manifest itself in different etch results when the same etch process is applied for gate stacks that contain the same TaN but were subjected to different thermal budget.

Recessed strained SiGe in the source/drain regions of planar Si pMOS devices is a well-known technique to enhance pMOS drive current. Both chemical vapour etching by HCl and conventional plasma etching have been proposed to define the source/drain recess. A comparison of both etching techniques brings us to the conclusion that isotropic plasma etching is the preferred etching technique. It avoids problems of facet formation during Si recess and allows better control of the lateral etching underneath the nitride spacer/gate oxide. Further, process optimization allows to minimize the variation in etch depth as function of window size. Surface damage caused during Si recess is removed by conventional cleans. High quality in situ doped SiGe layers, with boron concentrations up to ∼4 × 10 20 cm − 3 are grown, without modification of our standard pre-epi thermal treatments. The success of our SiGe source/drain fabrication scheme is demonstrated by a 40% improvement in pMOS drive current in comparison to Si reference devices.

We report on gate patterning development for the 45 nm node and beyond. Both poly-Si and different metal gates in combination with medium- k and high- k dielectrics have been defined. Source/drain silicon recess has been characterized for different stacks, yielding optimised processes for all investigated. Using hardmask based etching allowed us to produce sub-20 nm poly-Si and metal gates. Implementation of advanced metal gate patterning in already developed multi-gate field effect transistors (MuGFET) devices has been demonstrated.

In this work the removal of different metallic and particulate contaminants relevant for high-k/metal gate processing is studied. Best cleaning efficiency of both silicon and nitride substrates is achieved using a HF/HNO3-based cleaning resulting in a particle removal efficiency higher than 90% and metal removal down to 1010 at/cm2.

Performance improvements in microelectronic integrated circuits (ICs) over the past few decades have, for the most part, been achieved by increasing transistor speed, reducing transistor size, and packing more transistors onto a single chip. Smaller transistors work faster, so ICs have become faster and more complex. An emerging factor that may disrupt this trend is the slowing speed of signal propagation within the chip. Signal delays, caused by the interconnection wiring, increase with each generation of scaling and may soon limit the overall performance of the integrated system.

Atomic layer deposition (ALD) of tungsten carbide nitride (WC0.7N0.3) on a low-k (dielectric constant) dielectric aromatic polymer material is investigated. It is feasible to deposit thin WC0.7N0.3 films on polymers, but applying a nitrogen–oxygen (N2–O2) based plasma to the surface prior to ALD can significantly enhance the growth. The creation of polar surface groups by the plasma treatment is derived from the water contact angle and from O 1s to C 1s peak ratio extracted from x-ray photoelectron spectroscopy. Rutherford backscattering spectra and contact angle measurements revealed a typical ALD growth with at least two successive regimes. The first is controlled by the substrate surface, while during the last a constant amount of ALD material is added with each cycle. The plasma treatments create adsorption sites on the surface and therefore effectively enhance the growth and shorten the duration of the first regime. This observation is attributed to an improved initial ALD precursor adsorption. Howev...

Evaluation of diffusion barrier integrity is an important issue in advanced interconnects. A diffusion barrier separating Cu from low-k must be as thin as possible and must not contain pinholes. We have developed a method for measuring pinhole density in diffusion barriers deposited on low-k materials. The method employs ellipsometric porosimetry for measuring diffusion of toluene in a porous low-k film beneath the barrier in question.

Implementation of Cu/low-k in advanced interconnections requires a diffusion barrier to prevent copper penetration in low-k dielectrics. The barrier should be continuous to prevent copper diffusion and thin enough to keep interconnection line resistance low. Deposition of a diffusion barrier becomes an issue when porous low-k dielectrics are used. We developed a Monte Carlo simulation model to describe deposition of a diffusion barrier on a porous low-k film. The model provided explanation for the seating behavior of different porous film by TaN diffusion barrier. Previously we have shown that TaN barrier integrity depends on chemical nature of the substrate rather than on porous structure: the same barrier can be continuous on oxycarbide (SiOCH) but non-continuous on HSQ (hydrogen silsesquioxane) although porous structures of the two films are similar. Using the model, we show that surface diffusion of TaN during deposition plays a key role in continuous barrier formation. Presence of carbon suppresses TaN diffusion (probably by TaC formation) and the barrier does not penetrate deep into the film forming a continuous layer on the top surface. The model is also able to predict sealing behavior for different porous low-k films with different porosity/pore sizes.

The ever increasing requirements for electrical performance of on-chip wiring has driven three major technological advances in recent years. First, copper has replaced Aluminum as the new interconnect metal of choice, forcing also the introduction of damascene processing. Second, alternatives for SiO2 with a lower dielectric constant are being developed and introduced in main stream processing. The many new resulting materials needs to be classified in terms of their materials characteristics, evaluated in terms of their properties, and tested for process compatibility. Third, in an attempt to lower the dielectric constant even more, porosity is being introduced into these new materials. The study of processes such as plasma interactions and swelling in liquid media now becomes critical. Furthermore, pore sealing and the deposition of a thin continuous copper diffusion barrier on a porous dielectric are of prime importance. This review is an attempt to give an overview of the classification, the character...

Galvanic corrosion of copper as a function of barrier metal type together with the effect of acid type is investigated. Refractory metals such as Ta, Ti, and W are used as the barrier metals. HNO3-based and H2O2-based aqueous solutions are used to analyze the effect of acid type of the CMP slurry on the galvanic corrosion. The results show that the galvanic etch rate of copper is affected by the barrier metal type. In addition, the type of solution used is found to influence the barrier metal as well as the copper. Especially for the case of W, the change in the direction of the electrical current flow between copper and the barrier metal depending on the type of solution used seems to alter the galvanic reaction mechanism.

Four CVD SiOCH films deposited at various conditions were used for comparative evaluation. The films were evaluated by RBS, spectroscopic ellipsometry, and ellipsometric porosimetry. Oxygen plasma resistance was studied by spectroscopic ellipsometry and TOF-SIMS analysis after exposure of the films to downstream oxygen plasma. The different deposition conditions result in different carbon content and different porosity. The film with the highest carbon content has the lowest porosity and vice versa. As carbon content of films increases and their porosity decreases, the SiOCH films become more resistant to oxygen plasma.

The deposition of homogeneous thin films on porous substrates has been investigated. The thin film deposition of Ta(N) by physical vapor deposition on porous films with different average pore sizes and material compositions has been studied. The continuity of Ta(N) films on top of porous low-k dielectrics is evaluated by means of ellipsometric porosimetry combined with sheet resistance and atomic force microscopy measurements. Interface reactions are analyzed by x-ray photoelectron spectroscopy profiling. It has been observed that the minimal Ta(N) thickness required to obtain a continuous metal layer on top of the porous film depends, on the one hand, on the porosity and pore size and, on the other hand, on the chemical interaction of the thin film with the porous substrate. The sealing of pores is favored by the presence of carbon in the dielectric matrix. This is explained through a mechanism of local enhancement of the degree of crosslinking in the dielectric matrix, catalyzed by Ta.

This paper describes a method to manufacture bulk fins for finFET. The bulk fins consist of two parts: the straight top of 125nm height which is used as a fin and a sloped bottom of 200nm one that facilitates the trench filling. The method is based on a conventional shallow trench isolation (STI) process flow with an additional @a-C hard mask of 90nm (with antireflective SiOC coating of 35nm) on top of the STI stack (70nm nitride on top of 8nm oxide). The nitride layer and the top straight part of the fin is patterned using CH"2F"2/SF"6/N"2 chemistry and @a-C as a mask, while the bottom sloped part is patterned using Cl"2/O"2/N"2 chemistry and the nitride layer as a mask. After the etching, the STI process flow remains almost unchanged.

This letter reports on the implementation of high carbon content and high phosphorous content Si1-xCx layers in the source and drain regions of n-type MOSFET in a 65-nm-node integration scheme. The layers were grown using a novel epitaxial process. It is shown that by implementing stressors with x ap 0.01, nMOSFET device performance is enhanced by up to 10%, driving 880 muA/mum at 1-V V DD. It is also demonstrated that the successful implementation of Si1-xCx relies on the careful choice of integration and epitaxial layer parameters. There is a clear impact of the postepitaxial implantation and thermal treatment on the retained substitutional C content ([C sub]). Furthermore, adding a Si capping layer on top of the Si1 -xCx, greatly improves upon the stressors' stability during the downstream processing and the silicide sheet resistance.

Well-established analysis techniques, including secondary ions mass-spectrometry (SIMS) (Benninghoven et al., 1987; Brundle et al., 1992; Alford et al., 2007), high-resolution transmission electron microscopy (HRTEM) (Hirsch et al., 1977; Horiuchi, 1994; Williams & Carter, 2009) allow direct observation of the effect of ion implantation, although they suffer from being destructive, time consuming and unusable for real-time in-line monitoring of ion implantation process or to measure uniformity. Some of the more common methods, like sheet resistance measurements (four-point probe, FPP) (Keenan et al., 1985; Johnson, 2001; Schroder, 2006) and thermal-wave technology (TW) (Smith et al., 1985; Guidotti & van Driel, 1985; Smith et al., 1986), are fast and relatively inexpensive, but require special efforts in order to get reliable information and exclude measurement errors. Ideally, the technique should be non-destructive to the sample, fast, accurate and precise to be used for routine process monitoring and control.

This work presents a process to fabricate FinFETs in bulk silicon with advancements in critical fabrication steps such as STI trench oxide recess and adjustment of fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and FinFETs in the same wafer. Morphological and electrical results indicate perfectly filled trenches, better fin height control and bulk FinFET static performance similar to planar CMOS.

We report low V t (V t,Lg=1µm =±0.26V) high performance CMOS devices with ultra-scaled T inv down to T inv ∼8A using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3A reduction in nMOS and pMOS T inv (2) 220mV lower long channel pMOS V t (3) 21%/12% pMOS/nMOS drive current increase at I off =100nA/µm and (4) 50% improvement in long channel pMOS Vt variability. For a fixed T inv of 12A, a 4 times higher hole mobility and 350mV increase in NBTI 10years lifetime operating voltage are obtained.

In this paper, metal hard-ma.sk-based patterning schemes are proposed to pattern 30/30 nm line/space structures and 40-nm contact holes at 80 nm pitch. Various litho and etch approaches are compared and discussed. ispartof: pages:75-82 ispartof: Conf. Proc. AMC XXV: Mat. Res. Soc. pages:75-82 ispartof: Advanced Metalization Conference location:Baltimore date:13 Oct - 15 Oct 2009 status: published

Critical dimension (CD) shrink and patterning of contact features via plasma etching were studied for typical resistive random access memory (RRAM) stacks. These consist of SiO2 and Si3N4 (total thickness of 65 80 nm) with NiO or pure Ni at the bottom. First, the contact patterning of RRAM stacks was investigated for 90 nm contacts. Thus, a standard high power contact etch recipe was shown to give rise to resist strip challenges due to the incorporation of sputtered Ni in the resist film. Therefore, a low-sputter-yield contact etch recipe based on a CF4/H2/Ar gas chemistry was introduced. The ion sputter efficiency of the recipe was estimated from a blanket SiO2 sputter-yield experiment in Ar plasma for the same recipe settings: this yielded values close to the Ni sputter-yield threshold. Second, plasma-assisted CD shrink was studied in combination with the newly developed patterning scheme to get the contact CD well below the initial 90-nm litho print size. It was shown that a low contact etch power regime could also provide a larger window for contact CD shrink using a C2H4-based chemistry: e.g. the demonstrated CD shrink from 90 nm down to sub-40 nm was shown to be extremely challenging in the case of a high power regime due to polymer instability enhanced with the resulting thickness increase. Perhaps, the relaxation of the polymer film stress, which was measured to be in the range of 1200-1500 MPa, is more easily triggered at higher power settings, which leads to polymer blistering. Finally, the optimization of the plasma-assisted CD shrink step in combination with the low-sputter-yield contact etch recipe was demonstrated to be able to provide CDs as small as 27 nm. The demonstrated approach shows that plasma-assisted CD shrink can provide a robust test vehicle for research programs that require the patterning of small features in the sub-40-nm CD range.

The results of recent investigations show that after UV curing of CVD SiCOH low-k films deposited with organic material (porogen) some amount of the porogen remains in the cured films in the form of non-volatile graphitized phase, known as “porogen residue”. These residues could influence leakage current and reliability. The goal of the present work is investigation of the different parameters of UV curing that can influence amount of the porogen residue. In this work we focused generally on the study of the amount of porogen residues as function of the wavelength of curing light and the porosity of the material (amount of deposited porogen). To study the curing dependence on the wavelength, we compared optical properties (measured by spectroscopic ellipsometry) and IR adsorption (measured by FTIR) of samples cured by 172 nm monochromatic light (lamp A) with samples cured by broadband source with wavelength more than 200 nm (lamp B). To understand how the amount of porogen residue depends on the amount of deposited porogen (porosity), three films with different k-value were deposited: a film with k = 3 deposited without porogen and two porogen-based low-k with target k-value of 2.5 and 2.3. Furthermore, taking into account that He/H2 plasma effectively removes the porogen residues from porous films without any plasma damage of the matrix material, we exposed the films to that plasma. Then these films were cured by broadband lamp at different temperatures and amount of porogen residues was measured by ellipsometry. It was found that He/H2 plasma cannot fully remove the porogen and causes film shrinkage. The Subsequent UV curing does not produce significant changes.