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44 results on '"Denoulet, Julien"'

1. Embedded real-time monitoring using SystemC in IMA network

Author

Aloui, Zied, Ahamada, Nawfal, Denoulet, Julien, Pierre, Francine, Rayrole, Martin, Gatti, Marc, and Granado, Bertrand

Subjects
Computer Science - Software Engineering
Abstract

Avionics is one kind of domain where prevention prevails. Nonetheless fails occur. Sometimes due to pilot misreacting, flooded in information. Sometimes information itself would be better verified than trusted. To avoid some kind of failure, it has been thought to add,in midst of the ARINC664 aircraft data network, a new kind of monitoring.

Published
2017
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2. Network Attack Classification with a Shallow Neural Network for Internet and Internet of Things (IoT) Traffic.

Author

Ehmer, Jörg, Savaria, Yvon, Granado, Bertrand, David, Jean-Pierre, and Denoulet, Julien

Subjects
COMPUTER network traffic, COMPUTER network security, CYBERTERRORISM, MACHINE learning, TELECOMMUNICATION systems
Abstract

In recent years, there has been a tremendous increase in the use of connected devices as part of the so-called Internet of Things (IoT), both in private spaces and the industry. Integrated distributed systems have shown many benefits compared to isolated devices. However, exposing industrial infrastructure to the global Internet also generates security challenges that need to be addressed to benefit from tighter systems integration and reduced reaction times. Machine learning algorithms have demonstrated their capacity to detect sophisticated cyber attack patterns. However, they often consume significant amounts of memory, computing resources, and scarce energy. Furthermore, their training relies on the availability of datasets that accurately represent real-world data traffic subject to cyber attacks. Network attacks are relatively rare events, as is reflected in the distribution of typical training datasets. Such imbalanced datasets can bias the training of a neural network and prevent it from successfully detecting underrepresented attack samples, generally known as the problem of imbalanced learning. This paper presents a shallow neural network comprising only 110 ReLU-activated artificial neurons capable of detecting representative attacks observed on a communication network. To enable the training of such small neural networks, we propose an improved attack-sharing loss function to cope with imbalanced learning. We demonstrate that our proposed solution can detect network attacks with an F1 score above 99% for various attacks found in current intrusion detection system datasets, focusing on IoT device communication. We further show that our solution can reduce the false negative detection rate of our proposed shallow network and thus further improve network security while enabling processing at line rate in low-complexity network intrusion systems. [ABSTRACT FROM AUTHOR]

Published
2024
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7. Spinal cord monitoring by NIRS in reflection and transmission modes

Author

Tsiakaka, Olivier, Li, Songlin, Denoulet, Julien, Feruglio, Sylvain, Centre de recherche de l’Institut universitaire en santé mentale de Québec [Canada] (CERVO), Département de réadaptation (Faculté de médecine de l'Université Laval) [Canada], Faculté de médecine de l'Université Laval [Québec] (ULaval)-Faculté de médecine de l'Université Laval [Québec] (ULaval), Systèmes Electroniques (SYEL), LIP6, Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS)-Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS), and Feruglio, Sylvain

Subjects
[SDV.IB] Life Sciences [q-bio]/Bioengineering, [SPI.OPTI] Engineering Sciences [physics]/Optics / Photonic, [SPI.OPTI]Engineering Sciences [physics]/Optics / Photonic, [SDV.IB]Life Sciences [q-bio]/Bioengineering, [SPI.TRON] Engineering Sciences [physics]/Electronics, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; Real-time monitoring of the spinal cord was achieved on pig model with custom devices operating in both reflection and transmission modes. Although the reflective system was generally preferred, the obtained data wasn’t as rich as in transmission and could conduct to erroneous conclusions.

Published
2021

12. Modélisation et évaluation d’une architecture many-coeurs basée sur un réseau sur puce RF

Author

Brière, Alexandre, Romera, Thomas, Denoulet, Julien, Ecole Supérieure d'Informatique Electronique Automatique [Paris] (ESIEA), Architecture et Logiciels pour Systèmes Embarqués sur Puce (ALSOC), LIP6, Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS)-Sorbonne Université (SU)-Centre National de la Recherche Scientifique (CNRS), and Systèmes Electroniques (SYEL)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], ComputingMilieux_MISCELLANEOUS
Abstract

International audience

Published
2018

14. WiNoCoD: A Dynamically Reconfigurable RF NoC for Many-Core

Author

Brière, Alexandre, Denoulet, Julien, Pinna, Andrea, Granado, Bertrand, Pêcheux, Francois, Systèmes Electroniques (SYEL), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), Circuits Intégrés Numériques et Analogiques (CIAN), ANR-12-INSE-0004,WiNoCoD,Réseau sur puce basé sur des interconnexions RF reconfigurable à la demande(2012), Brière, Alexandre, and Ingénierie Numérique et Sécurité - Réseau sur puce basé sur des interconnexions RF reconfigurable à la demande - - WiNoCoD2012 - ANR-12-INSE-0004 - INS - VALID

Subjects
Reconfigurable, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Manycore, RF, CMP, SoC, NoC, Hierarchical, Network-on-chip
Abstract

National audience; With the growing number of cores on chips, conventional electrical interconnects reach scalability limits, leading the way for alternatives like Radio Frequency (RF), optical and 3D. Due to the variability of applications, communication needs change over time and across regions of the chip. To address these issues, we propose a dynamically reconfigurable Network on Chip (NoC) based on RF. We study the feasibility of the NoC on the basis of state of the art components. Furthermore, RF-NoC and electrical mesh communication latency are comparable for 256 nodes but RF becomes faster for wider networks.

Published
2017

15. A RF network-on-chip dynamically reconfigurable for many-cores

Author

Brière, Alexandre, Denoulet, Julien, Pinna, Andrea, Granado, Bertrand, Pecheux, François, Systèmes Electroniques (SYEL), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), Circuits Intégrés Numériques et Analogiques (CIAN), and ANR-12-INSE-0004,WiNoCoD,Réseau sur puce basé sur des interconnexions RF reconfigurable à la demande(2012)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], dynamic, hierarchical, hiérarchique, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES/C.1.2: Multiple Data Stream Architectures (Multiprocessors)/C.1.2.3: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch), multi-core, dynamique, RF, reconfigurable, CMP, many-cœurs, multi-cœurs, NoC, many-core
Abstract

National audience; The growing number of cores in a single chip goes along with an increase in communications. The variety of applications runing on the chip causes spatial and temporal heterogeneity of communications. To address these issues, we present in this paper a dynamically reconfigurable interconnect based on Radio Frequency (RF) for intra chip communications. The use of RF allows to increase the bandwidth while minimizing the latency. Dynamic reconfiguration of the interconnect allows to handle the heterogeneity of communications. We present the rationale for choosing RF over optics and 3D, the detailed architecture of the network and the chip implementing it, the evaluation of its feasibility and its performances. One advantage of this RF interconnect is the ability to broadcast without additional cost compared to point-topoint communications, opening new perspectives in terms of cache coherence.; La multiplication du nombre de cœurs de calcul présents sur une même puce va de pair avec une augmentation des besoins en communication. De plus, la variété des applications s’exécutant sur la puce provoque une hétérogénéité spatiale et temporelle des communications. C’est pour répondre à ces problématiques que nous présentons dans cet article un réseau d’interconnexion sur puce dynamiquement reconfigurable utilisant la Radio Fréquence (RF). L’utilisation de la RF permet d’avoir plus de bande passante en minimisant la latence. La possibilité de reconfigurer dynamiquement le réseau permet de s’adapter à la variabilité des communications. Nous présentons les raisons du choix de la RF par rapport aux autres nouvelles technologies du domaine que sont l’optique et la 3D, l’architecture détaillée de ce réseau et d’une puce le mettant en œuvre ainsi que l’évaluation de sa faisabilité et de ses performances. Un des avantages de ce réseau d’interconnexion RF est la possibilité de faire du broadcast sans surcoût par rapport aux communications point-à-point, ouvrant ainsi de nouvelles perspectives en termes de gestion de la cohérence mémoire notamment.

Published
2015

16. A hierarchical RF interconnect for MPSoC

Author

Brière, Alexandre, Denoulet, Julien, Pinna, Andrea, Granado, Bertrand, Pecheux, François, Systèmes Electroniques (SYEL), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), Circuits Intégrés Numériques et Analogiques (CIAN), ANR-12-INSE-0004,WiNoCoD,Réseau sur puce basé sur des interconnexions RF reconfigurable à la demande(2012), Brière, Alexandre, and Ingénierie Numérique et Sécurité - Réseau sur puce basé sur des interconnexions RF reconfigurable à la demande - - WiNoCoD2012 - ANR-12-INSE-0004 - INS - VALID

Subjects
MP SoC, Reconfigurable, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Mpsoc, Hardware_PERFORMANCEANDRELIABILITY, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, Hierarchical, Network-on-chip, MPSoCs, Manycore, Hardware_INTEGRATEDCIRCUITS, RF, [INFO.INFO-MO] Computer Science [cs]/Modeling and Simulation
Abstract

National audience; The increasing number of cores in a single chip goes along with the increase of communication needs. To address this issue, we propose a Network on Chip (NoC) using Radio Frequency (RF). We present the detailed architecture of this network and a Multi Processor System on Chip (MPSoC) usingit.

Published
2014

17. High Level Modeling of Signal Integrity in a USB 3.0 System

Author

Wang, Ruomin, Denoulet, Julien, Feruglio, Sylvain, Vallette, Farouk, Garda, Patrick, Systèmes Electroniques (SYEL), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), and Feruglio, Sylvain

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.TRON] Engineering Sciences [physics]/Electronics, ComputingMilieux_MISCELLANEOUS, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience

Published
2014

18. WiNoCoD : Un réseau d'interconnexion hiérarchique RF pour les MPSoC

Author

Brière, Alexandre, Denoulet, Julien, Pinna, Andrea, Granado, Bertrand, Pêcheux, François, Garda, Patrick, Ariaudo, Myriam, Drillet, Frédéric, Duperrier, Cédric, Hamieh, Mohamad, Quintanel, Sébastien, Romain, Olivier, Zerioul, Lounis, Louët, Yves, Moy, Christophe, Unlu, Eren, Bourdel, Emmanuelle, Systèmes Electroniques (SYEL), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), Circuits Intégrés Numériques et Analogiques (CIAN), ASTRE [Cergy-Pontoise], Equipes Traitement de l'Information et Systèmes (ETIS - UMR 8051), Ecole Nationale Supérieure de l'Electronique et de ses Applications (ENSEA)-Centre National de la Recherche Scientifique (CNRS)-CY Cergy Paris Université (CY)-Ecole Nationale Supérieure de l'Electronique et de ses Applications (ENSEA)-Centre National de la Recherche Scientifique (CNRS)-CY Cergy Paris Université (CY), Institut d'Électronique et des Technologies du numéRique (IETR), Nantes Université (NU)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), ANR-12-INSE-0004,WiNoCoD,Réseau sur puce basé sur des interconnexions RF reconfigurable à la demande(2012), Université de Nantes (UN)-Université de Rennes 1 (UR1), Brière, Alexandre, Ingénierie Numérique et Sécurité - Réseau sur puce basé sur des interconnexions RF reconfigurable à la demande - - WiNoCoD2012 - ANR-12-INSE-0004 - INS - VALID, Université de Nantes (UN)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), and Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)

Subjects
many cœur, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], multi cœur, WiNoCoD, RF, reconfigurable, MPSoC, NoC, hiérarchique
Abstract

International audience; La multiplication du nombre de cœurs de calcul présents sur les puces va de pair avec une augmentation des besoins en communication. C'est pour palier à ce problème que nous présentons dans cette article un réseau d'interconnexion sur puce utilisant la RF. Nous présentons les raisons du choix de la RF par rapport aux autres nouvelles technologies du domaine que sont l'optique et la 3D, l'architecture détaillée de ce réseau et d'une puce le mettant en œuvre ainsi que l'évaluation de sa faisabilité et de ses performances. Un des avantages potentiels de ce réseau d'interconnexion RF est la possibilité de faire du broadcast à faible coût, ce qui ouvre de nouvelles perspectives notamment en terme de gestion de la cohérence mémoire.

Published
2014

21. High Level Modeling of Signal Integrity in a High Frequency Point-to-Point System with SystemC-AMS

Author

Wang, Ruomin, Denoulet, Julien, Feruglio, Sylvain, Vallette, Farouk, Garda, Patrick, Systèmes Electroniques (SYEL), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), and Wang, Ruomin

Subjects
SystemC-AMS, signal integrity, High-level modeling, Point-to Point connections, [INFO.INFO-MO] Computer Science [cs]/Modeling and Simulation, high frequency, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation
Abstract

International audience; This paper addresses the modeling, at a high level of abstraction, of the functionality and Signal Integrity (SI) performances in a high frequency Point-to-Point connections (P2P) system. Our model is a unique platform, which includes a functional module and a non-functional module. The functional module represents the operative behavior of the P2P system and the non-functional module, based on neural network techniques, displays the SI characteristics. Our method was demonstrated by modeling a P2P of a Universal Serial Bus 3.0 (USB 3.0) system and it was applied to the prediction of transient waveforms and eye diagrams.

Published
2013

22. Modeling of signal integrity in bus communications with timed data flow SystemC-AMS

Author

Wang, Ruomin, Denoulet, Julien, Feruglio, Sylvain, Vallette, Farouk, Garda, Patrick, Systèmes Electroniques (SYEL), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), and Wang, Ruomin

Subjects
SystemC/SystemC-AMS, USB 3.0 Bus Communication, High-level modeling, [INFO.INFO-MO] Computer Science [cs]/Modeling and Simulation, neural networks, Signal Integrity, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation
Abstract

International audience; The paper presents a new method for modeling the functionality and Signal Integrity (SI) performances of bus communications at a high level of abstraction. Using neural networks, we build a SystemC/SystemC-AMS virtual platform that combines functional modules, which represent the operative behavior of the system, and non-functional modules based on neural network approximation, which display the systems SI characteristics. Our method was demonstrated by modeling a Universal Serial Bus 3.0 (USB 3.0) system and was applied to the prediction of transient waveforms and eye diagrams. Compared to a HSPICE simulation, our method achieves excellent accuracy (mean absolute error of 1%) with a much shorter simulation time (×6000 speedup).

Published
2013

23. High Level Modeling of Signal Integrity in High Frequency USB 3.0 Systems with SystemC-AMS

Author

Wang, Ruomin, Denoulet, Julien, Feruglio, Sylvain, Vallette, Farouk, Garda, Patrick, Publications, Lip6, Systèmes Electroniques (SYEL), Laboratoire d'Informatique de Paris 6 (LIP6), and Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)

Subjects
[INFO]Computer Science [cs], [INFO] Computer Science [cs], ComputingMilieux_MISCELLANEOUS
Abstract

National audience

Published
2013

24. Modeling Field Bus Communication with SystemC-AMS

Author

Wang, Ruomin, Alassir, Mohamad Dib, Denoulet, Julien, Feruglio, Sylvain, Vallette, Farouk, Garda, Patrick, Systèmes Electroniques (SYEL), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), and Publications, Lip6

Subjects
[INFO]Computer Science [cs], [INFO] Computer Science [cs], ComputingMilieux_MISCELLANEOUS
Abstract

National audience

Published
2012

25. A Dynamically Reconfigurable RF NoC for Many-Core

Author

Brière, Alexandre, primary, Denoulet, Julien, additional, Pinna, Andrea, additional, Granado, Bertrand, additional, Pêcheux, Francois, additional, Unlu, Eren, additional, Louët, Yves, additional, and Moy, Christophe, additional

Published
2015
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27. Case study analysis of linear Chirp and multi-tones radar signals through simulations and measurement with HYCAM-Research test bench

Author

Le Kernec, Julien, Dreuillet, Philippe, Bobillot, Gerard, Castelli, Juan-Carlos, Garda, Patrick, Romain, Olivier, Denoulet, Julien, Systèmes Electroniques (SYEL), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), ONERA - The French Aerospace Lab [Palaiseau], ONERA-Université Paris Saclay (COmUE), and Le Kernec, Julien

Subjects
[SPI.ELEC]Engineering Sciences [physics]/Electromagnetism, [SPI.ELEC] Engineering Sciences [physics]/Electromagnetism, ComputerSystemsOrganization_SPECIAL-PURPOSEANDAPPLICATION-BASEDSYSTEMS, [SPI.TRON] Engineering Sciences [physics]/Electronics, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

National audience; This paper present a experimental platform that allows comparing objectively any radar waveforms. This is realized by equating radar characteristics, using the same test-bench HYCAM-Research, the same signal processing and also the reproducibility of the experiments. The experimental measurements on linear chirp and multitones are analyzed through distance and velocity imaging.

Published
2009

28. Case Study Analysis of Linear Chirp and Multitones (OFDM) Radar Signals Through Simulations and Measurement with HYCAM-Research Test Bench

Author

Le Kernec, Julien, Dreuillet, Philippe, Bobillot, Gerard, Garda, Patrick, Romain, Olivier, Denoulet, Julien, Systèmes Electroniques (SYEL), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), ONERA - The French Aerospace Lab [Palaiseau], ONERA-Université Paris Saclay (COmUE), and Le Kernec, Julien

Subjects
[SPI.ELEC]Engineering Sciences [physics]/Electromagnetism, [SPI.ELEC] Engineering Sciences [physics]/Electromagnetism, [SPI.TRON] Engineering Sciences [physics]/Electronics, [SPI.TRON]Engineering Sciences [physics]/Electronics
Abstract

International audience; This paper presents a experimental platform that allows comparing objectively any radar waveforms. This is realized by equating radar characteristics, using the same test-bench HYCAM-Research, the same signal processing and also insuring the reproducibility of the experiments. The experimental measurements on linear chirp and multitones are analyzed through distance and velocity imaging.

Published
2009

29. Modeling I2C Communication Between SoCs with SystemC-AMS

Author

Alassir, Mohammad, Denoulet, Julien, Romain, Olivier, Garda, Patrick, Systèmes Electroniques (SYEL), Laboratoire d'Informatique de Paris 6 (LIP6), and Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)

Subjects
[INFO]Computer Science [cs], Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION, Hardware_LOGICDESIGN
Abstract

International audience; In this paper, we show how to mode the I2C bus communications between the nodes of an embedded system. For this purpose, we use the SystemC-AMS model of an I2C bus controller IP based on the PFC8584. Then we show how this IP can be included into two kinds of embedded systems nodes: on the one hand a 8051 micro-controller node, on the other hand a MIPS based SOC node. Finally the simulation results show the successful operation of the multi-master I2C bus communications between these two nodes in SystemC-AMS. Moreover the SystemC-AMS simulation introduces a small 10% overhead over the digital SystemC simulation for the two nodes multi-master I2C communication.

Published
2007

30. Modeling field bus communications for automotive applications

Author

Alassir, Mohammad, Denoulet, Julien, Romain, Olivier, Vasilescu, Gabriel, Arnaud, Romain, Garda, Patrick, Publications, Lip6, Systèmes Electroniques (SYEL), Laboratoire d'Informatique de Paris 6 (LIP6), and Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)

Subjects
[INFO]Computer Science [cs], [INFO] Computer Science [cs], Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION, Hardware_LOGICDESIGN
Abstract

International audience; In this paper, we present a modeling platform using the SystemC-AMS language to simulate field bus communications in automotive applications. Our platform includes the model of an I/O controller IP (in this specific case an I²C controller) that interfaces a master microprocessor with its peripherals on the field bus. Our platform shows the execution of the embedded software and its analog response on the lines of the bus. Moreover, it also takes into account the influence of the circuits’ I/O by including their IBIS models in the SystemC-AMS description, as well as the bus lines imperfections. Finally, we present simulation results to validate our platform and show that the overhead introduced by SystemC-AMS over a pure digital SystemC simulation is about 10%

Published
2007

33. An OFDMA based RF interconnect for massive multi-core processors

Author

Unlu, Eren, primary, Hamieh, Mohamad, additional, Moy, Christophe, additional, Ariaudo, Myriam, additional, Louet, Yves, additional, Drillet, Frederic, additional, Briere, Alexandre, additional, Zerioul, Lounis, additional, Denoulet, Julien, additional, Pinna, Andrea, additional, Granado, Bertrand, additional, Pecheux, Francois, additional, Duperrier, Cedric, additional, Quintanel, Sebastien, additional, Romain, Olivier, additional, and Bourdel, Emmanuelle, additional

Published
2014
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34. Flexible Radio Interface for NoC RF-Interconnect

Author

Drillet, Frederic, primary, Hamieh, Mohamad, additional, Zerioul, Lounis, additional, Briere, Alexandre, additional, Unlu, Eren, additional, Ariaudo, Myriam, additional, Louet, Yves, additional, Bourdel, Emmanuelle, additional, Denoulet, Julien, additional, Pinna, Andrea, additional, Granado, Bertrand, additional, Garda, Patrick, additional, Pecheux, Francois, additional, Duperrier, Cedric, additional, Quintanel, Sebastien, additional, Meunier, Philippe, additional, Moy, Christophe, additional, and Romain, Olivier, additional

Published
2014
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36. Architecture for Hardware Compression / Decompression of Large Images

Author

Akil, Mohamed, Perroton, Laurent, Gailhard, S., Denoulet, Julien, Bartier, F., inconnu temporaire UPEMLV, and Inconnu

Subjects
ComputingMilieux_MISCELLANEOUS, [INFO.INFO-CL]Computer Science [cs]/Computation and Language [cs.CL]
Abstract

International audience

Published
2001

44. Interfacing SoCLib CABA models with NoCBench for NoC perfomance evaluation

Author

Muhammad Moazam Azeem, Alexandre Briere, Manuel Bouyer, Julien Denoulet, Francois Pecheux, Andrea Pinna, Bertrand Granado, Systèmes Electroniques (SYEL), Laboratoire d'Informatique de Paris 6 (LIP6), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), Université Pierre et Marie Curie - Paris 6 (UPMC)-Centre National de la Recherche Scientifique (CNRS), Circuits Intégrés Numériques et Analogiques (CIAN), ANR, ANR-12-INSE-0004,WiNoCoD,Réseau sur puce basé sur des interconnexions RF reconfigurable à la demande(2012), Denoulet, Julien, and Ingénierie Numérique et Sécurité - Réseau sur puce basé sur des interconnexions RF reconfigurable à la demande - - WiNoCoD2012 - ANR-12-INSE-0004 - INS - VALID

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Hardware_INTEGRATEDCIRCUITS, Hardware_PERFORMANCEANDRELIABILITY, ComputerSystemsOrganization_PROCESSORARCHITECTURES
Abstract

International audience; The number of cores in a single chip increases with the increase of communication needs. Network on Chips (NoCs) are developed to handle these needs. We present our work to evaluate models of NoC present in the SoCLib library with the NoCBench platform. NoCBench contains performance evaluation tools for NoC such as a Transaction Generator and an Execution Monitor. SoClib is a library of IP cores, including NoC, written in SystemC, we retain the WiNoCoD RF-NoC as a use case. Various benchmarks can be ported to our NoC to evaluate its performance and it can be compared with existing NoCs which used the same performance evaluation tools under NoCBench.

Published
2015

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