19 results on '"Denoyelle, Nicolas"'
Search Results
2. Modeling Large Compute Nodes with Heterogeneous Memories with Cache-Aware Roofline Model
- Author
-
Denoyelle, Nicolas, Goglin, Brice, Ilic, Aleksandar, Jeannot, Emmanuel, Sousa, Leonel, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Jarvis, Stephen, editor, Wright, Steven, editor, and Hammond, Simon, editor
- Published
- 2018
- Full Text
- View/download PDF
3. From Biological to Numerical Experiments in Systemic Neuroscience: A Simulation Platform
- Author
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Denoyelle, Nicolas, Carrere, Maxime, Pouget, Florian, Viéville, Thierry, Alexandre, Frédéric, Guglielmelli, Eugenio, Series editor, Londral, Ana Rita, editor, and Encarnação, Pedro, editor
- Published
- 2016
- Full Text
- View/download PDF
4. A Topology-Aware Performance Monitoring Tool for Shared Resource Management in Multicore Systems
- Author
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Denoyelle, Nicolas, Goglin, Brice, Jeannot, Emmanuel, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Hunold, Sascha, editor, Costan, Alexandru, editor, Giménez, Domingo, editor, Iosup, Alexandru, editor, Ricci, Laura, editor, Gómez Requena, María Engracia, editor, Scarano, Vittorio, editor, Varbanescu, Ana Lucia, editor, Scott, Stephen L., editor, Lankes, Stefan, editor, Weidendorfer, Josef, editor, and Alexander, Michael, editor
- Published
- 2015
- Full Text
- View/download PDF
5. NUMA-AWARE DATA MANAGEMENT FOR NEUTRON CROSS SECTION DATA IN CONTINUOUS ENERGY MONTE CARLO NEUTRON TRANSPORT SIMULATION
- Author
-
Denoyelle Nicolas, Tramm John, Yoshii Kazutomo, Perarnau Swann, and Beckman Pete
- Subjects
Physics ,QC1-999 - Abstract
The calculation of macroscopic neutron cross-sections is a fundamental part of the continuous-energy Monte Carlo (MC) neutron transport algorithm. MC simulations of full nuclear reactor cores are computationally expensive, making high-accuracy simulations impractical for most routine reactor analysis tasks because of their long time to solution. Thus, preparation of MC simulation algorithms for next generation supercomputers is extremely important as improvements in computational performance and efficiency will directly translate into improvements in achievable simulation accuracy. Due to the stochastic nature of the MC algorithm, cross-section data tables are accessed in a highly randomized manner, resulting in frequent cache misses and latency-bound memory accesses. Furthermore, contemporary and next generation non-uniform memory access (NUMA) computer architectures, featuring very high latencies and less cache space per core, will exacerbate this behaviour. The absence of a topology-aware allocation strategy in existing high-performance computing (HPC) programming models is a major source of performance problems in NUMA systems. Thus, to improve performance of the MC simulation algorithm, we propose a topology-aware data allocation strategies that allow full control over the location of data structures within a memory hierarchy. A new memory management library, known as AML, has recently been created to facilitate this mapping. To evaluate the usefulness of AML in the context of MC reactor simulations, we have converted two existing MC transport cross-section lookup “proxy-applications” (XSBench and RSBench) to utilize the AML allocation library. In this study, we use these proxy-applications to test several continuous-energy cross-section data lookup strategies (the nuclide grid, unionized grid, logarithmic hash grid, and multipole methods) with a number of AML allocation schemes on a variety of node architectures. We find that the AML library speeds up cross-section lookup performance up to 2x on current generation hardware (e.g., a dual-socket Skylake-based NUMA system) as compared with naive allocation. These exciting results also show a path forward for efficient performance on next-generation exascale supercomputer designs that feature even more complex NUMA memory hierarchies.
- Published
- 2021
- Full Text
- View/download PDF
6. Modeling Large Compute Nodes with Heterogeneous Memories with Cache-Aware Roofline Model
- Author
-
Denoyelle, Nicolas, primary, Goglin, Brice, additional, Ilic, Aleksandar, additional, Jeannot, Emmanuel, additional, and Sousa, Leonel, additional
- Published
- 2017
- Full Text
- View/download PDF
7. From Biological to Numerical Experiments in Systemic Neuroscience: A Simulation Platform
- Author
-
Denoyelle, Nicolas, primary, Carrere, Maxime, additional, Pouget, Florian, additional, Viéville, Thierry, additional, and Alexandre, Frédéric, additional
- Published
- 2015
- Full Text
- View/download PDF
8. Narrowing the Search Space of Applications Mapping on Hierarchical Topologies
- Author
-
Denoyelle, Nicolas, primary, Perarnau, Swann, additional, Videau, Brice, additional, Beckman, Pete, additional, and Jeannot, Emmanuel, additional
- Published
- 2021
- Full Text
- View/download PDF
9. A Topology-Aware Performance Monitoring Tool for Shared Resource Management in Multicore Systems
- Author
-
Denoyelle, Nicolas, primary, Goglin, Brice, additional, and Jeannot, Emmanuel, additional
- Published
- 2015
- Full Text
- View/download PDF
10. Explicit Data Layout Management for Autotuning Exploration on Complex Memory Topologies
- Author
-
Perarnau, Swann, primary, Videau, Brice, additional, Denoyelle, Nicolas, additional, Monna, Florence, additional, Iskra, Kamil, additional, and Beckman, Pete, additional
- Published
- 2019
- Full Text
- View/download PDF
11. From Software Locality to Hardware Locality in Shared Memory Systems with NUMA and Heterogenous Memory
- Author
-
Denoyelle, Nicolas, Laboratoire Bordelais de Recherche en Informatique (LaBRI), Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB), Topology-Aware System-Scale Data Management for High-Performance Computing (TADAAM), Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Inria Bordeaux - Sud-Ouest, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria), Bull atos technologies, Université de Bordeaux, Brice Goglin, Emmanuel Jeannot, Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS), and Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Inria Bordeaux - Sud-Ouest
- Subjects
Mapping ,Memory ,Modélisation ,Applications ,Calcul haute performance ,High-Performance-Computing ,Mémoire ,Locality ,Localité ,[INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] ,Model ,Placement - Abstract
Through years, the complexity of High Performance Computing (HPC) systems’ memory hierarchy has increased. Nowadays, large scale machines typically embed several levels of caches and a distributed memory. Recently, on-chip memories and non-volatile PCIe based flash have entered the HPC landscape. This memory architecture is a necessary pain to obtain high performance, but at the cost of a thorough task and data placement. Hardware managed caches used to hide the tedious locality optimizations. Now, data locality, in local or remote memories, in fast or slow memory, in volatile or non-volatile memory, with small or wide capacity, is entirely software manageable. This extra flexibility grants more freedom to application designers but with the drawback of making their work more complex and expensive. Indeed, when managing tasks and data placement, one has to account for several complex trade-offs between memory performance, size and features. This thesis has been supervised between Atos Bull Technologies and Inria Bordeaux – Sud-Ouest. In the hereby document, we detail contemporary HPC systems and characterize machines performance for several locality scenarios. We explain how the programming language semantics affects data locality in the hardware, and thus applications performance. Through a joint work with the INESC-ID laboratory in Lisbon, we propose an insightful extension to the famous Roofline performance model in order to provide locality hints and improve applications performance. We also present a modeling framework to map platform and application performance events to the hardware topology, in order to extract synthetic locality metrics. Finally, we propose an automatic locality policy selector, on top of machine learning algorithms, to easily improve applications tasks and data placement.; La hiérarchie mémoire des serveurs de calcul est de plus en plus complexe. Les machines disposent de plusieurs niveaux de caches plus ou moins partagés et d’une mémoire distribuée. Plus récemment le paysage du Calcul Haute Performance (CHP) a vu apparaître des mémoires adressables embarquées dans le processeur ainsi que de nouvelles mémoires non-volatiles (périphérique mémoire sur le bus d’entrées sorties et prochainement de la mémoire non-volatile directement sur le bus mémoire). Cette hiérarchie est nécessaire pour espérer obtenir de bonnes performances de calcul, au prix d’une gestion minutieuse du placement des données et des tâches de calcul. Là où la gestion des caches était entièrement matérielle et masquée au développeur, le choix du placement des données dans telle ou telle zone de mémoire, plus ou moins rapide, volatile ou non, volumineuse ou non, est maintenant paramétrable logiciellement. Cette nouvelle flexibilité donne une grande liberté aux développeurs mais elle complexifie surtout leur travail quand il s’agit de choisir les stratégies d’allocation, de communication, de placement, etc. En effet, les caractéristiques des nombreux niveaux de hiérarchie impliqués varient significativement en vitesse, taille et fonctionnalités. Dans cette thèse, co-encadrée entre Atos Bull Technologies et Inria Bordeaux– Sud-Ouest, nous détaillons la structure des plates-formes contemporaines et caractérisons la performance des accès à la mémoire selon plusieurs scénarios de localité des tâches de calcul et des données accédées. Nous expliquons comment la sémantique du langage de programmation impacte la localité des données dans la machine et donc la performance des applications. En collaboration avec le laboratoire INESC-ID de Lisbonne, nous proposons une extension au célèbre modèle Roofline pour exposer de manière intelligible les compromis de performance et de localité aux développeurs d’applications. Nous proposons par ailleurs un outil de synthèse de métriques de localité mettant en lien les évènements de performance de l’application et de la machine avec la topologie de cette dernière. Enfin, nous proposons une approche statistique pour sélectionner automatiquement la meilleure politique de placement des tâches de calcul sur les coeurs de la machine et des données sur les mémoires.
- Published
- 2018
12. NUMA-AWARE DATA MANAGEMENT FOR NEUTRON CROSS SECTION DATA IN CONTINUOUS ENERGY MONTE CARLO NEUTRON TRANSPORT SIMULATION.
- Author
-
Margulis, M., Blaise, P., Denoyelle, Nicolas, Tramm, John, Yoshii, Kazutomo, Perarnau, Swann, and Beckman, Pete
- Subjects
NEUTRON transport theory ,NUCLEAR fission ,NEUTRON diffusion ,NEUTRON flux ,NUCLEAR reactor cores - Abstract
The calculation of macroscopic neutron cross-sections is a fundamental part of the continuous-energy Monte Carlo (MC) neutron transport algorithm. MC simulations of full nuclear reactor cores are computationally expensive, making high-accuracy simulations impractical for most routine reactor analysis tasks because of their long time to solution. Thus, preparation of MC simulation algorithms for next generation supercomputers is extremely important as improvements in computational performance and efficiency will directly translate into improvements in achievable simulation accuracy. Due to the stochastic nature of the MC algorithm, cross-section data tables are accessed in a highly randomized manner, resulting in frequent cache misses and latency-bound memory accesses. Furthermore, contemporary and next generation non-uniform memory access (NUMA) computer architectures, featuring very high latencies and less cache space per core, will exacerbate this behaviour. The absence of a topology-aware allocation strategy in existing high-performance computing (HPC) programming models is a major source of performance problems in NUMA systems. Thus, to improve performance of the MC simulation algorithm, we propose a topology-aware data allocation strategies that allow full control over the location of data structures within a memory hierarchy. A new memory management library, known as AML, has recently been created to facilitate this mapping. To evaluate the usefulness of AML in the context of MC reactor simulations, we have converted two existing MC transport cross-section lookup "proxy-applications" (XSBench and RSBench) to utilize the AML allocation library. In this study, we use these proxy-applications to test several continuous-energy cross-section data lookup strategies (the nuclide grid, unionized grid, logarithmic hash grid, and multipole methods) with a number of AML allocation schemes on a variety of node architectures. We find that the AML library speeds up cross-section lookup performance up to 2x on current generation hardware (e.g., a dual-socket Skylake-based NUMA system) as compared with naive allocation. These exciting results also show a path forward for efficient performance on next-generation exascale supercomputer designs that feature even more complex NUMA memory hierarchies. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
13. Automatic Cache Aware Roofline Model Building and Validation Using Topology Detection
- Author
-
Denoyelle, Nicolas, Ilic, Aleksandar, Goglin, Brice, Sousa, Leonel, Jeannot, Emmanuel, Topology-Aware System-Scale Data Management for High-Performance Computing (TADAAM), Laboratoire Bordelais de Recherche en Informatique (LaBRI), Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Inria Bordeaux - Sud-Ouest, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria), Instituto Superior Técnico, Universidade Técnica de Lisboa (IST), Instituto de Engenharia de Sistemas e Computadores Investigação e Desenvolvimento em Lisboa (INESC-ID), Instituto Superior Técnico, Universidade Técnica de Lisboa (IST)-Instituto de Engenharia de Sistemas e Computadores (INESC), Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS), NESUS WG2, Jesus Carretero, INESC-ID, Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Inria Bordeaux - Sud-Ouest, Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB), and Denoyelle, Nicolas
- Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] ,[INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR] ,DRAM ,Cache ,plafrim ,[INFO.INFO-DC] Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] ,hwloc ,Roofline Model ,Tool ,Cache Aware Roofline Model ,[INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] - Abstract
International audience; The ever growing complexity of high performance computing systems imposes significant challenges to exploit as much as possible their computational and memory resources. Recently, the Cache-aware Roofline Model has gained popularity due to its simplicity when modeling multi-cores with complex memory hierarchy, characterizing applications bottlenecks, and quantifying achieved or remaining improvements. In this short paper we involve hardware locality topology detection to build the Cache Aware Roofline Model for modern processors in an open-source locality-aware tool. The proposed tool also includes a set of specific micro-benchmarks to assess the micro-architecture performance upper-bounds. The experimental results show that by relying on the proposed tool, it was possible to reach near-theoretical bounds of an Intel 3770K processor, thus proving the effectiveness of the modeling methodology.
- Published
- 2016
14. Data and Thread Placement in NUMA Architectures
- Author
-
Denoyelle, Nicolas, primary, Goglin, Brice, additional, Jeannot, Emmanuel, additional, and Ropars, Thomas, additional
- Published
- 2019
- Full Text
- View/download PDF
15. Modeling Non-Uniform Memory Access on Large Compute Nodes with the Cache-Aware Roofline Model
- Author
-
Denoyelle, Nicolas, primary, Goglin, Brice, additional, Ilic, Aleksandar, additional, Jeannot, Emmanuel, additional, and Sousa, Leonel, additional
- Published
- 2019
- Full Text
- View/download PDF
16. Moniteurs hiérarchiques de performance, pour gérer l’utilisation des ressources partagées de la topologie
- Author
-
Denoyelle, Nicolas, Topology-Aware System-Scale Data Management for High-Performance Computing (TADAAM), Laboratoire Bordelais de Recherche en Informatique (LaBRI), Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Inria Bordeaux - Sud-Ouest, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria), Atos - Inria, Denoyelle, Nicolas, and Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Inria Bordeaux - Sud-Ouest
- Subjects
[INFO]Computer Science [cs] ,[INFO] Computer Science [cs] ,parallélisme outil localité topologie multicoeur performance hiérarchie moniteur partage caractérisation modèle analyse - Abstract
National audience; L'avènement des machines multicoeurs et manycoeurs a permis en partie de soutenir la crois-sance de la performance des machines de calcul. Cependant, l'accroissement du nombre d'uni-tés d'exécution n'est pas nécessairement synonyme de réduction de la durée d'exécution. Les différentes tâches d'une application peuvent entre autre s'interrompre pour envoyer ou at-tendre des messages (synchronisations) ou concourir pour utiliser une ressource matérielle partagée dans la machine. Lorsque la modification du code n'est pas permise (e.g dans un support d'exécution), le placement des tâches et des données permet de surmonter en partie ces problèmes, respectivement en minimisant le chemin des communications, ou en équilibrant la charge sur la machine. Dans ces deux cas, il est nécessaire d'avoir un modèle de l'architec-ture et des métriques sur l'utilisation de celle-ci, pour espérer caractériser le couple (machine, application) et calculer un placement efficace. Dans ce contexte, nous proposons un outil de mesure de performances, permettant d'agréger des évènements collectés au cours du temps sur des noeuds de la topologie d'une machine afin d'en tirer une analyse couplée du programme et de la machine. Cet outil est basé sur un modèle d'architecture fourni par hwloc et des greffons de collecte d'évènements (implémentés avec papi et maqao) et permet l'analyse d'applications parallèles sur un système. L'outil proposé ne réalise pas directement cette analyse mais propose des mécanismes pour y parvenir. Un utilitaire permet d'afficher la topologie et l'évolution des évènements ainsi que de générer une trace des évènements collectés, accompagnés de leur localisation, au cours du temps. Nous montrons avec une application simple écrite pour l'occasion qu'il est possible d'utiliser les résultats fournis par notre outil pour déduire un placement des fils d'exécution plus efficace.
- Published
- 2016
17. Automatic Cache Aware Roofline Model Building and Validation Using
- Author
-
Denoyelle, Nicolas, Ilic, Aleksandar, Goglin, Brice, Sousa, Leonel, Jeannot, Emmanuel, Carretero Pérez, Jesús, García Blas, Javier, Margenov, Svetozar, and Universidad Carlos III de Madrid. Computer Architecture, Communications and Systems Group (ARCOS)
- Subjects
Informática ,DRAM ,Cache ,Roofline Model ,Tool ,Cache Aware Roofline Model ,Hw loc - Abstract
Proceedings of: Third International Workshop on Sustainable Ultrascale Computing Systems (NESUS 2016). Sofia (Bulgaria), October, 6-7, 2016. The ever growing complexity of high performance computing systems imposes significant challenges to exploit as much as possible their computational and memory resources. Recently, the Cache-aware Roofline Model has gained popularity due to its simplicity when modeling multi-cores with complex memory hierarchy, characterizing applications bottlenecks, and quantifying achieved or remaining improvements. In this short paper we involve hardware locality topology detection to build the Cache Aware Roofline Model for modern processors in an open-source locality-aware tool. The proposed tool also includes a set of specific micro-benchmarks to assess the micro-architecture performance upper-bounds. The experimental results show that by relying on the proposed tool, it was possible to reach near-theoretical bounds of an Intel 3770K processor, thus proving the effectiveness of the modeling methodology. We would like to acknowledge Action IC1305 (NESUS) for funding this work.
- Published
- 2016
18. VirtualEnaction - A Platform for Systemic Neuroscience Simulation
- Author
-
Denoyelle, Nicolas, primary, Pouget, Florian, primary, Vieville, Thierry, primary, and Alexandre, Frédéric, primary
- Published
- 2014
- Full Text
- View/download PDF
19. From Software Locality to Hardware Locality in Shared Memory Systems with NUMA and Heterogenous Memory
- Author
-
Denoyelle, Nicolas, Goglin, Brice, Jeannot, Emmanuel, Papauré, Guillaume, Legrand, Arnaud, Carribault, Patrick, and STAR, ABES
- Subjects
Mapping ,Memory ,Modélisation ,Applications ,[INFO.INFO-DC] Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] ,Calcul haute performance ,High-Performance-Computing ,Mémoire ,Locality ,Localité ,Model ,Placement - Abstract
Through years, the complexity of High Performance Computing (HPC) systems’ memory hierarchy has increased. Nowadays, large scale machines typically embed several levels of caches and a distributed memory. Recently, on-chip memories and non-volatile PCIe based flash have entered the HPC landscape. This memory architecture is a necessary pain to obtain high performance, but at the cost of a thorough task and data placement. Hardware managed caches used to hide the tedious locality optimizations. Now, data locality, in local or remote memories, in fast or slow memory, in volatile or non-volatile memory, with small or wide capacity, is entirely software manageable. This extra flexibility grants more freedom to application designers but with the drawback of making their work more complex and expensive. Indeed, when managing tasks and data placement, one has to account for several complex trade-offs between memory performance, size and features. This thesis has been supervised between Atos Bull Technologies and Inria Bordeaux – Sud-Ouest. In the hereby document, we detail contemporary HPC systems and characterize machines performance for several locality scenarios. We explain how the programming language semantics affects data locality in the hardware, and thus applications performance. Through a joint work with the INESC-ID laboratory in Lisbon, we propose an insightful extension to the famous Roofline performance model in order to provide locality hints and improve applications performance. We also present a modeling framework to map platform and application performance events to the hardware topology, in order to extract synthetic locality metrics. Finally, we propose an automatic locality policy selector, on top of machine learning algorithms, to easily improve applications tasks and data placement., La hiérarchie mémoire des serveurs de calcul est de plus en plus complexe. Les machines disposent de plusieurs niveaux de caches plus ou moins partagés et d’une mémoire distribuée. Plus récemment le paysage du Calcul Haute Performance (CHP) a vu apparaître des mémoires adressables embarquées dans le processeur ainsi que de nouvelles mémoires non-volatiles (périphérique mémoire sur le bus d’entrées sorties et prochainement de la mémoire non-volatile directement sur le bus mémoire). Cette hiérarchie est nécessaire pour espérer obtenir de bonnes performances de calcul, au prix d’une gestion minutieuse du placement des données et des tâches de calcul. Là où la gestion des caches était entièrement matérielle et masquée au développeur, le choix du placement des données dans telle ou telle zone de mémoire, plus ou moins rapide, volatile ou non, volumineuse ou non, est maintenant paramétrable logiciellement. Cette nouvelle flexibilité donne une grande liberté aux développeurs mais elle complexifie surtout leur travail quand il s’agit de choisir les stratégies d’allocation, de communication, de placement, etc. En effet, les caractéristiques des nombreux niveaux de hiérarchie impliqués varient significativement en vitesse, taille et fonctionnalités. Dans cette thèse, co-encadrée entre Atos Bull Technologies et Inria Bordeaux– Sud-Ouest, nous détaillons la structure des plates-formes contemporaines et caractérisons la performance des accès à la mémoire selon plusieurs scénarios de localité des tâches de calcul et des données accédées. Nous expliquons comment la sémantique du langage de programmation impacte la localité des données dans la machine et donc la performance des applications. En collaboration avec le laboratoire INESC-ID de Lisbonne, nous proposons une extension au célèbre modèle Roofline pour exposer de manière intelligible les compromis de performance et de localité aux développeurs d’applications. Nous proposons par ailleurs un outil de synthèse de métriques de localité mettant en lien les évènements de performance de l’application et de la machine avec la topologie de cette dernière. Enfin, nous proposons une approche statistique pour sélectionner automatiquement la meilleure politique de placement des tâches de calcul sur les coeurs de la machine et des données sur les mémoires.
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