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Pipe design in 3D is typically characterized by competing objectives, since the different design objectives, such as the reduction of length, weight, number of bends, manufacturing cost, and overall angle sum, are examples for such competing design goals, where one goal is often at the expense of the other. The origin of these competing design goals lies in the highly coupled problems of finding a permissible and collision-free pipe path in a complex 3D geometry and the physical properties of the path found. Because of the complex physics and geometry, these couplings are highly non-linear and mostly accessible via simulation only. The underlying pipe design optimization problem can thus not be solved explicitly and is tackled instead with a multi-disciplinary search procedure. Since the trade-offs between different competing evaluation objectives are often not known in advance, an automated design space exploration can be performed to generate different pipe designs, leading to well-informed design decisions by human experts. Such a design space exploration is shown and discussed using the pipework in a mounting rack in an Airbus A320 main landing gear bay. A total of 144 valid designs are generated, out of which the best in each criteria and the pareto-optimal solutions are automatically selected. Compared to the manually created Airbus A320 series solution, up to |$10.4\%$| of the pipe length or up to |$16.9\%$| of the bends can be saved using the same fixings and connection points, demonstrating both the feasibility and the industrial applicability of the automated toolchain. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Computer Engineering & Applications is the property of Beijing Journal of Computer Engineering & Applications Journal Co Ltd. and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Layout designs have a large number of design variables and various physical constraints. Conventional design exploration approaches are time-consuming and may require human intervention. A unique feature about physical layout designs is the availability of domain knowledge, which can be utilised to speed up the design process. In this paper, we propose a generative deep learning-based design space exploration (DSE) methodology that is capable of learning design constraints in the layout design without explicit supervision. Moreover, it can incorporate domain knowledge in the generated layouts, thereby speeding up the design process. This is realised by constructing a layout generation variational autoencoder (LGVAE) model, which uses a latent space as an interface to generate the layouts. By training the LGVAE model, significantly lower-dimensional representations can be learned compared to the original dimensionality of the design space. Therefore, the number of design variables is greatly reduced. We showcase the performance of the proposed DSE approach by solving the heat source layout design problem encountered in thermal management of chips. Experiments demonstrate that the LGVAE model is capable of generating compressed latent representations that capture the characteristics of the input samples, which makes the DSE cost-effective. [ABSTRACT FROM AUTHOR]

The emergence of data-intensive applications, such as Deep Neural Networks (DNN), exacerbates the well-known memory bottleneck in computer systems and demands early attention in the design flow. Electronic System-Level (ESL) design using SystemC Transaction Level Modeling (TLM) enables effective performance estimation, design space exploration (DSE), and gradual refinement. However, memory contention is often only detectable after detailed TLM-2.0 approximately-timed or cycle-accurate RTL models are developed. A memory bottleneck detected at such a late stage can severely limit the available design choices or even require costly redesign. In this work, we propose a novel TLM-2.0 loosely-timed contention-aware (LT-CA) modeling style that offers high-speed simulation close to traditional loosely-timed (LT) models, yet shows the same accuracy for memory contention as low-level approximately-timed (AT) models. Thus, our proposed LT-CA modeling breaks the speed/accuracy tradeoff between regular LT and AT models and offers fast and accurate observation and visualization of memory contention. Our extensible SystemC model generator automatically produces desired TLM-1 and TLM-2.0 models from a DNN architecture description for design space exploration focusing on memory contention. We demonstrate our approach with a real-world industry-strength DNN application, GoogLeNet. The experimental results show that the proposed LT-CA modeling is 46× faster in simulation than equivalent AT models with an average error of less than 1% in simulated time. Early detection of memory contentions also suggests that local memories close to computing cores can eliminate memory contention in such applications. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Computer Engineering & Applications is the property of Beijing Journal of Computer Engineering & Applications Journal Co Ltd. and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In wearable optical sensing applications whose target tissue is not superficial, such as deep tissue oximetry, the task of embedded system design has to strike a balance between two competing factors. On one hand, the sensing task is assisted by increasing the radiated energy into the body, which in turn, improves the signal-to-noise ratio (SNR) of the deep tissue at the sensor. On the other hand, patient safety consideration imposes a constraint on the amount of radiated energy into the body. In this paper, we study the trade-offs between the two factors by exploring the design space of the light source activation pulse. Furthermore, we propose BASS, an algorithm that leverages the activation pulse design space exploration, which further optimizes deep tissue SNR via spectral averaging, while ensuring the radiated energy into the body meets a safe upper bound. The effectiveness of the proposed technique is demonstrated via analytical derivations, simulations, and in vivo measurements in both pregnant sheep models and human subjects.

Design ideation activities that involve the manipulation of geometry rely heavily on manual input. For feasibility reasons, the generation of design alternatives must often be limited, particularly when these alternatives need to be prototyped and tested. This paper describes a conceptual design strategy that leverages variational three-dimensional geometry to automatically generate a large number of design alternatives from a template model and their corresponding physical prototypes for evaluation and testing. In our approach, 3D geometric variations are produced automatically from a single design concept modeled parametrically, which are then used to generate 3D-printable files. Our method is suitable for design scenarios where real-world testing is preferred over virtual simulation and requires designers to consider a concept idea as a family of solutions, instead of a single design option. Our strategy enables an effective exploration of conceptual design spaces in highly constrained situations and facilitates parallel prototyping, which is known to produce better results than serial prototyping. We demonstrate the feasibility and effectiveness of the proposed method through a case study that involves the design of an instrument for ophthalmic surgery for extracting an intraocular lens (IOL) from the eye. Using our approach, nine unique concept families comprising a total of 150 designs were rapidly and successfully prototyped and tested. [ABSTRACT FROM AUTHOR]

During the architectural design phase, the decisions made have a crucial impact on developing complex systems. These decisions often limit the performance bounds and steer subsequent research directions. However, the multitude of architectural components and intricate interrelationships cause component combination explosion. Additionally, the diverse requirements of different stakeholders add complexity to determining the weight of indicators, posing challenges to complex system architecture generation and trade-off. This paper proposes a method for exploring the architectural design space in complex systems realisation, which aims to resolve issues related to the formal representation of architectures, selection within the architectural design space, and trade-offs. Firstly, the architectural design space is represented by formulating and mathematically describing a morphological matrix. Then, the construction of the Constraint Satisfaction Problem model aims to achieve a reduction in the scale of the design space. Moreover, through the evolutionary algorithm, the Pareto front is identified. Weight sensitivity analysis and the improved Technique for Order Preference by Similarity to the Ideal Solution method are combined to assist designers in finding a satisfactory architecture from the design space with many combinations. Finally, the proposed method is verified by the design of the launch vehicle's primary and secondary separation system. [ABSTRACT FROM AUTHOR]

Design space exploration and margin analysis can inform critical decisions early in engineering design, helping to handle the uncertainties of early design while ensuring design performance. In practice, the complexity of many products makes such decision-making challenging. This paper addresses the challenge with a new design framework that relies on the margin value method to evaluate sets of concepts that are combinatorially generated from an enhanced function-means tree. The basis for concept comparison is the margin value in each design alternative. The margin value method is expanded to address a broad class of design problems by using surrogate models and novel metrics for evaluating different conceptual alternatives. Visualization tools are introduced to support the evaluations. The efficacy of the framework is demonstrated using the design of a structural aero-engine component involving simulation models and uncertain load specifications. Overall, this paper shows how design concepts can be compared objectively and distilled to a set of alternatives that would retain their values throughout product development. [ABSTRACT FROM AUTHOR]

Composite curing through infrared radiation (IR) has become a popular autoclave alternative due to lower energy costs and short curing cycles. As such, understanding and measuring the effect of all parameters involved in the process can aid in selecting the proper constituents as well as curing cycles to produce parts with a high degree of cure and low curing time. In this work, a numerical model that takes inputs such as part geometry, material properties, curing-related properties and applied curing cycle is created. Its outputs include the degree of cure, maximum curing temperature and total curing time. A genetic algorithm and a design of experiments (DOE) sequence cover the range of each input variable and multiple designs are evaluated. Correlations are examined and factor analysis on each output is performed, indicating that the most important inputs are activation energy, specimen precuring, applied curing temperature and curing duration, while all the others can be considered constant. Finally, response surfaces are created in order to effectively map and provide estimations of the design space, resulting in a curing cycle optimizer given certain restrictions over the input parameters.

We present a systematic MEMS structural design approach via a "trial-and-error"learning process by using the deep reinforcement learning framework. This scheme incorporates the feedback from each "trial"to obtain sophisticated strategies for MEMS design optimizations. Disk-shaped MEMS resonators are selected as case studies and three remarkable advancements have been realized: 1) accurate overall performance predictions (97.9%) via supervised learning models; 2) efficient MEMS structural optimizations to guarantee targeted structural properties with an excellent generation accuracy of 97.7%; and 3) superior design explorations to achieve one order of magnitude performance enhancement than the training dataset. As such, the proposed scheme could facilitate a wide spectrum of MEMS applications with this data-driven inverse design methodology.

During preliminary phases in product design, on the basis of strong physical hypotheses (e.g. isotherm, steady state), physical and functional requirements can be expressed as coarse-grained constraint-based models on a few degrees of freedom, possibly including several design criteria to optimize. Such models are usually handled by multi-objective optimization solvers in order to find design solutions giving the best trade-offs between design criteria. Another approach developed in this paper is to partially explore all the areas of the design space using an anytime interval branch-and-prune algorithm called IDFS such that the design criteria are converted into so-called ε -constraints. The expected result is a sample of solutions diversified in both the objective space and the design space. Several quality indicators are introduced in order to measure this diversity and compare IDFS with two state-of-the-art multi-objective optimization solvers NSGA-II and NSGA-III on three real-world case studies. The results show that IDFS is able to identify new close-to-optimal designs and permits a better understanding of the design space. This framework provides a promising alternative tool for decision making, in particular for integrating interaction in the preliminary design process. Partial exploration aims to compute a diversified subset of feasible solutions; We built an anytime branch and prune algorithm for partial design space exploration. We built a protocol to analyze diversity in both the design and the objective space. We compare partial exploration and optimization approaches on three design problems. Partial Exploration is a tool for decision makers to identify quasi-optimal designs. [ABSTRACT FROM AUTHOR]

One of today's main concerns is to bring artificial intelligence capabilities to embedded systems for edge applications. The hardware resources and power consumption required by state-of-the-art models are incompatible with the constrained environments observed in edge systems, such as IoT nodes and wearable devices. Spiking Neural Networks (SNNs) can represent a solution in this sense: inspired by neuroscience, they reach unparalleled power and resource efficiency when run on dedicated hardware accelerators. However, when designing such accelerators, the amount of choices that can be taken is huge. This paper presents SpikExplorer, a modular and flexible Python tool for hardware-oriented Automatic Design Space Exploration to automate the configuration of FPGA accelerators for SNNs. SpikExplorer enables hardware-centric multiobjective optimization, supporting target factors such as accuracy, area, latency, power, and various combinations during the exploration process. The tool searches the optimal network architecture, neuron model, and internal and training parameters leveraging Bayesian optimization, trying to reach the desired constraints imposed by the user. It allows for a straightforward network configuration, providing the full set of explored points for the user to pick the trade-off that best fits their needs. The potential of SpikExplorer is showcased using three benchmark datasets. It reaches 95.8% accuracy on the MNIST dataset, with a power consumption of 180 mW/image and a latency of 0.12 ms/image, making it a powerful tool for automatically optimizing SNNs. [ABSTRACT FROM AUTHOR]

Convolutional neural networks (CNNs) have significantly advanced various fields; however, their computational demands and power consumption have escalated, posing challenges for deployment in low-power scenarios. To address this issue and facilitate the application of CNNs in power constrained environments, the development of dedicated CNN accelerators is crucial. Prior research has predominantly concentrated on developing low precision CNN accelerators using code generated from high-level synthesis (HLS) tools. Unfortunately, these approaches often fail to efficiently utilize the computational resources of field-programmable gate arrays (FPGAs) and do not extend well to full precision scenarios. To overcome these limitations, we integrate vector dot products to unify the convolution and fully connected layers. By treating the row vector of input feature maps as the fundamental processing unit, we balance processing latency and resource consumption while eliminating data rearrangement time. Furthermore, an accurate design space exploration (DSE) model is established to identify the optimal design points for each CNN layer, and dynamic partial reconfiguration is employed to maximize each layer's access to computational resources. Our approach is validated through the implementation of AlexNet and VGG16 on 7A100T and ZU15EG platforms, respectively. We achieve an average convolutional layer throughput of 28.985 GOP/s and 246.711 GOP/s for full precision. Notably, the proposed accelerator demonstrates remarkable power efficiency, with a maximum improvement of 23.989 and 15.376 times compared to current state-of-the-art FPGA implementations. [ABSTRACT FROM AUTHOR]

Deep Neural Networks (DNN) have made significant advances in various fields including speech recognition and image processing. Typically, modern DNNs are both compute and memory intensive, therefore their deployment in low-end devices is a challenging task. A well-known technique to address this problem is Low-Rank Factorization (LRF), where a weight tensor is approximated by one or more lower-rank tensors, reducing both the memory size and the number of executed tensor operations. However, the employment of LRF is a multi-parametric optimization process involving a huge design space where different design points represent different solutions trading-off the number of FLOPs, the memory size, and the prediction accuracy of the DNN models. As a result, extracting an efficient solution is a complex and time-consuming process. In this work, a new methodology is presented that formulates the LRF problem as a (FLOPs vs. memory vs. prediction accuracy) Design Space Exploration (DSE) problem. Then, the DSE space is drastically pruned by removing inefficient solutions. Our experimental results prove that the design space can be efficiently pruned, therefore extract only a limited set of solutions with improved accuracy, memory, and FLOPs compared to the original (non-factorized) model. Our methodology has been developed as a stand-alone, parameterized module integrated into T3F library of TensorFlow 2.X. [ABSTRACT FROM AUTHOR]

Nowadays, product development is challenged by increasing system complexity and stringent time-to-market. To handle the demanding market requirements, knowledge from prior product generations is used to derive new, but partially similar product versions. The concept of product generation engineering, hence, allows manufacturers to release high-quality products within short development times. Therefore, in this paper, we propose a novel approach to evaluate the similarity of two product implementations based on the concept of the Hamming distance. This allows the usage of similarity information in various heuristics as well as in strategies and thus, to improve the product design process. In a wide set of cases, we investigate the quality and similarity of design points. In the experiments, the use of strategies leads to significantly short searching times, but also tends to be too restrictive in certain cases. Simultaneously, the quality of the solutions found in the heuristic design space exploration has been shown to be as good or better than for the search from scratch and considerably closer solutions as part of the non-dominated solution front have been found. [ABSTRACT FROM AUTHOR]

When designing a system at the Electronic System Level (ESL), designers are confronted with a very large number of design decisions, each affecting the characteristics of the resulting system. Simultaneously, the demands for the system's performance, reliability, and energy consumption have increased drastically. Design Space Exploration (DSE) aims to facilitate this complex task by automating the system synthesis and traversing the design space autonomously. Previous studies on DSE have mainly considered fixed architectures with a fixed set of hardware components only. In the paper at hand, we overcome this limitation to allow for a higher degree of freedom in the design of a multiprocessor system. Instead of a fixed architecture as input, we are using a resource library containing resource types whose instances can then be arbitrarily placed and connected. More specifically, we enable the exploration of the types, the number, and the positions of required processing-type instances in a grid-based topology template in addition to deciding on the remaining system synthesis tasks, namely, resource allocation, task binding, routing, and scheduling. We provide an extensible framework, based on Answer Set Programming (ASP) modulo Theories (ASPmT), for generating system architectures fulfilling predefined constraints. Our studies show that this higher degree of freedom, originating from fewer restrictions regarding the architecture, leads to an increased complexity of the problem. In extensive experiments, we show scalability trends for a set of parameters, demonstrating the capabilities and limits of our approach. [ABSTRACT FROM AUTHOR]

The surrogate model is an essential part of modern design optimization and exploration. In some cases, exploration of design space in multi-objective problems is important to reveal useful design insight and guidelines that will be useful for engineers. However, most surrogate models are black boxes, making interpretation difficult. This paper investigates the framework of explainable surrogate models using Shapley Additive Explanations (SHAP) to gain important design insight that helps users better understand the relationship between objective functions and design variables. We applied the explainable surrogate model framework to multi-objective design problems and performed a comparison with active subspaces and Sobol indices. Several techniques to extract design insight based on SHAP values are discussed: the averaged SHAP, the SHAP summary plot, the single- and bi-objective SHAP dependence plot, and the SHAP correlation matrix. Two aerodynamic design cases are selected to demonstrate the capability of explainable surrogate models: nine-variable inviscid and twenty-variable viscous transonic airfoil design. The findings indicate that SHAP provides more valuable insights than active subspaces and Sobol indices, particularly regarding the impact of individual design variables on the objectives. Consequently, SHAP can be employed in conjunction with active subspaces and Sobol indices to explore the input–output relationship in multi-objective design exploration comprehensively. [ABSTRACT FROM AUTHOR]

Composite curing through infrared radiation (IR) has become a popular autoclave alternative due to lower energy costs and short curing cycles. As such, understanding and measuring the effect of all parameters involved in the process can aid in selecting the proper constituents as well as curing cycles to produce parts with a high degree of cure and low curing time. In this work, a numerical model that takes inputs such as part geometry, material properties, curing-related properties and applied curing cycle is created. Its outputs include the degree of cure, maximum curing temperature and total curing time. A genetic algorithm and a design of experiments (DOE) sequence cover the range of each input variable and multiple designs are evaluated. Correlations are examined and factor analysis on each output is performed, indicating that the most important inputs are activation energy, specimen precuring, applied curing temperature and curing duration, while all the others can be considered constant. Finally, response surfaces are created in order to effectively map and provide estimations of the design space, resulting in a curing cycle optimizer given certain restrictions over the input parameters. [ABSTRACT FROM AUTHOR]

A cooperative intelligent transport system (C-ITS) enables information sharing among ITS subsystems, such as vehicle and roadside infrastructure, with vehicle-to-everything (V2X) communications. Novel C-ITS applications aim to reduce traffic congestion and improve road safety. For example, a roadside unit (RSU) can sense the traffic status of an intersection and share the information to nearby vehicles to prevent potential collision, i.e., the intersection movement assist (IMA) scenario. Typically, C-ITS applications are developed in a simulated world to mitigate the high costs and safety hazards associated with the real-world counterpart. Unfortunately, existing simulation tools focus primarily on modeling vehicle-to-vehicle (V2V) communications, rather than the vehicle-to-infrastructure (V2I) communications involved in the above example. This poses a great challenge for developing V2I-based applications, especially for the application-level performance assessment on such systems. This work proposes a software framework that enables the simulation of full software stacks for the ITS subsystems, i.e., vehicle and RSU. This full-stack simulation capability enables hardware-in-the-loop simulations, evaluating the application-level performance and relative cost in the early stage of system development. This can shorten the time to market for C-ITS applications. We believe that this framework paves the way toward the development of novel V2I applications.

Contemporary smartphones integrate dedicated AI accelerators alongside CPUs and GPUs, in response to the growing demand for deep learning applications. While existing software development kits (SDKs) for these devices provide neural network optimization techniques, they often lack system-level optimizations, specifically in distributing layers across heterogeneous processors. This paper introduces a novel approach to enhance the throughput of deep learning applications through the utilization of quantization and pipelining techniques. The proposed technique employs different quantization schemes for activation data and filter weights to minimize accuracy drop. A genetic algorithm is employed to explore the extensive design space of layer-wise mapping and pipelining, aiming to find the best pipelining solution. To estimate performance of each solution candidate, the actual execution time of the application on the device is measured, accounting for unique smartphone characteristics, such as dynamic voltage and frequency scaling (DVFS) and OS scheduling. The impact of thermal throttling on throughput is also investigated by running benchmark applications continuously for 10 minutes. Our technique is validated through experiments conducted on Google Pixel 6 and Samsung Galaxy S22. Throughput enhancements, ranging from $\times 5.4$ to $\times 7.6$ on Google Pixel 6 and $\times 35.5$ to $\times 44.2$ on Samsung Galaxy S22, are achieved, compared to single-processor mappings for networks with floating-point parameters. It confirms that significant performance improvements can be achieved through the proposed software optimization methodology on contemporary smartphones with diverse constraints at the user level.

This paper proposes a Design Space Exploration for Edge machine learning through the utilization of the novel MathWorks FPGA Deep Learning Processor IP, featured in the HDL Deep Learning toolbox. With the ever-increasing demand for real-time machine learning applications, there is a critical need for efficient and low-latency hardware solutions that can operate at the edge of the network, in close proximity to the data source. The HDL Deep Learning toolbox provides a flexible and customizable platform for deploying deep learning models on FPGAs, enabling effective inference acceleration for embedded IoT applications. In this study, our primary focus lies in investigating the impact of parallel processing elements on the performance and resource utilization of the FPGA-based processor. By analyzing the trade-offs between accuracy, speed, energy efficiency, and hardware resource utilization, we aim to gain valuable insights into making optimal design choices for FPGA-based implementations. Our evaluation is conducted on the AMD-Xilinx ZC706 development board, which serves as the target device for our experiments. We consider all the compatible Convolutional Neural Networks available within the HDL Deep Learning toolbox to comprehensively assess the performances.

The poultry processing industry struggles to keep up with new developments in meat consumption and livestock breeding. Designing poultry processing systems is becoming increasingly more complex, and an increasing number of iterations of (re)design are required to optimize the product flow in these systems. To address this issue, this study presents a discrete-event simulation-based method for design space exploration of production systems. This method is mostly automated, greatly reducing the time and effort required in the design process. The steps that are automated are iterating on the design, model construction, performing simulation experiments, and interpreting the simulation results. An industrial case study in which a poultry processing system is redesigned is used to validate the effectiveness of the proposed method. A detailed description of this case study is given to showcase the different ways in which this design space exploration method can be used. [ABSTRACT FROM AUTHOR]

Design space exploration (DSE) is an elegant way to tackle the ever‐growing design complexity of automotive Electrical/Electronic (E/E) architectures. In this paper, a toolchain extension is presented and discussed. While still under development, it enhances the modeling with a graphical canvas and allows the model to be defined more naturally, and agnostically before being attached to the rest of the toolchain. It is, then, that more heavy‐duty simulation frameworks such as Metropolis are put to use to perform guided design space exploration and converge toward an optimum. We validated the extended toolchain with a proof of concept use case being challenged by the addition of a third camera, and the way the existing two‐frontal cameras subsystem could be adjusted to fit it best. It is intended for this modeling toolchain to be reusable on a larger range of design use‐cases. [ABSTRACT FROM AUTHOR]

We demonstrate a design scheme for weakly coupled resonators (WCRs) by integrating the supervised learning (SL) with the genetic algorithm (GA). In this work, three distinctive achievements have been accomplished: 1) the precise prediction of coupling characteristics of WCRs with an accuracy of 98.7% via SL; 2) the stepwise evolutionary optimization of WCR geometries while maintaining their geometric connectivity via GA; and 3) the highly efficient generation of WCR designs with a mean coupling factor down to 0.0056, which outperforms 98% of random designs. The coupling behavior analysis and prediction are validated with experimental data of coupled microcantilevers from a published work. As such, this newly proposed scheme could shed light upon the structural optimization methods for high-performance MEMS devices with high degree of design freedom.