125 results on '"Devgan, Anirudh"'
Search Results
2. Closed-form delay and slew metrics made easy
3. Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees
4. Buffer insertion for noise and delay optimization
5. Transient simulation of integrated circuits in the charge-voltage plane
6. Adaptively controlled explicit simulation
7. Accelerated design of analog, mixed-signal circuits in Titan
8. Accelerated design of analog, mixed-signal circuits with fineSim™ and titan™
9. Reinventing EDA with manycore processors
10. A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits
11. Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce
12. Robust analytical gate delay modeling for low voltage circuits
13. Leakage and Leakage Sensitivity Computation for Combinational Circuits
14. Variability modeling and variability-aware design in deep submicron integrated circuits
15. Sleep transistor sizing using timing criticality and temporal currents
16. Spatially distributed 3D circuit models
17. Power grid voltage integrity verification
18. Leakage power
19. An efficient algorithm for statistical minimization of total power under timing yield constraints
20. Session details: Noise-tolerant design and analysis techniques
21. Parametric yield estimation considering leakage variability
22. Session details: Statistical timing analysis
23. Delay and slew metrics using the lognormal distribution
24. Closed form expressions for extending step delay and slew metrics to ramp inputs
25. Full chip leakage estimation considering power supply and temperature variations
26. Leakage and leakage sensitivity computation for combinational circuits
27. Efficient techniques for gate leakage estimation
28. Robust analytical gate delay modeling for low voltage circuits.
29. PERI
30. Power grid voltage integrity verification.
31. An efficient algorithm for statistical minimization of total power under timing yield constraints.
32. Spatially distributed 3D circuit models.
33. Sleep transistor sizing using timing criticality and temporal currents.
34. Achieving continuous VT performance in a dual VT process.
35. Parametric yield estimation considering leakage variability.
36. RC delay metrics for performance optimization
37. Interconnect synthesis without wire tapering
38. Delay and slew metrics using the lognormal distribution.
39. PERI.
40. KSim
41. KSim.
42. Efficient Coupled Noise Estimation for On-Chip Interconnects.
43. How to Efficiently Capture On-Chip Inductance Effects: Introducing a New Circuit Element K.
44. How to efficiently capture on-chip inductance effects.
45. An "effective" capacitance based delay metric for RC interconnect.
46. A two moment RC delay metric for performance optimization.
47. Transient sensitivity computation in controlled explicit piecewise linear simulation
48. Buffer insertion with accurate gate and interconnect delay computation
49. Buffer insertion for noise and delay optimization
50. Simulation of coupling capacitances using matrix partitioning
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.