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BACKGROUND: Residual peri-device leakage (PDL) is frequent after left atrial appendage occlusion (LAAO). Little is known about management strategies, procedural aspects and outcomes of interventional PDL closure.AIMS: The aim of this study was to assess the safety and feasibility of PDL closure after LAAO.METHODS: Fifteen centres contributed data on baseline characteristics, in-hospital and follow-up outcomes of patients who underwent PDL closure after LAAO. Outcomes of interest included acute success and complication rates and long-term efficacy of the procedure.RESULTS: A total of 95 patients were included and a cumulative number of 104 leaks were closed. The majority of PDLs were detected within 90 days (range 41-231). Detachable coils were the most frequent approach (42.3%), followed by the use of the AMPLATZER Vascular Plug II (29.8%) and the AMPLATZER Duct Occluder II (17.3%). Technical success was 100% with 94.2% of devices placed successfully within the first attempt. There were no major complications requiring surgical or transcatheter interventions. During follow-up (96 days [range 49-526]), persistent leaks were found in 18 patients (18.9%), yielding a functional success rate of 82.7%, although PDLs were significantly reduced in size (pre-leak sizemax: 6.1±3.6 mm vs post-leak sizemax: 2.5±1.3 mm, p5 mm. Major adverse events during follow-up occurred in 5 patients (2 ischaemic strokes, 2 intracranial haemorrhages, and 1 major gastrointestinal bleeding).CONCLUSIONS: Several interventional techniques have become available to achieve PDL closure. They are associated with high technical and functional success and low complication rates.

Embolic protection devices were developed to reduce the risk of stroke during carotid artery stenting. The aim of this study was to test the capture efficiency of five embolic protection devices under reproducible in vitro conditions. The setup consisted of silicone tubes representing the vessel modeling round and oval cross sections. Spherical polystyrene particles (150 μm, COOH-coating) were used to simulate the plaque. The particles were inserted in a clean water circuit and either captured by the device or collected in a glass filter. The missed particles were counted by laser obscuration as a measure of device leakage. The systems Angioguard RX, RX Accunet, FiberNet, FilterWire EZ and EmboshieldNAV were analyzed. At the round cross section, FilterWire EZ demonstrated the highest capture efficiency (0% of missed particles) and RX Accunet the lowest, at 34%. The amount of leaked particles increased to 22% for FilterWire EZ and 89% for Angioguard RX during the test with the oval cross profile.

Background Oral anticoagulation for prophylaxis of central and peripheral embolisation is limited in its use in patients with atrial fibrillation (AF) and bleeding events. As an alternative to anticoagulation, the interventional closure of the left atrial appendage (LAAO) is available. A common clinical dilemma is the treatment of patients with potential peri-device leakage following LAA occlusion. The specific definition of the severity of the leak and the long-term clinical implications have not yet been sufficiently investigated. Methods The multi-centre ORIGINAL registry was initiated 2014. The aim of this registry is to analyze the safety and efficacy of the procedure in patients with a high risk of bleeding in everyday clinical practice and to evaluate hemorrhagic and thromboemb. events in the long term follow-up. Patients with an indication for LAA occl. were included in the registry after informed consent. The impl., follow-up and anticoagulation regimens are performed according to the standard of the participating centers. 521 patients with AF underwent an implantation of an LAA closure device between Jul. 2014 and Nov. 2018. A mean follow-up of 463 days could be reached in 386 patients. Results The periprocedural complication rate was 3.8% of which 5 patients experienced pericardial effusion (successful treatment with pericardial puncture or surgical), 2 patients had periprocedural stroke and 1 patient suffered from air embolism. In 27 patients a peri-device flow due to incomplete occlusion was detected by TEE (5.4% of the implantations). The size ranged between 1 and 8 mm (mean 2.28 mm (SD=2.11)). The eccentricity index (EI) of the LAA in these patients was 1.22 (SD 0.17), and thus the LAA rather oval, while those LAA without leakage tend to be more circular (EI 1.08 with SD=0.17). 2 of the patients with leakage (7.4%) experienced stroke or peripheral embolism, respectively. The annual risk for stroke/TIA/peripheral embolism of these patients was 5.84%, the annual risk of the patients without leakage was 2.04%. Patients with a leakage >6 mm were treated with rivaroxaban in full therapeutic dosage. One patient underwent an additional procedure. Conclusion The evaluation and management of para-device leakage after an interventional LAA occlusion represents a challenge. Currently, limited data are available on the optimal strategy. Those data indicate that residual peri-device flow into the LAA after percutaneous closure with the Watchman device represents no cause for alarm. However, our data suggest, that patients with peridevice leak might be at a higher risk of thromboembolic events. Furthermore, it could be shown, that these patients had rather oval ostium of the LAA, while those LAA without leakage tend to be more circular. This implicates the importance of advanced imaging methods, such as 3D-TEE, which are capable to precisely determine the size of the LAA and the degree of its circularity. Acknowledgement/Funding None

The introduction of automated process inspection (API) system using in-line SEMVision was applied to monitor the contact process of the inter layer dielectric (ILD). The conventional optical inspection systems do not have enough resolution to monitor ILD contact etching when the technology has scaled down to the deep submicron node from the submicron. In semiconductor process, the contact process of the ILD is one of the most critical processes. Usually, in-line E-beam system is used in monitoring the contact process or to detect device leakage. The Off-line uses TEM to check contact etching with a physical failure analysis [1]. Low throughput is the main disadvantage in both E-beam and TEM inspections, especially the physical analysis of TEM, which needs more than 2~3 days due to the complex sample preparation. In order to shorten the inspection time of the E-beam, we developed a novel mode of a rapid auto process inspection system using inline SEMVision, this can effectively detect contact processing issues.

This paper explores the 30nm channel length tri-layered strained channel Heterostructure on Insulator (HOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The effects of strained Silicon-Germanium thickness on the device leakage current have been analyzed and optimized using Synopsis TCAD simulations. The enriched device characteristics for the scaled 30nm device have also been examined in comparison to 40nm and 50nm channel length device MOSFET.

The integration of porous membranes with microfluidic devices allows a simple but high-throughput mass transport control for numerous microfluidic applications, such as single-cell separation, sample analysis, and purification. In this study, we demonstrate a novel integration process of porous membranes into microfluidic devices by applying a magnetic field and hydrodynamically stabilizing them. This new approach simplifies the integration process by removing physicochemical bonding between membranes and microfluidic devices, but overcomes many practical issues observed in current methods, such as device leakage, membrane replacement, and membrane material selection. More importantly, our approach allows us to install membranes with diverse physicochemical features and spatial configurations into a single microfluidic device. This additional ability can significantly improve its performance and capability in applications. Finally, we successfully demonstrate the utilization of our membrane device for simple particle separation.

This paper introduces the role of axial flow fan with adjustable movable vane, aiming at complicated structure, difficult regulation and hydraulic device leakage of hydraulic movable vane regulation device, designs a new kind of movable vane regulation system-electronically controlled movable vane regulation system, describes the composition and working principle of electronically controlled movable vane regulation system, and emphasizes on structure features of control system, reducing mechanism and impeller assembly.

A new metric is proposed to solely evaluate the performance gap of digital ring oscillators between silicon and model specifications. It separates the impact of device leakage from the traditional static current versus RO frequency. When using together, these two metrics can identify the sources of silicon gap and guide process improvement in the fab.

Adopting coupling drain bias stresses to probe the device integrity achieved the good consequences in the study of device leakage, interface state, and oxide trap causing some degradation effect in the tested devices and observed the GCIP effect at the higher drain stress conditions. Keywords-impact ionization; leakage; DIBL; MOSFET; drain; trap; GCIP effect; high-k

Background After left atrial appendage (LAA) device closure, peri-device leakage into the LAA persists due to incomplete occlusion. We hypothesized that pre-procedural three-dimensional (3D) geometric analysis of the interatrial septum (IAS) and LAA orifice can predict this leakage. We investigated the predictive parameters of LAA device closure obtained from baseline cardiac computerized tomography (CT) using a novel 3D analysis system. Methods We conducted a retrospective study of 22 patients who underwent LAA device closure. We defined peri-device leakage as the presence of a Doppler signal inside the LAA after device deployment (group 2, n = 5) compared with patients without peri-device leakage (group 1, n = 17). Conventional parameters were measured by cardiac CT. Angles θ and φ were defined between the IAS plane and the line, linking the LAA orifice center and foramen ovale. Results Group 2 exhibited significantly better left atrial (LA) function than group 1 (p = 0.031). Pre-procedural θ was also larger in this group (41.9° vs. 52.3°, p = 0.019). The LAA cauliflower-type morphology was more common in group 2. Overall, the patients' LA reserve significantly decreased after the procedure (21.7 mm(3) vs. 17.8 mm(3), p = 0.035). However, we observed no significant interval changes in pre- and post-procedural values of θ and φ in either group (all p > 0.05). Conclusion Angles between the IAS and LAA orifice might be a novel anatomical parameter for predicting peri-device leakage after LAA device closure. In addition, 3D CT analysis of the LA and LAA orifice could be used to identify clinically favorable candidates for LAA device closure.

The formation processes for nickel silicide are assessed to determine limitations of using the silicide for sub-65 nanometer technologies. Various aspects of the NiSi formation process are described and addressed by using a two-step process sequence for annealing. This study focused on developing a process with three principal steps to achieve low resistivity NiSi films utilizing a low temperature isothermal cavity based furnace. Process parameters for a low resistivity NiSi film were determined for a two-step annealing sequence to enhance device electrical characteristics. Optimization of the initial anneal, combined with a second higher temperature stabilization anneal, reduced defect levels resulting in reduced device leakage.

Electroluminescence devices that use Si/Ge multilayer quantum dots as emission material emitting at 1.3 and 1.5 μm are reported in this paper. The Si/Ge quantum dots were made by commercial ultra-high vacuum chemical vapor deposition techniques at 600 °C. The photoluminescence spectrum shows a 1.55 μm emission peak at room temperature. Low and high temperature (710 °C) oxides are used as passivation layers for the mesa surface. The high temperature oxidized samples exhibit low device leakage currents and a 2×10 −7 external quantum efficiency at room temperature. However, the high temperature process causes Si and Ge to inter-diffuse and makes the emission shift to 1.3 μm. The low temperature oxidation results in large device leakage current and lower emission intensity but leaves the emission peak at 1.5 μm.

Multiple-gate FETs such as FinFETs would be adopted at the 22nm technology generation and beyond, owing to the better control of short-channel effects (SCEs) in high-volume manufacturing. In this paper, we present a novel implantation mode called “FlexScan” that consists of a series of various rotated angles. We perform the implant with FlexScan mode by Monte-Carlo simulation. FlexScan shows more conformal doping distribution in the fin structure. We expect that it could reduce device leakage and device variation caused from random doping distribution. The FlexScan mode could be used for 3D device doping process needed conformal doping profile.

In this study, we define and investigate the maximum power handling capability (Pmax) in an SOI RF shunt branch switch. One of the critical factor in the Pmax is the non-uniform voltage division across an OFF shunt branch. In this study we provide a simple analytical method to determine the stack voltage imbalance. The Pmax is characterized as a function of various parameters, such as, switch stack height, channel length, Gate and Body bias, and process parameters. Overall, we find that the Pmax can be improved by reducing stack imbalance as well as device leakage currents, namely, GIDL.

An experimental characterization of new-generation normally-off vertical channel 1200 V SiC JFETs under unclamped repetitive stress (URS) is presented. The drain and gate leakage currents are monitored, and their time evolution is recorded. The degradation of the leakage characteristics has been compared with repeated short circuits tests, at the same stress energy, thus demonstrating that different mechanisms take place in these conditions. Furthermore, a post-failure analysis of the surface of the device by means of a optic microscope indicates that a termination weakness could be the major cause for the device leakage increment and consequent failure.

We show here for the first time that the band-to-band (B2B) leakage current of nanoscale p-n junctions has a significant statistical dispersion caused by the atomistic nature of both the n-type and the p-type doping. As a result, the B2B current displays a log-normal distribution, with a spread increasing with the scaling of the junction width. This spread may largely increase the average device leakage and, in turn, increase power dissipation in future technologies.

In this paper, the first class of low power current-based physically unclonable functions (PUFs) is introduced. The new PUF circuit is able to convert the analog variations present in device leakage currents to a unique digital quantity at high speed and low power. Robust digital responses are achieved with the new architecture in presence of fluctuations in operational conditions such as temperature and supply voltage. The experimental results suggest 3% response error rate under extreme temperature variations from −55°C to 125°C and 20% fluctuations in supply voltage. The PUF consumes 150 µWatt for a duration of 250 ps per each response bit (37.5 femto joules of energy per response bit).

Being successful in semiconductor manufacturing of sub 50nm devices requires controlling variability of device leakage. Full wafer monitoring is essential to provide significant data. The Device Leakage Scribe Characterization Vehicle (CV®) Test Chips presented here fit well within the scribe area constraints of product wafers. Their devices under test (DUT) are using product relevant layout pattern to support new product introduction. Those DUTs are passively connected into a Passive Leakage Array (PLA) to increase the signal to noise ratio of the device leakage measurements, which is essential to enable full wafer testing within existing test time restrictions on product wafers. Furthermore, the PLAs can be arranged inside a Multiplexed Leakage Array (MLA), which significantly increases the number of experiments within the precious scribe line area.

A test pattern for testing DRAM cell data retention that differs from conventional retention time tests is described. The test pattern is applicable to non-V/sub DD/ bit-line precharge designs, and is specifically designed to test for worst-case subthreshold leakage through the cell access device by holding bit lines in their latched position for extended periods. This action stresses the cell access devices with the worst-case V/sub DS/ across them. The reasons to perform this test on a DRAM are reviewed, its advantages over standard retention time tests are described, and its ability to differentiate access device leakage from isolation leakage is discussed. Measured results on a 1-Mb chip are shown, illustrating the test pattern's effectiveness in screening subthreshold leakage. >

To achieve the required drive performance for sub 32 nm technology nodes there is strong interest in exploring the use of Ge-based technologies. This paper reviews some important processing aspects from a defect control viewpoint. Attention is given to crystal growth, shallow junction formation and germanidation techniques, respectively. The main focus is on defect related aspects. The last section deals with the device performance and the impact of processing on device leakage current and low frequency noise behavior.

This paper reports an accurate method of measuring the anomalous leakage current in pass-gate MOSFET's unique to SOI devices. A high-speed measurement setup is used to provide experimental results, and to quantify the magnitude of leakage. Particularly, great care is taken to measure only the device leakage current and not the currents due to parasitic capacitances. Systematic influences of different factors such as temperature, bias, device history, and device structure on this leakage current are experimentally established,.

In this paper we demonstrate the transient behavior of off-state device leakage due to signal switching history in PD SOI devices. We address the leakage modeling for PD SOI circuits taking input switching history into account and demonstrate that the off-state power dissipation is a function of the device input duty cycle due to body voltage variations with switching history in SOI devices. We also demonstrate that the device off-state power dissipation can be 2.4 times higher than the power dissipation calculated with traditional steady state off-state device current.

The impact of device leakage on the operation of conventional static and dynamic digital circuits is presented. Particular focus is on signal integrity, performance degradation, and power dissipation. A first order estimation regarding the expected circuit and system performances for a technology from a leakage standpoint can be defined based on the developed results. Developing an early guidance and discrimination methodology for device design is another target. The ultimate limits for device leakage for any trade-offs among the signal integrity, performance degradation, and power dissipation, can be estimated for any given technology.

A speed related problem degraded the yield of a 0.65 /spl mu/m triple level metal device. Reducing the channel length was the most simple and cost effective approach to improve device speed. However, an overly aggressive downsized channel length could also cause device leakage. To determine the optimal channel length with adequate speed performance and without leakage, a series of experiments were run to establish a yield model as a function of channel length and device threshold voltage (Vt). The Vt was varied by adjusting the channel implant dose. Instead of using masks with different sizings, the channel length was varied by adjusting photo exposure time and lightly doped drain (LDD) implant dose. This approach greatly reduced the cost of experiments and shortened the learning cycle. A strong correlation was established by Analysis of Variances (ANOVA) between yield and p-channel transistor length. The range of operational channel length was defined, where higher channel length caused poor speed performance and lower channel length caused device leakage. An interim process with increased photo exposure time was implemented immediately to ensure die shipment quantity and delivery schedule. In parallel, the optimal mask sizing was determined and this mask regenerated such that the original photo exposure when used with this mask would re-center the process. The interim process was then eliminated to streamline manufacturability. The optimized process resulted in significant yield improvement. Strong partnerships were established among device engineering, process engineering, and manufacturing groups to achieve yield enhancement in a timely manner without compromising manufacturability and customer deliveries.

In this paper, an investigation of the DC characteristics of 0.25 micrometers indium-implanted MOSFETs concerning on indium implantation induced damages is presented. The experimental data indicates that the devices with indium-implanted channel tend to show increases in device leakage current, which could be attributed the indium implantation induced damages. The impact of the indium implantation on the degradation of device performance was investigated through detailed studies of device I-V characteristics, and the measurement results are found to correlate well with the variations in the process conditions. Our findings indicate that the elimination of the implantation-induced damages by post implantation annealing is particularly important for deep sub-micron MOSFETs using indium implantation.© (2000) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

A study on the generation of crystallographic defects during FET processing and the influence of such defects on device parameters is reported. Diagnostic X-ray charts are used to pinpoint the critical processing steps and the corresponding defects that influence device properties. This is done by comparing and correlating the X-ray topographs of every single device on a silicon wafer recorded after each processing step with the device leakage currents which are correlated with stacking faults in the device area. The stacking faults appear as “extra” diffraction spots in high resolution X-ray topographs and are clearly recognized even after metallization. Such diffraction spots are analyzed through electron microscopy as stacking faults. Finally, it is shown that such faults are generated during the oxidation process of the silicon wafer.

Providing sound countermeasures against passive side channel attacks has received large interest in open literature. The scheme proposed in (Ishai et al., 2003) secures a computation against a d-probing adversary splitting it into d+1 shares, albeit with a significant performance overhead (5× to 20×). We maintain that it is possible to apply such countermeasures only to a portion of the cipher implementation, retaining the same computational security, backing a widespread intuition present among practitioners. We provide the sketch of a computationally bound attacker model, adapted as an extension of the one in (Ishai et al., 2003), and detail the resistance metric employed to estimate the computational effort of such an attacker, under sensible assumptions on the characteristic of the device leakage (which is, to the current state of the art, still lacking a complete formalization).

Conditions for effective intrinsic gettering by oxide precipitate induced dislocations, which we suggest as an important mechanism in explaining device leakage limited yield enhancement due to oxygen in Czochralski‐grown Si wafers, are examined. The effectiveness of this mechanism is demonstrated.

To the Editor.—Mahieu et al1recently reported thatCandida albicanswas responsible for early deterioration of silicone voice prostheses used in a tracheoesophageal fistula for postlaryngectomy voice restoration. Fungal vegetations on the prosthesis prevented competent valve closure, causing aspiration. Prosthesis durability was reduced from an average of three months to just a few weeks. We have also identifiedCandidaon the esophageal surface of silicone voice prostheses used by a significant number of our patients. They report inability to remove these deposits by routine cleaning methods and device leakage after three to four weeks' use. In two patients selected for study,Candidadeposits embedded in the porous silicone surface appeared within a week of use, and proliferation interfered with valve function as early as 21 and 28 days, respectively. As an alternative to eradication ofCandidain the host, we suggest disinfecting the prosthesis with an antifungal agent