9 results on '"Dewolf, Tristan"'
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2. Nano-analytical investigation of the forming process in an HfO2-based resistive switching memory.
- Author
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Lefevre, Gauthier, Dewolf, Tristan, Guillaume, Nicolas, Blonkowski, Serge, Charpin-Nicolle, Christelle, Jalaguier, Eric, Nowak, Etienne, Bernier, Nicolas, Blomberg, Tom, Tuominen, Marko, Sprey, Hessel, Audoit, Guillaume, and Schamm-Chardon, Sylvie
- Subjects
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NONVOLATILE random-access memory , *RANDOM access memory , *DIELECTRIC breakdown , *NONVOLATILE memory , *COMPUTER storage devices , *TRANSMISSION electron microscopy , *SHAPE memory alloys - Abstract
Metal oxide-based resistive random access memory devices are highly attractive candidates for next-generation nonvolatile memories, but the resistive switching phenomena remain poorly understood. This article focuses on the microscopic understanding of the initial forming step, which is decisive for the switching process. The integrated resistive switching memory effect in Ti / Hf O 2 / TiWN metal insulator metal structures is studied. After forming, transmission electron microscopy investigations pointed out the presence of a funnel-shaped region, in the ON state of the cell, where slightly oxidized Ti (Ti Ox ) was present within Hf O 2 dielectric. Modeling of the measured ON state conductance of the cell with the semi-classical approximation is consistent with a conductive nanometric Ti Ox filament (or a sum of sub-nanometric Ti Ox filaments) present in the funnel-shaped region. The conductive area is likely formed by diffusion after the dielectric breakdown. [ABSTRACT FROM AUTHOR]
- Published
- 2021
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3. Overlay Diagnostics of Die-to-die Alignment on the Kulicke and Soffa LITEQ 500 Stepper
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Misat, Sylvain, primary, Loktev, Mikhail, additional, Schiedon, Ralph, additional, De Boeij, Jeroen, additional, van der Stam, Michiel, additional, Huang, Chia-Ching, additional, Sixt, Pierre, additional, Al Dujaili, Haidar, additional, Dewolf, Tristan, additional, Allouti, Nacima, additional, Pain, Laurent, additional, Vannuffel, Cyril, additional, Coudrain, Perceval, additional, and Garnier, Arnaud, additional
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- 2022
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4. Very Low Temperature Tensile and Selective Si:P Epitaxy for Advanced CMOS Devices
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Kanyandekwe, Joël, primary, Bauer, Matthias, additional, Marion, Tanguy, additional, Saidi, Lazhar, additional, Pin, Jean-Baptiste, additional, Bisserier, Jeremie, additional, Richy, Jérôme, additional, Gauthier, Nicolas, additional, Dezest, Pattamon, additional, Brunet, Laurent, additional, Lapras, Valérie, additional, Dewolf, Tristan, additional, Thomas, Shawn, additional, and Hartmann, Jean-Michel, additional
- Published
- 2022
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5. Die-to-die alignment for lithographic processing of reconstructed wafers
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Loktev, Mikhail, Misat, Sylvain, Schiedon, Ralph, de Boeij, Jeroen, van der Stam, Michiel, Sixt, Pierre, Al Dujaili, Haidar, Dewolf, Tristan, Allouti, Nacima, Pain, Laurent, Vannuffel, Cyril, Coudrain, Perceval, Garnier, Arnaud, Kulicke & Soffa Liteq BV (Hooge Zijde 32, 5626 DC Eindhoven), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Département Plate-Forme Technologique (DPFT), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Direction de Recherche Technologique (CEA) (DRT (CEA)), and IEEE
- Subjects
Lithography ,die-to-die ,RDL ,WLP ,LITEQ 500 ,alignment ,Overlay ,Fan-out ,[SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics - Abstract
International audience; In this work, we address one of the challenges of Fan-Out Wafer Level Packaging (FO-WLP), which is chip placement error, which occurs during the process of wafer reconstruction and molding. In a typical FO-WLP process, a wafer processed on a front-end tool is diced, and the dies are repositioned on a carrier with additional space created for fan-out structures. A dedicated alignment approach, which includes measurement of individual dies to adjust the settings per exposure, would result in a dramatic improvement of the overlay performance. This process further referred to as die-to-die alignment is generally known to have negative impact on throughput for IC manufacturers.The accuracy of die-to-die alignment on 200 mm wafers is evaluated experimentally in collaboration between Kulicke & Soffa and CEA LETI. The wafer layout consists of dies of different sizes (120 chips of 4 mm x 4 mm and 70 of 10 mm x 10 mm) for which intentional misalignments have been introduced with different amounts of translation (up to +/-50 micrometers) and rotation (up to +/-10 milliradians) in order to emulate typical errors found in reconstructed wafers.Alignment of the "back-end" layer with respect to existing patterns on the wafer was measured both at Kulicke & Soffa and at CEA LETI. Both measurements confirmed sub-micrometer accuracy of overlay between the structures on the reference wafer and the new layer exposed on LITEQ 500. Throughput in-line with current industrial standards was achieved. Data analysis shows that major improvements of the throughput can be achieved by optimizing the exposure process.
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- 2022
6. Advanced roughness characterization for 300mm Si photonics patterning and optimization
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Le Tiec, Remi, primary, Levi, Shimon, additional, Kravtsov, Angela, additional, Novak, Olga, additional, Dupre, Cecilia, additional, Vannuffel, Cyril, additional, Dewolf, Tristan, additional, Garcia, Stephanie, additional, Wilmart, Quentin, additional, and Faugier-Tovar, Jonathan, additional
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- 2021
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7. Nano-caractérisation des mécanismes de commutation dans les mémoires résistives à base d'HfO2
- Author
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Dewolf, Tristan, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Université Paul Sabatier - Toulouse III, Sylvie Schamm, Guillaume Audoit, and STAR, ABES
- Subjects
Resistives memories ,[SPI.ELEC]Engineering Sciences [physics]/Electromagnetism ,Ti migration ,EELS ,Oxygen vacancies ,[SPI.ELEC] Engineering Sciences [physics]/Electromagnetism ,Lacunes d'oxygène ,TEM ,OxRRAM ,Migration de Ti ,Mémoires résistives - Abstract
Digital technology is invading our day life and the amount of data is exploding. This implies to develop memories which perform better and better. This is a major issue in microelectronics. Among non-volatile memories, Oxide based resistive RAM are particularly attractive (compatible with CMOS technology, low programming voltage) and are considered as promising candidate for replacing FLASH memories. The stack is simple (M-I-M) and the switching is based on resistance changes under an applied electrical stress. If forming and breaking a nanometer-sized conductive area is commonly accepted as the physical phenomenon involved in the switching mechanism, a debate remains about the nature and the characteristics of the filamentary area (oxygen vacancies, metallic element). Based on transmission electron microscopy methods - STEM-HAADF and STEM-EELS - this thesis work provides, at the scale of the filament (nm), a further understanding about the physico-chemical modifications of the memory cell induced by the operating step (FORMING, RESET). The TiN/Ti/HfO2/TiN stack, processed with microelectronic techniques, was incorporated into different architectures (1R, 1T1R) with a shaped top electrode (diameter 50 to 200 nm) to confine the filament in a volume compatible with TEM and then biased with different methods (C-AFM, measuring bench, in-situ TEM). When thermal effects are under control, the analysis of the EELS elementary maps shows that titanium from the top electrode plays a role in the switching mechanism (local migration in the HfO2 layer) in addition to the oxygen depletion at the HfO2/bottom electrode interface and probably at grain boundaries in HfO2., Le numérique prend une place de plus en plus importante dans la vie de tous les jours et les quantités de données échangées explosent ce qui impose de développer des mémoires de plus en plus performantes, enjeu majeur du secteur de la microélectronique. Parmi les mémoires non-volatiles émergentes, les mémoires OxRRAM à base d'oxyde résistif sont particulièrement attrayantes et représentent un candidat potentiel au remplacement des mémoires FLASH (compatibles avec la technologie CMOS, faibles tensions de programmation). Leur structure est simple (Métal-Isolant-Métal) et leur fonctionnement est basé sur une commutation de résistance sous l'effet d'un champ électrique. Si le mécanisme de formation/dissolution d'un filament conducteur de taille nanométrique est reconnu par la communauté, un débat subsiste encore sur la nature et les caractéristiques du/des filaments dans le cas de l'oxyde HfO2 (lacunes d'oxygène, élément métallique). En nous appuyant sur des méthodes de la microscopie électronique en transmission - STEM-HAADF et STEM-EELS - cette thèse apporte des éléments de compréhension par rapport aux modifications d'état physico-chimique qui s'opèrent lors des différentes étapes du fonctionnement d'une mémoire (FORMING, RESET) et ceci à l'échelle nanométrique définie par la taille du filament conducteur. L'empilement TiN/Ti/HfO2/TiN, préparé selon les procédés de la microélectronique, a été intégré dans différentes architectures (1R, 1T1R) avec une électrode supérieure structurée (50 à 200 nm) pour confiner la zone de conduction dans un volume fini compatible avec la MET puis polarisé selon différentes méthodes (C-AFM, banc de mesure et TEM in-situ). Lorsque les effets thermiques sont contrôlés, l'analyse des cartographies chimiques élémentaires montre que le titane de l'électrode supérieure participe au mécanisme de commutation (migration localisée dans la couche HfO2) en plus de la déplétion en oxygène à l'interface HfO2/électrode inférieure et probablement aux joints de grains dans HfO2.
- Published
- 2018
8. Nano-characterization of switching mechanism in HfO2-based oxide resistive memories by TEM-EELS-EDS
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Dewolf, Tristan, primary, Delaye, Vincent, additional, Bernier, Nicolas, additional, Cooper, David, additional, Chevalier, Nicolas, additional, Grampeix, Helen, additional, Charpin, Christelle, additional, Jalaguier, Eric, additional, Kogelschatz, Martin, additional, Schamm-Chardon, Sylvie, additional, and Audoit, Guillaume, additional
- Published
- 2016
- Full Text
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9. Very Low Temperature Tensile and Selective Si:P Epitaxy for Advanced CMOS Devices
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Kanyandekwe, Joël, Bauer, Matthias, Marion, Tanguy, Saidi, Lazhar, Pin, Jean-Baptiste, Bisserier, Jeremie, Richy, Jérôme, Gauthier, Nicolas, Dezest, Pattamon, Brunet, Laurent, Lapras, Valérie, Dewolf, Tristan, Thomas, Shawn, and Hartmann, Jean-Michel
- Abstract
We demonstrate the feasibility of selectively growing highly doped and tensile-strained Si:P layers at temperatures 500°C or less on each side of advanced n-type MOS devices. To that end, we used a Cyclic Deposition Etch (CDE) strategy instead of a conventional “co-flow” approach fit for the high temperature (> 600°C) Selective Epitaxial Growth (SEG) of t-SiP films. A high order silicon precursor was used together with PH3to benefit from high t-Si:P growth rates at 500°C and less. Selective etchings were performed with Cl2as an etchant gas, as it yielded much higher etch rates than HCl. We first investigated the blanket growth of t-SiP on fullsheet Si wafers. 5 to 15 times higher higher growth rates than with standard precursors were obtained at low temperatures with our new HOS silicon precursor. We then investigated the etching efficiency of Cl2, with several tens of nanometers per minutes etch rates achieved at very low temperatures. Using a CDE strategy, we then probed phosphorus incorporation in blanket t-Si:P films on fullsheet wafers. High quality and smooth t-SiP layers with up to 5.4%, 4.3% and 5.8% of P and sheet resistances as low as 0.33, 0.27 and 0.21 mohm.cm were obtained at 500°C, 475°C and 450°C, respectively. We then tested our CDE SiP process for SEG, first on test structures then on each side of real FD-SOI devices, with smooth, high quality, tensile SiP layers grown at 500°C with 4.5% of P.
- Published
- 2022
- Full Text
- View/download PDF
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