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In the digital age, medical images have become an indispensable tool for the diagnosis of certain diseases and health prevention. In the face of increasing computing power and diverse means of attack, as well as the need for real-time processing of medical images, traditional encryption and watermarking techniques may no longer be sufficient to effectively protect the integrity and copyright of these sensitive images. Based on this practical requirement, this study proposes a novel digital watermarking algorithm for copyright authentication of ophthalmic medical images using a chaotic system. This algorithm integrates a novel three-dimensional pupal equilibrium curved hyperchaotic system (PCHCS) to enhance the encryption effect of the AES algorithm. Clever embedding of watermarks in the edge regions of the ROI using Least Significant Bit (LSB) technology ensures minimal impact on diagnostic quality. RONI uses DCT transform for processing to enhance copyright authentication. The chaotic system and watermarking algorithm have been implemented on FPGA to further demonstrate their feasibility. The PSNR of the proposed system can reach more than 55 dB and the SSIM value is close to 1. The values of NC and BER also perform well under various attacks. Experimental results show that the designed watermarking algorithm has good invisibility and robustness. [ABSTRACT FROM AUTHOR]

This paper describes observations and experiences collected during 14 years of running the "Integrated circuits" course in the framework of a distance learning program. The main objective of the "Integrated circuits" course is to raise the interest in microelectronics, convince the students that IC design is not a "secret science" requiring extraordinary talent and prepare the students for continuation toward M.Sc. degree. The course includes a mixture of teaching materials available online for self-studying, short video files, interactive self-tests, two "hands on" exercises and educational software needed for these exercises. E-mail and/or phone consultations, face-to-face or online meetings with the instructor are possible. About 1/3 of all students enrolled for the distance learning course perceive the "Integrated circuits" course as interesting, praise the design exercises and ask if it would be possible to continue education in microelectronic design at a more advanced level. Unfortunately distance learning at advanced level is not possible, mainly because professional design software can be used only on site, not remotely. [ABSTRACT FROM AUTHOR]

Currently, design and application of discrete memristor aroused much interests. In this paper, digital integrated circuits of discrete memristive systems are designed based on the proposed fixed-point specific processor with acceleration instructions. The discrete memristor and the discrete memristive chaotic map are designed based on the trigonometric function including the Sine function and the Cosh function. It shows that the chaotic system has rich dynamics and can generate hyperchaos. To design a universal digital integrated circuit implementation method, a fixed-point specific processor is designed which is programmable. As a result, the chip layout of the memristive systems is obtained. Numerical simulations are completed in accordance with the Matlab simuation results. Compared with the ASIC(Application-Specific Integrated Circuit) based method, the digital circuit in this paper is two times larger in area and has 50% more power consumption due to the trigonometric and hyperbolic functions, but it can be reprogrammed to implement different models. It provides a new technical scheme for the application of discrete memristors in different engineering application fields. [ABSTRACT FROM AUTHOR]

The feedthrough effect can significantly affect the performance of MEMS gyroscopes and even lead to device failure. In order to address the inevitable problem of feedthrough capacitance caused by microfabrication process and circuit structure, two automatic feedthrough cancellation solutions are proposed based on the analysis of the feedthrough effect. Firstly, an equivalent feedthrough model is established for MEMS gyroscopes. Then, through theoretical derivation and model simulation, various influences of feedthrough effect are analysed, and the critical value of feedthrough capacitance is calculated to achieve better compensation effects. For feedthrough capacitance greater than the critical value, a feedthrough cancellation method utilizing AD5231 digital potentiometer for generating an inverse signal is designed. For the situation of feedthrough capacitance less than the critical value, a feedthrough cancellation method based on pure digital circuit calculation is proposed. The experimental results show that the method of utilizing digital potentiometer effectively reduces the feedthrough level from −17.46 dB to −32.75 dB, and the method of utilizing pure digital circuit calculation compensates the feedthrough signal of 100.04 mV to almost zero (2.44 mV) within the range of ADC sampling accuracy. These two methods can accurately and quickly suppress feedthrough signal to improve the detection performance of MEMS gyroscopes, and are expected to meet the needs of future mass production. In addition, they can be widely applied to various MEMS devices that require feedthrough cancellation. [ABSTRACT FROM AUTHOR]

This article discusses the issue of studying the parameters of the bounce of electrical contacts of switches in digital systems. Digital circuits of bounce analyzer are described. The results of experimental studies of the behavior of electrical contacts of various buttons and switches are presented. It is shown that various electric switches have random and unique characteristics, which can be used to solve the problems of random numbers generating, identifying of digital devices and user’s authentication. Prototyping of the proposed circuits was carried out on Digilent ZYBO Z7-10 debug boards, digital circuits were designed in VHDL for the Xilinx Zynq-7000 FPGA chip.

Computational cost in metaheuristics such as Evolutionary Algorithm (EAs) is often a major concern, particularly with their ability to scale. In data-based training, traditional EAs typically use a significant portion, if not all, of the dataset for model training and fitness evaluation in each generation. This makes EA suffer from high computational costs incurred during the fitness evaluation of the population, particularly when working with large datasets. To mitigate this issue, we propose a Machine Learning (ML)-driven Distance-based Selection (DBS) algorithm that reduces the fitness evaluation time by optimizing test cases. We test our algorithm by applying it to 24 benchmark problems from Symbolic Regression (SR) and digital circuit domains and then using Grammatical Evolution (GE) to train models using the reduced dataset. We use GE to test DBS on SR and produce a system flexible enough to test it on digital circuit problems further. The quality of the solutions is tested and compared against state-of-the-art and conventional training methods to measure the coverage of training data selected using DBS, i.e., how well the subset matches the statistical properties of the entire dataset. Moreover, the effect of optimized training data on run time and the effective size of the evolved solutions is analyzed. Experimental and statistical evaluations of the results show our method empowered GE to yield superior or comparable solutions to the baseline (using the full datasets) with smaller sizes and demonstrates computational efficiency in terms of speed.

Basic analog–digital motion detection circuits with low power consumption were proposed based on the vertebrate retina. The motion sensor based on the retina is constructed with a one- or two-dimensional array of the unit circuits. The proposed unit circuit for motion detection is constructed with an analog circuit for photoelectric conversion and the digital circuit for generating the motion signal. The metal oxide semiconductor (MOS) transistors utilized to the analog circuits are operated in the subthreshold region. The analog circuit has the characteristic of the low power consumption. The proposed circuit was evaluated by the simulation program with integrated circuit emphasis (SPICE) with the 0.6 μm complementary metal oxide semiconductor (CMOS) process. The test circuits of basic digital circuits were fabricated with the same process. In the simulation and the experiment, the power supply voltage was set to the low voltage. We found that the digital circuit becomes low power consumption because the MOS transistors was operated in the subthreshold region by setting the low voltage. The proposed circuit is characterized by the simple structure and the low power consumption. In the future, the novel motion detection sensor with low power consumption can be realized by applying the integrated circuits constructed with the array of the proposed unit circuits. [ABSTRACT FROM AUTHOR]

The multiplier circuit is considered to be a significant component of larger circuits, such as the arithmetic and logic unit (ALU), and it is crucial to enhance its energy efficiency. This objective can be easily achieved by utilizing graphene nanoribbon field-effect transistor (GNRFET) devices and adopting ternary logic. Ternary circuit designs demonstrate superior energy efficiency and occupy less space compared to binary ones. The adjustability of the threshold voltage (Vth) in GNRFET devices is directly influenced by the width of the graphene nanoribbon (GNR). This offers significant advantages for ternary circuit designs. This paper presents a 24-transistor low-energy GNRFET-based single-trit ternary multiplier. Our proposed design incorporates an enhanced voltage division technique to achieve logic ‘1’ while minimizing power consumption. The primary design approach employed in our design involves the utilization of unary operators and specialized transistor configurations to reduce the number of transistors and shorten the critical path. We used the Hewlett simulation program with integrated circuit emphasis (HSPICE) and GNRFET technology with a 32- nm channel length operating at 0.9 V and 300˚ K to evaluate the efficiency of our circuit. We then compared it with similar existing ternary multiplier circuits. The suggested circuit displays favorable delay and power consumption characteristics and ranks as the second most optimal design in terms of energy efficiency. Furthermore, it improves the energy-delay-product by at least 2.80%. [ABSTRACT FROM AUTHOR]

The Internet of Things (IoT) is pivotal in transforming the way we live and interact with our surroundings. To cope with the advancement in technologies, it is vital to acquire accuracy with the speed. A phase frequency detector (PFD) is a critical device to regulate and provide accurate frequency in IoT devices. Designing a PFD poses challenges in achieving precise phase detection, minimising dead zones, optimising power consumption, and ensuring robust performance across various operational frequencies, necessitating complex engineering and innovative solutions. This study delves into optimising a PFD circuit, designed using 90 nm standard CMOS technology, aiming to achieve superior operational frequencies. An efficient and high-frequency PFD design is crafted and analysed using cadence virtuoso. The study focused on investigating the impact of optimising PFD design. With the optimised PFD, an operational frequency of 5 GHz has been achieved, along with a power consumption of only 29 µW. The dead zone of the PFD was only 25 ps. [ABSTRACT FROM AUTHOR]

A hydrogen maser is a high-precision time measurement instrument with high frequency stability and low frequency drift, which is widely used in satellite navigation, ground time keeping, frequency measurement, and other fields. An active hydrogen maser (AHM) is better than the current space passive hydrogen maser (PHM) in orbit in terms of its frequency stability and drift rate, but it has the disadvantages of large volume and weight. To further reduce the volume and weight of the circuit, this paper demonstrates a digital circuit control system based on a field-programmable gate array (FPGA). It uses digital temperature control, digital detectors, digital down-conversion, digital phase-locked loops, and other digital methods for temperature control, cavity auto-tuning, and crystal phase locking, which improve the integration and flexibility of the circuit system. Meanwhile, a tuning method based on hydrogen flow is proposed, which effectively solves the problem of fluctuations in hydrogen maser resonance frequency with changes in the external environment. Our experimental results show that the designed digital circuit control system meets the requirements of an oven-controlled crystal oscillator (OCXO) loop and a cavity loop. Its frequency stability can reach 2.6 × 10 − 13 / 1   s and 1.4 × 10 − 15 / 10,000   s , which is close to the stability index of ground active hydrogen maser. This scheme has certain practical engineering value, and can be used in the design of hydrogen masers for next-generation space navigation satellites, deep space exploration, and space stations. [ABSTRACT FROM AUTHOR]

To meet the high dynamic voltage or current range measuring in real-time in the modern electrical industry, ranging from the surface science to non-destructive testing, this paper reports two broad dynamic ranging, universal, and compact digital lock-in amplifier methods for the huge dynamic range signal, termed as the hybrid and all-digital amplifiers. Both have reduced the complex components required in the traditional amplifiers to only two or three components without sacrificing the measuring accuracy, even by less than 0.05% in some situations, which has been evaluated via simulations and experiments with the FPGA circuit. Additionally, benefiting from the single-power supply strategy, the proposed methods are suitable for portable devices, including the pocket spectrometer, mechanical resonator monitor, and powered on battery. Such results in this paper illustrate the phase coherent technology with a compact, universal, and integrated circuit with a promising future. [ABSTRACT FROM AUTHOR]

Novel basic analog–digital edge detection circuits in this research were proposed based on the vertebrate retina. The vertebrate retina is a pre-processor for image processing in the brain and has superior functions such as edge detection and motion detection. The proposed circuit was evaluated by the simulation program with integrated circuit emphasis (SPICE) with the 0.6 μm complementary metal oxide semiconductor (CMOS) process. The simulation results with SPICE showed that the proposed circuits can operate normally. The test integrated circuit of the unit circuit was fabricated with a 0.6 μm CMOS process. The measured results showed that the unit circuit can detect the edge position. The test integrated circuits of one-dimensional array of unit circuits were fabricated with the same process. The measured results showed that the one-dimensional circuits can detect the edge position. In the future, the realization of a new vision sensor can be expected using the proposed circuit. [ABSTRACT FROM AUTHOR]

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In this work, a digital circuit for fast scan voltammetry (FSV) was developed based on dual-frequency method. It consists of six main modules including the microcontroller unit, signal generator module, solution resistance measurement module, ohmic drop automatic compensation module, keying module and display module. By online measuring the solution resistance without any interference from capacitive impedance first, the ohmic drop compensation could be precisely carried out, bringing reliable FSV detection. RC dummy cell, dummy cell with pseudo-Faradaic impedance and actual electrochemical cell were used to verify the performance of automatic ohmic drop compensation. Results show that, FSV could be performed using a conventional electrode with the scan rate up to 2400 V/s. And, a handheld device was manufactured with a weight of 100 g and a size of 9 × 6 × 3 cm, costing only $35. It provides a simple, reliable and stable FSV plateau for electrochemical detection. [ABSTRACT FROM AUTHOR]

Embryonic architecture that carries self-evolving design with fault tolerant feature is proposed for deep space missions. Fault tolerance is achieved in the embryonic architecture due to its homogeneous structure. The cloning of configuration data or genome data to all the embryonic cells makes each cell capable of selecting required cell function using selective gene. The primary digital circuits of avionics are implemented on the fabric, where the configuration data in Cartesian Genetic Programming (CGP) format is evolved through customized GA. The CGP format is preferred over LUT format for the circuit configuration data due to its fixed data size in case of modular design. Further the CGP format enables fault detection at embryonic cell level as well as logic gate level. The various combinational and sequential circuits like adder, comparator, multiplier, register and counter are designed and implemented on embryonic fabric using Verilog. The circuit performance is evaluated using simulation. The proposed PHsClone genetic algorithm (GA) design with parallel-pipeline approach is to achieve faster convergence. Four concurrent PHsClone GA executions (four parallel threads) achieve convergence for the 10 times faster for a 1-bit adder, and 3 times faster for a 2-bit comparator. [ABSTRACT FROM AUTHOR]

This paper reports a new fractional-order Chua’s system with arctan function and an algorithm for determining the initial value of fractional-order hidden attractors. Firstly, dynamics of the system is investigated by employing the stability analysis, dissipativeness, phase diagrams, 0-1 test, bifurcation diagram and SampEn complexity measure. It shows rich dynamics in the proposed system. Secondly, using the proposed algorithm, the initial values of the new fractional-order Chua’s system are calculated. And according to two sets of initial conditions, hidden attractors are found and verified by the numerical simulation. Meanwhile, the basin attraction is analyzed to confirm that the hidden attractor is indeed not near the fixed point. Thirdly, the new fractional-order Chua’s system is implemented on the DSP platform, and the arctan function’s processing algorithm is proposed. The DSP experimental results show that the system can produce a pair of coexisting fractional-order hidden attractors, and the experimental results are consistent with the numerical simulation results. It verifies the effectiveness of the presented methods and shows the potential engineering application value of the proposed Chua’s system.

The quantum-dot cellular automata computing paradigm shows particular promise in terms of density and power and also enabling a new approach to implement reversible computing. In this paper, we explore the efficient designs of various latches based on reversible logic for quantum-dot cellular automata building blocks, while applying the cell placement constraints introduced by the use of wave clock. Compared to previous literature, the proposed solutions show smaller cell count while using a potentially implementable clocking scheme for molecular QCA wave clocking. The functional correctness of the proposed latches are presented and verified using QCADesigner and HDLQ. Furthermore, we present detailed characterization and analysis, considering different cost metrics of the proposed latches. It is shown that, compared to previous literature, critical paths are decreased by 50%, 33%, 50%, 25% respectively for D-Latch, T-Latch, JK-Latch, and SR latch. There is also an improvement in timing is about 50% for D-Latch and JK-Latch, and 25% for SR-Latch. [ABSTRACT FROM AUTHOR]

The main idea is to create logic-free vector computing, using only read-write transactions on address memory. The strategic goal is to create a deterministic vector-quantum computing using photons for read-write transactions on stable subatomic memory elements. The main task is to implement new vector computing models and methods based on primitive read-write transactions in vector flexible interpretive fault modeling and simulation technology, where data is used as addresses for processing the data itself. The essence of vector computing is read-write transactions on vector data structures in address memory. Vector computing is a computational process based on elementary read-write transactions over cells of binary vectors that are stored in address memory and form a functionality where the input data to be processed is the addresses of these cells. The advantages of a vector universal model for a compact description of ordered processes, phenomena, functions, and structures are defined for the purpose of their parallel analysis. Analytical expressions of logic, which require algorithmically complex calculators, are replaced by output state vectors of elements and digital circuits, focused on the parallelism of register logical procedures on regular data structures. A vector-deductive method for formula synthesis for propagating input lists (data) of faults is proposed, which has a quadratic computational complexity of register operations. A new matrix of deductive vectors has been synthesized, which is characterized by the following properties: compactness, parallel data processing based on a single read-write transaction in memory, elimination of traditional logic from fault simulation procedures, full automation of its synthesis process, and focus on technological solving all problems of technical diagnosis. In the work, the transition to vector logic in the organization of computing and the elimination of traditional logic presented in the form of tables and analytical expressions were carried out. The use of read-write transactions on memory in the absence of a command system focuses the new vector-logic computing to-wards deterministic quantum architectures based on stable subatomic memory particles. [ABSTRACT FROM AUTHOR]

In this study, we propose a lightweight and low-latency advanced encryption standard (AES) accelerator. Instead of being connected to the bus through its own slave wrapper, the proposed AES accelerator is located within the slave wrapper of the static random-access memory (SRAM) and is directly attached to the SRAM. Hence, the AES accelerator can directly access data in the SRAM and share SRAM space for storing expanded keys, resulting in no time for transferring input and output data, no resource usage for storing keys, and no power wastage for repeated key expansion. The proposed AES accelerator has a latency of 53 clock cycles per encryption/decryption process and has a gate count of 2912 when synthesized using 28 nm process technology. The latency is similar to that of another AES accelerator with the same 32-bit data path; however, the size of the proposed accelerator is 46.0% smaller. Furthermore, compared with other AES accelerators with 8-bit data path, the proposed AES accelerator has a 3.0–22.0 times smaller latency with a slightly larger area.

In real-time applications, unpredictable random numbers play a major role in providing cryptographic and encryption processes. Most of the existing random number generators are embedded with the complex nature of an amplifier, ring oscillators, or comparators. Hence, this research focused more on implementing a Hybrid Nature of a New Random Number Generator. The key objective of the proposed methodology relies on the utilization of True random number generators. The randomness is unpredictable. The additions of programmable delay lines will reduce the processing time and maintain the quality of randomizing. The performance comparisons are carried out with power, delay, and lookup table. The proposed architecture was executed and verified using Xilinx. The Hybrid TRNG is evaluated under simulation and the obtained results outperform the results of the conventional random generators based on Slices, area and Lookup Tables. The experimental observations show that the proposed Hybrid True Random Number Generator (HTRNG) offers high operating speed and low power consumption. [ABSTRACT FROM AUTHOR]

In the present research article, we have proposed an analytical compact model for nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor's operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (ΦS), obtained from approximated solutions of Poisson's equation. The proposed model has implemented in standard Verilog-A language using SMASH circuit simulator in order to be used in various commercial circuit simulators. The proposed model has also validated using ATLAS-TCAD simulation for various physical parameters such as the channel doping concentration (Nd) and the channel radius (R) of JLNGAA MOSFET. Finally, based on the developed Verilog-A JLNGAA MOSFET model, we have tested it in four types of low voltage circuits, CMOS inverter, CMOS NOR-Gate, an amplifier and a Colpitts oscillator. [ABSTRACT FROM AUTHOR]

Circuit designers are always faced with new obstacles as a result of the persistent trend in today's nanoscale technology to follow Moore's law. The complexities inherent in the production process have increased dramatically due to the rapid downscaling of integration. Parallel to this, the complexity and unpredictability of silicon chip flaws have increased, making circuit testing and diagnosis more challenging. The amount of test data has multiplied, and the criteria governing integrated circuit testing have grown both in size and in the complexity of correlation. The modern situation provides a useful framework for investigating novel machine learning-based test solutions. In this paper, the authors examine different recent developments in this developing field in the context of digital logic testing and diagnosis.

In this paper, a two-wing chaotic system is transformed into a four-wing chaotic system and an eight-wing chaotic system using fractal processing and the dynamic characteristics of new multi-wing chaotic systems are analyzed. The encryption of the image is accomplished by combining the eight-wing chaotic system and the improved AES algorithm. The number of AES encryption rounds is reduced to make it more suitable for image encryption. To further improve the encryption efficiency, the chaotic system circuit and AES parallel computation are designed and implemented on FPGA. Finally, the high performance of the chaotic system is demonstrated by the satisfactory encryption effect. This methodology provides a promising direction for the study of real-time image encryption. [ABSTRACT FROM AUTHOR]

Thin-walled cylindrical shells are widely used in industries, such as the main parts of aircrafts, rockets, and submarines. Except for meeting the load-bearing capacities, such structures must also have good vibration and acoustic performances. However, it is still a challenge to control the multi-modal vibration of cylindrical shells at low frequencies. This study explores the cutting-edge local resonant piezoelectric metamaterials to control the low-frequency vibration of cylindrical shells. A novel cylindrical meta-shell with piezoelectric materials and digital circuits was proposed, and a multi-resonance transfer function is implemented in each digital circuit. A method to optimizing the parameters in the transfer function for the purpose of vibration reduction is developed. The vibrational characteristics of the meta-shell are numerically analyzed using the finite element method. Numerical results clearly demonstrate that by delicately designing the parameters in the transfer function, the meta-shell can reduce the peak amplitudes of the first five modes by 30 dB or more. Therefore, the proposed piezoelectric cylindrical meta-shell may open new opportunities in vibration mitigation of transport vehicles and underwater equipment.

Background. Cancer care involves a multidisciplinary approach to diagnosis and treatment of patients. A complex interaction of actors in the deployment of oncology services dictates usage of modern management technologies for improving the quality and efficiency of patient care through processes optimisation.Objectives. Provision of recommendations for patient routing based on research into the oncology service inter-level information exchange, integration of the process approach and electronic services. The lack of a unified information space with a regional oncology service has been explained. Measures are proposed for the patient routing optimisation as part of establishing a unified digital oncology service circuit.Methods. The oncology service was effectively remodelled through functional and information engineering of electronic services and the process management integration to establish a horizontal decision flow between facilities and employees on a process level bypassing the supervisor coordination. Statistical approaches were used to analyse the oncological patient population.Results. The following electronic services have been implemented: specialised patient referral routing, telemedicine and teleradiology. A comprehensive information framework has been created comprising medical, laboratory and radiological information subsystems integrated through regional electronic services of the unified state healthcare information platform. The goals, objectives, general principles, architecture and expected social economic impact on healthcare of Krasnodar Krai have been defined.Conclusion. Use of electronic services ensures an improved quality of specialised care and effective routing of patients. We perceive prospects of the integrated information platform in the extension and improvement of its subsystems’ functionality and content, sourcing more data providers and the circuit expansion to the federal and regional levels.

Summary: In advanced technology, static random‐access memory (SRAM) cells used in space are highly sensitive to charge variations caused by high‐energy particle strikes, which cause soft‐error. Therefore, it is imperative for an SRAM to withstand this harsh environment. However, 6T cells are unable to function reliably in such a place. In order to address this, a radiation‐hardened read‐decoupled 12T (RHRD12T) SRAM cell is proposed in this paper. The relative strength of RHRD12T is estimated by comparing it with other contemporary cells such as NS10T, PS10T, RHBD10T, QUATRO12T, QUCCE12T, and RHD12T on various major design metrics. Due to the read‐decoupled nature of RHRD12T, it shows the highest read stability. It also consumes the lowest hold power compared to all other considered cells, except NS10T. Moreover, RHRD12T exhibits the highest write ability due to the use of two extra access transistors and the poor driving ability of the internal nodes. In terms of write delay, RHRD12T shows an improvement of 1.02×/1.06×/1.07×/1.08× over NS10T/RHD12T/PS10T/RHBD10T at VDD = 1 V. Moreover, RHRD12T is capable of tolerating the highest amount of critical charge among all other comparison cells and is the least susceptible to single‐event upsets. All the aforementioned improvements are obtained at the cost of longer read delay. [ABSTRACT FROM AUTHOR]

In this paper, a new fundamental cell in positive feedback source coupled logic is presented, which is an improvement over the existing fundamental cell employed in digital circuit design in various high resolution mixed-signal integrated circuits. The operation of the existing fundamental cell relies on using large sized transistor in its centre branch, resulting in significantly larger implementation area. The proposed fundamental cell incorporates multi-threshold transistor in the center branch thereby allowing designer to use reduce its dimension and hence the area. The impact of the proposed modification is examined by configuring the cell as two input exclusive OR (XOR2) gate. The behaviour is analysed in terms of static and propagation delay parameters which are modelled and a design procedure is also elaborated. The theoretical prepositions are verified by designing and simulating for various operating conditions using model parameters of 180 nm CMOS technology node. A maximum error of 27% is observed between the simulated and predicted parameters. The process variation study through Monte Carlo analysis and PVT variations identifies the proposed fundamental cell based circuit as less prone to variations in comparison to existing fundamental cell based counterparts. A full adder, as an application of the proposed fundamental cell, shows a significant (66%) area reduction while delay, power and PDP are within 4% of their corresponding values for the existing one. [ABSTRACT FROM AUTHOR]

It is proposed to use transistor-transistor logic (TTL) for future fast, low-power digital electronic circuits. A relaxation quantum transistor can be the basic element of these circuits. This approach allows us to circumvent the difficulties of using field effect transistors based on nanowires. [ABSTRACT FROM AUTHOR]

We examine the modes of intervention of global public intellectuals at times of crisis. In critical situations, public intellectuals take positions on matters that affect the societies they inhabit and, eventually, all humanity. To this end, they take advantage of the opportunities afforded by new communications technologies, establishing an important distinction between the "analog" intellectual (who relies on the slow time of books, opinion columns, and bookstores) and the "digital" intellectual who uses modern information and communications technologies. To study the activities of global public intellectuals and their political influence, we propose to leave aside the notion of "transnational intellectual field" in favor of an understanding of a transnational intellectual stage peopled by a certain type of intellectual agent whose symbolic and cultural production is disseminated through a digital global public circuit. To illustrate the functioning of a circuit of this type, we take the example of the Project Syndicate platform. [ABSTRACT FROM AUTHOR]

To reduce the energy consumption of logic gates in digital circuits, the size of transistors approaches the mesoscopic scale, e.g. sub-7 nanometers. However, existing energy consumption analysis methods exhibit various deviation for logic gates when the nonequilibrium information processing of mesoscopic scale transistors with ultra-low voltages is analyzed. Based on the stochastic thermodynamics theory, an information energy ratio method is proposed for the energy consumption estimation of XOR gates composed of mesoscopic scale transistors. The proposed method provides a new insight to quantify the transformation between the information capacity and energy consumption for XOR gates and extending to other logic gates. Utilizing the proposed analysis method, the supply voltage of the parity check circuit can be optimized by numerical simulations without expensive and complex practical measurements. The information energy ratio is the first analytical method to quantify the energy and information transformation of logic gates at the mesoscopic scale., (© The Author(s) 2024. Published by Oxford University Press on behalf of National Academy of Sciences.)

The insistent trend in today's nanoscale technology, to keep abreast of the Moore's law, has been continually opening up newer challenges to circuit designers. With rapid downscaling of integration, the intricacies involved in the manufacturing process have escalated significantly. Concomitantly, the nature of defects in silicon chips has become more complex and unpredictable, adding further difficulty in circuit testing and diagnosis. The volume of test data has surged and the parameters that govern testing of integrated circuits have increased not only in dimension but also in the complexity of their correlation. Evidently, the current scenario serves as a pertinent platform to explore new test solutions based on machine learning. In this survey, we look at various recent advances in this evolving domain in the context of digital logic testing and diagnosis. This article is categorized under:Algorithmic Development > Structure DiscoveryTechnologies > Machine LearningTechnologies > Prediction [ABSTRACT FROM AUTHOR]

This article proposes a new necessary condition and the corresponding speedup strategies to the threshold function (TF) identification problem. The state-of-the-art to this identification problem could be very time-consuming when the function-under-identification is a non-TF with the unateness property. The proposed new necessary condition can be seamlessly integrated into this identification algorithm. As compared with the state-of-the-art, the improved identification algorithm with the proposed necessary condition can more effectively and efficiently detect non-TFs. Furthermore, according to the experimental results, the ratio of CPU time overhead in the process of checking the proposed necessary condition for identifying all the 8-input TF is only 0.1%. [ABSTRACT FROM AUTHOR]

A framework is presented to identify an optimal accelerated test region and accelerated test conditions for the accelerated test of logic circuits for time-dependent dielectric breakdown (TDDB). Both gate-oxide breakdown and middle-of-line (MOL) TDDB are investigated. Separate test regions are identified for each wearout mechanism. Two digital circuits, an 8-bit fast Fourier transform (FFT) circuit and a Leon3 microprocessor are used to demonstrate the capability of the framework. The lifetimes of standard cells are combined to compute the circuit lifetime, by combining the Weibull distributions that characterize the lifetime distribution of each of the standard cells. The errors in estimating wearout parameters consist of two parts: the error in estimating the wearout parameters at accelerated test conditions and the forecasting accuracy at use conditions. By estimating the errors in wearout parameters at accelerated test conditions, the optimal accelerated test region is found by determining the test conditions producing a minimal error. Test conditions are selected by minimizing the error at use conditions. Given a forecasting error target, the required sample size at each test condition is found. This work also considers the impact of variation in circuit size, type, and process parameters on the selection of optimal test conditions. [ABSTRACT FROM AUTHOR]