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At cryogenic temperatures, carrier mobility in bulk silicon exhibits a significantly different temperature dependence compared with that at room temperature. To capture this difference and accurately calculate cryogenic carrier mobility in technology computer-aided design (TCAD) simulation, we have developed a physics-based analytical mobility model. The proposed model is built upon two components: ionized impurity scattering and neutral impurity scattering. The ionized impurity scattering component is developed within the unified Klaassen’s mobility model framework, which also incorporates other scattering mechanisms such as lattice scattering and carrier-carrier scattering. To overcome the limitations of Klaassen’s model below 100 K, we incorporated the nonlinear screening effect and used the variable phase approach (VPA), a robust method for calculating minority impurity mobility. The neutral impurity scattering component adopts an existing practical model, which accurately captures the effect of scattering by neutral impurities at low temperatures. Our model exhibits good match to the experimental data on both majority and minority carrier mobility. Above 100 K, our model can be simplified to the original Klaassen’s mobility model, demonstrating its compatibility with the existing models at higher temperatures. In cryogenic bulk silicon simulations, our model exhibits good convergence performance and accuracy, making it applicable in cryogenic device simulations.

This article proposes a novel zigzag-cell design for the six-transistor static random access memory (SRAM) bitcell in the complementary field-effect transistor (CFET) framework. The zigzag-cell design not only maintains the aggressive area reduction but also allows for shorter bitlines, directly benefiting from the circuit layout changes caused by the CFET architecture. The specific layouts of the zigzag-cell design are introduced by incorporating them into two process flows with different complexity. The first assumed process flow contains only the essential steps of CFET SRAM, and according to which the zigzag-cell bitcell can achieve an area reduction of more than 20% over the thin-cell bitcell. Moreover, the performance of zigzag-cell SRAM is also improved by 4.6% and 16.3% in read time and write margin, respectively. Following the second more complicated process flow, the zigzag-cell design does not offer further area reduction compared with the thin-cell design, but it needs fewer metal layers. The proposed design is a promising choice for the CFET SRAM bitcell layout.