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A broadband 28 nm complementary metal–oxide–semiconductor (CMOS) power amplifier was implemented using a distributed amplification design. To develop a model library for high-frequency design, various test patterns for active and passive elements were fabricated and compared through measurements. As a result, a symmetrical n-channel field-effect transistor (NFET) was used as the active device, and a co-planar waveguide (CPW) with floating bottom metal layers was chosen as the transmission line for the passive element. These choices demonstrated superior radio frequency (RF) characteristics at high frequencies compared to other device candidates. Furthermore, to address the low breakdown voltage of CMOS, a triple-stacked FET structure was designed as the gain cell of the distributed power amplifier (DPA). The fabricated DPA showed a maximum small-signal gain of 22 dB and a minimum of 10 dB from DC to 56 GHz, with a maximum saturated output power of 20 dBm and a minimum of 13 dBm from 1 to 39 GHz. Notably, these results were achieved on the first attempt by designing solely based on measurement data from the test patterns. [ABSTRACT FROM AUTHOR]

This paper describes a distributed power amplifier(DA) which was developed using 0.25 μm GaAs pHEMT process. The process of its circuit design and optimization is presented in details. Gain flatness in the low frequency range of this DA has a significant improvement by employing low frequency termination. The simulation result shows that DA which operates between DC and 30 GHz has a gain of 8.5 dB and 21 dBm of output power at 1 dB gain compression and maximum PAE up to 20%.

A 6‐GHz‐to‐18‐GHz monolithic nonuniform distributed power amplifier has been designed using the load modulation of increased series gate capacitance. This amplifier was implemented using a 0.25‐μm AlGaN/GaN HEMT process on a SiC substrate. With the proposed load modulation, we enhanced the amplifier's simulated performance by 4.8 dB in output power, and by 13.1% in power‐added efficiency (PAE) at the upper limit of the bandwidth, compared with an amplifier with uniform gate coupling capacitors. Under the pulse‐mode condition of a 100‐μs pulse period and a 10% duty cycle, the fabricated power amplifier showed a saturated output power of 39.5 dBm (9 W) to 40.4 dBm (11 W) with an associated PAE of 17% to 22%, and input/output return losses of more than 10 dB within 6 GHz to 18 GHz.

This study presents a 2–20 GHz monolithic distributed power amplifier (DPA) using a 0.25 μm AlGaN/GaN on SiC high electron mobility transistor (HEMT) technology. The gate width of the HEMT was selected after considering the input capacitance of the unit cell that guarantees decade bandwidth. To achieve high output power using small transistors, a 12-stage DPA was designed with a nonuniform drain line impedance to provide optimal output power matching. The maximum operating frequency of the proposed DPA is above 20 GHz, which is higher than those of other DPAs manufactured with the same gate-length process. The measured output power and power-added efficiency of the DPA monolithic microwave integrated circuit (MMIC) are 35.3–38.6 dBm and 11.4%–31%, respectively, for 2–20 GHz.

This letters presents a new wideband power amplifier approach to achieve high performance of wideband frequency operation from low frequency such as 80-2100 MHz for two-way radio applications. The approach is referring to distributed power amplifier with phase adjustment of the gate line network to balance with drain line network (specifically with drain line tapering). Experimental of the prototype level with gallium nitride high-electron-mobility-transistor demonstrated output power of 41 dBm, flat gain at 12 dB, and bandwidth covering 80 MHz to 2.1 GHz with power added efficiency of 45% under 28 V drain bias. According to the author's knowledge, this work has illustrated a significant enhancement in efficiency over the conventional topology, low cost implementation, and offers wideband operation for public safety applications. [ABSTRACT FROM AUTHOR]

A 6-GHz-to-18-GHz monolithic nonuniform distributed power amplifier has been designed using the load modulation of increased series gate capacitance. This amplifier was implemented using a 0.25-μm AlGaN/GaN HEMT process on a SiC substrate. With the proposed load modulation, we enhanced the amplifier's simulated performance by 4.8 dB in output power, and by 13.1% in power-added efficiency (PAE) at the upper limit of the bandwidth, compared with an amplifier with uniform gate coupling capacitors. Under the pulse-mode condition of a 100-μs pulse period and a 10% duty cycle, the fabricated power amplifier showed a saturated output power of 39.5 dBm (9 W) to 40.4 dBm (11 W) with an associated PAE of 17% to 22%, and input/output return losses of more than 10 dB within 6 GHz to 18 GHz. [ABSTRACT FROM AUTHOR]

The self-biasing circuit through a feedback resistor is applied to a gallium nitride (GaN) distributed power amplifier (PA) monolithic microwave circuit (MMIC). The self-biasing circuit is a useful scheme for biasing depletion-mode compound semiconductor devices with a negative gate bias voltage, and is widely used for common source amplifiers. However, the self-biasing circuit is rarely used for PAs, because the large DC power dissipation of the feedback resistor results in the degradation of output power and power efficiency. In this study, the feasibility of applying a self-biasing circuit through a feedback resistor to a GaN PA MMIC is examined by using the high operation voltage of GaN high-electron mobility transistors. The measured results of the proposed GaN PA are the average output power of 41.1 dBm and the average power added efficiency of 12.2% over the 6-16 GHz band. [ABSTRACT FROM AUTHOR]

This paper presents the design, analysis, and measurement of a pseudodifferential distributed power amplifier in a 0.13-\mum SiGe BiCMOS process. To mitigate the large loaded transmission line loss due to bipolar base resistance, emitter degeneration is used and an optimal small-signal design point is selected for maximum gain-bandwidth product. To enhance the efficiency of distributed amplifiers (DAs), a stage-scaling technique is proposed to utilize more voltage swing while reducing the total current consumption. The output power and efficiency of the amplifier are evaluated as a function of two scaling coefficients. The fabricated distributed power amplifier achieves a small-signal gain of 10 dB and a 3-dB bandwidth of 110 GHz. The measured midband saturated output power is 17.5 dBm with a peak power-added efficiency (PAE) of 13.2% and the 3-dB output power bandwidth is greater than 77 GHz. The amplifier consumes 119 mA from a 3-V supply and occupies an area of 2.08 mm \,\times\, 1.05 mm. Compared to a uniform nonscaled DA fabricated in the same process, the stage-scaled amplifier achieves the same output power with higher collector efficiency and PAE over the entire measured frequency range. [ABSTRACT FROM AUTHOR]

In this paper, an area-efficient 4-stage dual-fed distributed power amplifier (DPA) implemented in a 0.35 μm Complementary Metal Oxide Semiconductor (CMOS) process is presented. To effectively reduce the area of the circuit, techniques such as using multilevel inductors and closely-placing conventional spiral inductors are employed. Additionally, a novel technique based on stacking inductors one on top of others is implemented. Based on these techniques, a 32% area reduction is achieved compared to a conventional design without a noticeable performance degradation. This reduction could be further exploited as the number of stages of the dual-fed DPA increases. [ABSTRACT FROM AUTHOR]