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Doping of HfO2 thin films is a powerful means for stabilizing ferroelectricity in this material. Yet, the amount of doping is critical to achieving the best ferroelectric response. This article investigates the impact of the Si doping content on the key performance metrics of ferroelectric field-effect transistors (FeFETs). We report on its considerable effect on the memory window, switching uniformity and steepness, number of intermediate conductance states, and data retention. Based on the experimental results, we introduce simple figures of merit for a rapid assessment of the FeFET performance. Finally, we identify an important tradeoff between the abovementioned properties as a function of the dopant content and discuss possibilities for specialized device design for nonvolatile memory applications and potential neuromorphic devices based on FeFETs.

In this work, we study and characterize the layout-induced device strain and its impact on RF performance of 22-nm-ultrathin body and buried oxide fully depleted silicon-on-insulator (UTBB FDSOI) P-channel field-effect transistor (PFET). This will help in boosting and optimizing the RF performance for the targeted application. With shrinking device dimensions, conventional stress liners and embedded stressors used in strain-engineered CMOS devices become less effective. Therefore, intrinsically strained materials, such as compressively strained SiGe, are widely used to boost the holes’ mobility in the channel. The stress level depends on both the manufacturing process and device geometry, and the optimization of these leads to improved dc and RF performances of PFET devices. We hereby study various layout parameters, such as width and length of the active region, contacted poly pitch, number of fingers, and source/drain contact, to maximize the channel uniaxial strain parallel to the current flow direction and, thus, improve the electrical performances. The studied layout parameters are then applied on sliced-active (RX) structures, which enables to achieve up to 30% improvement of both ${f}_{T}$ and ${f}_{\text {MAX}}$ parameters of SiGe PFET with respect to a reference device. This also allows reducing the parasitic capacitance without significantly degrading the dc performance. The device strain modeling and physical characterization were conducted through the finite-element method (FEM) and nanobeam electron diffraction (NBED) in the transmission electron microscopy (TEM), respectively.

Long data retention is a critical requirement for many of the potential applications of HfO2-based ferroelectric field-effect transistors (FeFETs). However, methods for its rapid assessment are still missing. In this article, we report a detailed investigation of the retention and switching properties of FeFETs fabricated in the 28-nm high- ${k}$ metal gate technology. We identify a clear correlation between the two properties and propose a method for fast prediction of the device retention behavior, which can be easily adopted to judge different fabrication processes. Finally, we extend the validity of the method to a direct assessment of disturb-free operating conditions, which may be particularly valuable for FeFET array operation.

Ferroelectric field-effect transistors (FeFETs) with a single gate structure and using the newly discovered ferroelectric hafnium oxide as an active material are attracting considerable interest for nonvolatile memory devices. However, such FeFETs struggle to achieve a large separation between the two logic states (memory window, MW) because of the thickness limitations of the ferroelectric film. Moreover, they are affected by detrimental disturbs coming from the read operation because of the shared write and read paths. Therefore, significant performance improvements are needed for the device to compete with established memory technologies like flash. Here, we present an asymmetric double-gate FeFET structure, where only one gate stack comprises the ferroelectric layer. We propose a novel read operation at the non-ferroelectric gate and demonstrate an amplified MW exceeding 12 V thanks to the enhanced body effect factor and the increased sensitivity of the transfer characteristics to the ferroelectric polarization. As a result, the above physical limitation is circumvented, thus by far outperforming the MW values reported in the literature. Based on this, we implement the multi-level cell storage featuring 4 bits per cell and stable data retention. Finally, an essential benefit originating from the separated write and read paths in our structure is exploited to demonstrate the fully disturb-free read operation. Besides memory, this could be particularly favorable for those neuromorphic and in-memory computing concepts with an occasional update of the stored variable but a very frequent read.

With the discovery of ferroelectricity in HfO 2 based thin films and the co-integration of ferroelectric field effect transistors (FeFET) into standard high-k metal gate (HKMG) CMOS platforms, the FeFET has emerged from a theoretical dream to an applicable reality. This paper summarizes the status of GLOBALFOUNDRIES FeFET technology and some of its potential applications. We show excellent 0.12µm2 SRAM yields of our mature 28nm CMOS platform, with co-integrated FeFETs, exhibiting a solid memory window of 1.4V. In contrast to conventional embedded memory cells, the FeFET can be integrated like a regular 26A EOT transistor, exhibiting two reversibly programmable VT states, while offering full design flexibility. We show state of the art across wafer VT variability of the programmed and erased states of the FeFETs and discuss its layout-dependence. Embedded size-competitive FeFETs already allow solid separation of the memory states, approaching a mature 6Sigma distribution. Reasonable endurance and stable data retention are demonstrated. Moreover, an outlook of this technology beyond the von Neumann computing will be discussed, considering some of the various applications of this new, versatile device.