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Germanium is a promising material for the laser that can be monolithically integrated on Si complementary metal-oxide-semiconductor platform and has emission wavelength of 1550 nm for optical interconnect. To obtain significant optical gain, it is necessary to achieve high n-type doping concentration level, while avoiding the damage to Ge crystalline quality. In this paper, we report an ex-situ phosphorus diffusion doping of Ge film, based on low-temperature phosphosilicate glass (PSG) pre-deposition process such as spin-on-glass and sub-atmospheric chemical vapor deposition (SACVD) methods. Closely related to optical gain properties of Ge for Ge-on-Si laser application, the photoluminescence characteristics of Ge epitaxial film after P diffusion doping were investigated. In particular, SACVD-processed PSG deposited directly on Ge film without any Si capping layer successfully led to high phosphorus doping concentration of ∼1019 cm−3 deep inside Ge and dramatically enhanced photoluminescence intensity by more than 10 times compared to intrinsic Ge film. By using the SACVD-PSG based P doping process, we developed an inverted-rib Ge waveguide structure for more effective optical gain. In the inverted-rib Ge structure, the mode will be positioned upward and stay relatively away from the Ge-Si interface where many dislocations are located and, as a result, we can expect less optical loss due to scattering and the overall higher mode gain. As a very promising preliminary result, from optical-pumping of the inverted-rib Ge, a threshold-like behavior starting at 18 kW/cm2 and amplified spontaneous emission around 1570 nm were demonstrated.

We report an ex-situ phosphorus diffusion doping for germanium integrated photonic devices on silicon chip. Here, phosphorus oxychloride (POCl3)-based phosphosilicate glass is chosen for n-type diffusion. As an alternative process to the in-situ P doping during Ge epitaxy so far reported for Ge laser prototyping, the presented external P-diffusion method demonstrates photoluminescence (PL) emission enhancement of Ge-on-Si. The PL enhancement, along with the P secondary ion mass spectroscopy profile in Ge, clearly indicates that our ex-situ diffusion method to form n-type Ge has a significant potential for Ge active device fabrication as an enabling technology. It should be also noted that PL quenching is observed at high temperature diffusion processes which is induced by intermixing at the Ge and Si interface. The presented ex-situ P-diffusion process can serve as a template to monolithically integrate Ge devices such as not only light sources but modulators and photodetectors on Si complementary metal-oxde-semiconductor platform, as it may tailor device-specific pn junctions.

We developed open-cell copper foams with uniformly distributed nanopores by chemical dealloying of Al2Cu samples that were synthesized by a powder process. High-energy ball-milling was utilized for mechanical alloying of aluminum and copper powders and either hot rolling or hot pressing was then employed to consolidate the ball-milled powders into sheets or pellets. Subsequent dealloying aluminum from the samples produced nanoporous copper foams. X-ray diffractometry and scanning electron microscopy confirmed the uniform formation of Al2Cu and aluminum phases prior to dealloying, and the introduction of nanoporous structures after dealloying. [doi:10.2320/matertrans.M2014068]

A large single-grain Pb(Zr,Ti)O3 (PZT) film was integrated into low-temperature polycrystalline silicon (poly-Si) thin-film transistors fabricated on a glass substrate. The poly-Si was crystallized by NiSi2 seed-induced lateral crystallization (SILC). The SILC poly-Si had a superior electrical performance to other crystallization methods as a result of its high crystalline volume fraction (91.2%). PZT with a perovskite phase is generally obtained at 800 °C, which is not suitable for glass substrates. Therefore we developed a low-temperature perovskite PZT using an artificially controlled seeding process. An artificially controlled nucleation seed was first formed by rapid thermal annealing at 650 °C in 1 s pulses and a single seed was then grown in a tube furnace at 550 °C for 2 h. The resulting device had a large memory window (3.5 V) and a highly reliable memory operation. This approach could potentially be applied to the next generation of non-volatile memory devices as well as in integrated system-on-glass displays.

A compressively stressed polycrystalline-silicon (poly-Si) thin-film transistor (TFT) was successfully demonstrated on a tensile stressed glass substrate. The layer of a-Si:H/bare glass was annealed for 45 h with a sharp annealing and a slow cooled condition in order to form compressive strain on the a-Si:H film. Then, the a-Si:H was crystallized by NiSi2 seed-induced lateral crystallization having (110) preferred texture, and the top-gated TFT was fabricated. The electrical properties were excellent comparing with the strain-free poly-Si TFT, and especially the field-effect mobility increased 9.3 times higher.

We present designs for stacked Si microring couplers for compact exchange of optical signals between photonic planes separated vertically in excess of 10 μm with wide bandwidth and flat pass-bands.

We present a design for a low-footprint optical interconnect that efficiently couples between two photonic planes with significant vertical separation up to 10 μm and a footprint less than 10 μm × 10 μm. The device may be used to connect between deposited passive waveguide devices in the upper plane and active devices on a substrate. The design is based on a vertical stack of coupled ring resonators. We demonstrate basic feasibility of the design and estimates of device performance based on numerical simulation. A matrix model is presented to estimate spectral performance as a function of several design parameters.

Controlling the grain-boundary of ferroelectric thin-film is significantly important for realizing ultimate multibit-FeRAM, when a ferroelectric thin-film deposited by radio-frequency reactive magnetron sputtering is integrated into silicon-based devices. A novel crystal-growth process of a ferroelectric thin-film using platinum (Pt)-seed matrix is developed for dividing the nucleation and growth of PbZr0.52Ti0.48O3 (PZT), which cannot be observed in the classical nucleation and growth of PZT. Locating artificial nucleation seeds using Pt-seeds in a desirable position enables one to obtain a large single-grain PZT (~40 μm) that is large enough to fabricate a field-effect transistor (FET)-type FeRAM. The fabricated FeRAM with a Pt/PZT/ZrTiO4(ZTO)/p-Si structure showed a wide memory window (~1.8 V), low operation voltage (~6 V), ultra-fast Program/Erase (P/E) switching speed (~10–7 s), and a stable multibit operation controlled by local polarization. In addition, the FeRAM showed no degradation even after cycling the P/E more than 1011 times in all multibit states, and the retention time was expected to have a wide memory window even after 10 years in all multibit states. These characteristics show great potential for the multi-bit FeRAM, which is difficult to expect a reliable operation with large grain-boundaries.

We demonstrate Ge metal-semiconductor-metal (MSM) photodetectors monolithically integrated with silicon-oxynitride (SiO x N y ) waveguides. Ge photodetector layer was epitaxially grown by an UHVCVD system and thewaveguide was formed on top of the Ge photodetector by PECVD. The entire process is found to be completelycompatible with the standard CMOS process. Light is evanescently coupled from silicon-oxynitride (SiO x N y )waveguide to the underlying Ge photodetector, achieving at 2 V a responsivity of 0.33 A/W at 1.55 µ m wavelengthand a dark current of 1 µ Afora10µ m long photodetector.Keywords: Photodetectors, Photonic integrated circuits, Optical interconnects, Optoelectronics 1. INTRODUCTION Integration of optical components on a Si platform is expected to reduce the cost of optical interconnects andenhance the Complementary Metal-Oxide-Semiconductor (CMOS) electronic circuit performance. Optical inter-connect technology, in the form of “ber optics, have dominated the long distance applications for twenty years,in the areas such as telephone, Internet, Wide Area Network and Local Area Networks. Such applications haveunlimited distance-bandwidth product as compared with electrical cables, with a minimal loss in signal andalmost no cross-talk. However, ultra-short-distance optical applications are gathering new focus

To achieve grid parity, photovoltaic (PV) technologies must reduce the production cost of PV modules to well below $1/Wp. In crystalline Si (c-Si) solar cells the cost of raw Si wafers is over 40% of the module cost. There is an industry wide push to reduce the active Si content of the cell through a combination of thinner wafers and increased cell efficiency. However, cell manufacturers are struggling to reduce the wafer thickness below 150μm as there are no economically viable technologies for manufacturing very thin Si wafers and such thin silicon wafers impose stringent handling requirements as wafer breakage and yield loss impact final module cost. In this paper, we demonstrate for the first time, a novel exfoliation technology capable of producing large area (6-in diameter) 25μm thin flexible mono c-Si foils that will dramatically change the cost structure and form factor of high efficiency-Si solar cells without the yield losses and handling issues that are a major problem for traditional thin Si wafers. An un-optimized single side heterojunction cell has been formed with a 25μm exfoliated c-Si foil, which shows an efficiency of 12.5%. The cell characteristics of a 25μm thin c-Si cell with intrinsic a-Si passivation will be presented in the paper. Simulations show that with optimized texturing of the foil and passivation, higher efficiencies (20%) can be attained. Depending on the starting wafer or ingot thickness a final cell cost of between $0.46/Wp to $0.50/Wp can be achieved compared to $1.1/Wp for today's commercial thick crystalline Si cells.

We propose a new InP-based comb generator for optical OFDM transmission. The device integrates a Mach-Zehnder modulator inside an amplified ring. We demonstrate a 6-line frequency comb which is tunable in wavelength and spacing.

We investigate boron transient enhanced diffusion (TED) and series resistance in SiGe/Si heterojunction channel pMOSFET. The stress gradient at the SiGe/Si interface near the gate edge in high Ge concentrations are found to determine boron TED as well as extension junction shape, which has a significant impact on the parasitic LDD and source/drain (S/D) series resistance. In addition, high Ge concentrations in the epitaxial SiGe layer on top of Si substrate result in a high sheet resistance during a 1000°C/5s rapid thermal processing (RTP), which is mainly due to alloy scattering and interface roughness scattering.

Multilevel thin film processing, global planarization and advanced photolithography enables the ability to integrate complimentary materials and process sequences required for high index contrast photonic components all within a single CMOS process flow. Developing high performance photonic components that can be integrated with electronic circuits at a high level of functionality in silicon CMOS is one of the basic objectives of the EPIC program sponsored by the Microsystems Technology Office (MTO) of DARPA. Our research team consisting of members from: BAE Systems, Alcatel-Lucent, Massachusetts Institute of Technology, Cornell University and Applied Wave Research reports on the latest developments of the technology to fabricate an application specific, electronic-photonic integrated circuit (AS_EPIC). Now in its second phase of the EPIC program, the team has designed, developed and integrated fourth order optical tunable filters, both silicon ring resonator and germanium electro-absorption modulators and germanium pin diode photodetectors using silicon waveguides within a full 150nm CMOS process flow for a broadband RF channelizer application. This presentation will review the latest advances of the passive and active photonic devices developed and the processes used for monolithic integration with CMOS processing. Examples include multilevel waveguides for optical interconnect and germanium epitaxy for active photonic devices such as p-i-n photodiodes and modulators.

We present waveguide-coupled, Ge-based photodetectors and electro-absorption (EA) modulators for active Si integrated photonics. These devices offer high optoelectronic performance and compatibility with Si CMOS process.

Ge p-i-n photodetectors monolithically integrated with silicon oxynitride and silicon nitride waveguides on Si CMOS platform are presented. The devices demonstrated high efficiency (~1.08 A/W) and high-speed (>14 Gbit/s) performances at low bias.

The complete integration of photonic devices into a CMOS process flow will enable low cost photonic functionality within electronic circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, Cornell University, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application specific, electronic-photonic integrated circuit (AS-EPIC). The first phase of the program was dedicated to photonics device designs, CMOS process flow integration, and basic electronic functionality. We will present the latest results on the performance of waveguide integrated detectors, and tunable optical filters.

We demonstrate waveguide-integrated Ge p-i-n photodetectors on Si with vertical coupling and butt-coupling schemes. A responsivity of >1.0 A/W around 1550 nm and a bandwidth of several GHz were achieved in both cases.

We present selectively grown Ge p-i-n photodetectors coupled to high index contrast Si(core)/SiO2(cladding) waveguides on a silicon-on-insulator (SOI) platform. Two coupling schemes, namely butt-coupling and vertical coupling, were demonstrated in this study. With the butt-coupling scheme we have achieved a high responsivity of 1.0 A/W at 1520 nm and a 3 dB bandwidth greater than 4.5 GHz at 1550 nm. With the vertical coupling scheme, where the light couples from a Si waveguide evanescently to the Ge detector on top of it, a responsivity of 0.22 A/W and a 3 dB bandwidth of ~1.5 GHz have been demonstrated at 1550 nm. The devices were fabricated on a standard 180 nm industrial complementary metal oxide semiconductor production (CMOS) line, and can be integrated with CMOS circuitry for electronic and photonic integrated circuits

The optical components industry stands at the threshold of a major expansion that will restructure its business processes and sustain its profitability for the next three decades. This growth will establish a cost effective platform for the partitioning of electronic and photonic functionality to extend the processing power of integrated circuits. BAE Systems, Lucent Technologies, Massachusetts Institute of Technology, and Applied Wave Research are participating in a high payoff research and development program for the Microsystems Technology Office (MTO) of DARPA. The goal of the program is the development of technologies and design tools necessary to fabricate an application-specific, electronicphotonic integrated circuit (AS-EPIC). As part of the development of this demonstration platform we are exploring selected functions normally associated with the front end of mixed signal receivers such as modulation, detection, and filtering. The chip will be fabricated in the BAE Systems CMOS foundry and at MIT's Microphotonics Center. We will present the latest results on the performance of multi-layer deposited High Index Contrast Waveguides, CMOS compatible modulators and detectors, and optical filter slices. These advances will be discussed in the context of the Communications Technology Roadmap that was recently released by the MIT Microphotonics Center Industry Consortium.

We demonstrate a fully CMOS processed Ge p-i-n photodetector integrated with a Si waveguide on a SOI platform with a high responsivity of 1.0 A/W at lambda=1520 nm, and a 3 dB bandwidth of >4.5 GHz measured at lambda=1550 nm

SiOxNy waveguide-based optical clocking signal distributions with 64 nodes were fabricated in 3mmx5mm Silicon chip area. The network circuitry consists of 3-levels of waveguide H-trees with decreasing bending radii. A novel splitter structure demonstrates < 3% loss at split and 49:51 power splitting uniformity.

In this work, the authors fabricated 1-transistor ferroelectric random access memory based on polycrystalline-silicon (poly-Si) on a glass substrate. A novel technique was used to form a large single-grained Pb(Zr,Ti)O3 (PZT) layer as the gate insulator. Generally, the crystallization temperature of PZT is 800 °C, which is beyond the limits for a glass substrate; however, here the authors developed a selectively nucleated lateral crystallization technique to minimize the crystallization temperature and grow 40 μm grains of PZT. Pt layer using rapid thermal annealing at 650 °C for a short time, and grew a single seed by tube-furnace at 550 °C for 2 h. Our device demonstrated excellent electrical properties with long retention time, which only decreased by 9% after 104 s, and good fatigue characteristics, which only decreased by 4% after 104 cycles.

A ferroelectric-flash (F-flash) memory cells having a metal-ferroelectric-nitride-oxynitride-silicon structure are demonstrated, and the ferroelectric materials were perovskite-dominated Pb(Zr,Ti)O3 (PZT) crystallized by Pt gate electrode. The PZT thin-film as a blocking layer improves electrical and memorial performance where programming and erasing mechanism are different from the metal-ferroelectric-insulator-semiconductor device or the conventional silicon-oxide-nitride-oxide-silicon device. F-flash cells exhibit not only the excellent electrical transistor performance, having 442.7 cm2 V−1 s−1 of field-effect mobility, 190 mV dec−1 of substhreshold slope, and 8 × 105 on/off drain current ratio, but also a high reliable memory characteristics, having a large memory window (6.5 V), low-operating voltage (0 to −5 V), faster P/E switching speed (50/500 μs), long retention time (>10 years), and excellent fatigue P/E cycle (>105) due to the boosting effect, amplification effect, and energy band distortion of nitride from the large polarization. All these characteristics correspond to the best performances among conventional flash cells reported so far.

We studied evanescent wave coupling behavior between low index-contrast upper-level waveguides and thin-film Si and Ge photodetectors on SOI and germanium-on-insulator (GOI) substrates, respectively. We present a simple and intuitive leaky-mode phase-matching model using a ray-optics approach to determine the conditions for efficient coupling, both in 2D and 3D structures. It is shown that the presence of leaky modes that are phase-matched between the waveguide and the Si or Ge photodetector layer is the key condition for efficient coupling. Our approach was compared to other methods, such as finite-difference time domain (FDTD)/beam propagation method (BPM) and mode analysis. We report that, depending on the way a waveguide photodetector device is designed, waveguide-to-photodetector coupling efficiency may or may not be critically sensitive to design parameters, such as the photodetector layer thickness. As an example, the stark contrast of coupling behavior in the two most popular Ge photodetector stru...

A waveguide-integrated photodetector provides a small-footprint, low-capacitance design that overcomes the bandwidth-efficiency trade-off problem of free space optics. High performance silicon devices are critical to the emergence of electronic-photonic integrated circuits on the complementary metal oxide semiconductor platform. We have fabricated vertical p-i-n silicon photodetectors that are monolithically integrated with compact silicon oxynitride channel waveguides. We report over 90% coupling efficiency of 830 nm light from the silicon oxynitride (SiOxNy) channel waveguide to the silicon photodetector. We analyze the dependence of coupling on waveguide index by comparing coupling from low index-contrast waveguides and high index-contrast waveguides.

Photonic systems based on complementary metal oxide semiconductor (CMOS) technology require the integration of passive and active photonic devices. The integration of waveguides and photodetector is one of the most important technologies. We report a Ge p-i-n photodetector that is monolithically integrated with silicon oxynitride and silicon nitride waveguides. All processes and materials are CMOS compatible and can be implemented in the current integrated circuit process technology. The small size of the devices results in low absolute dark current. The waveguidecoupled Ge devices show high efficiency (~90%) over a wide range of wavelengths well beyond the direct band gap of Ge, resulting in a responsivity of 1.08 A/W for 1550 nm light. The device speed of 7.2 GHz at 1V reverse bias is strongly affected by the capacitance of the probe pads. The high-performance of the devices at low voltage (/= 1V) facilitates the integration with CMOS circuits.