37 results on '"Doria, Rodrigo Trevisoli"'
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2. Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors
3. Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization
4. On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration
5. In-depth low frequency noise evaluation of substrate rotation and strain engineering in n-type triple gate SOI FinFETs
6. Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors
7. Low-frequency noise and effective trap density of short channel p- and n-types junctionless nanowire transistors
8. A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors
9. Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates
10. Trap density characterization through low-frequency noise in junctionless transistors
11. Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS
12. Effect of Substrate Bias and Temperature Variation in the Capacitive Coupling of SOI UTBB MOSFETs
13. Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation
14. UTBB Thermal Coupling Analysis in Technological Node Level
15. Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors
16. Substrate Effect Evaluation by the Analysis of Intrinsic Capacitances in SOI UTBB Transistors
17. Effect of Substrate Bias and Temperature Variation in the Capacitive Coupling of SOI UTBB MOSFETs.
18. Back bias influence on low-frequency noise of n-type nanowires SOI MOSFETs
19. Physical Insights on the Dynamic Response of SOI n- and p-Type Junc-tionless Nanowire Transistors
20. Static and dynamic compact analytical model for junctionless nanowire transistors
21. A New Method for Series Resistance Extraction of Nanometer MOSFETs
22. Junctionless nanowire transistors operation at temperatures down to 4.2 K
23. Non-linearity analysis of triple gate SOI nanowires MOSFETS
24. Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors
25. Errata to “Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors” [Dec 12 3510-3518]
26. Origin of the Low-Frequency Noise in the Asymmetric Self-Cascode Structure Composed by Fully Depleted SOI nMOSFETs.
27. Asymmetric self-cascode FD SOI nMOSFETS harmonic distortion at cryogenic temperatures
28. Analysis of harmonic distortion of asymmetric self-cascode association of SOI nMOSFETs operating in saturation
29. Performance of Junctionless Nanowire MOSFET as a Quasi-Linear Resistor
30. Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors
31. Analysis of gate capacitance of n-type junctionless transistors using three-dimensional device simulations
32. Drain current model for junctionless nanowire transistors
33. Threshold voltage in junctionless nanowire transistors
34. Junctionless Multiple-Gate Transistors for Analog Applications
35. Harmonic Distortion of Unstrained and Strained FinFETs Operating in Saturation
36. Operação analógica de transistores de múltiplas portas em função da temperatura.
37. Substrate Bias Influence on the Operation of Junctionless Nanowire Transistors.
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