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1. P-type $\delta$-doping with Diborane on Si(001) for STM Based Dopant Device Fabrication

Author

Škereň, Tomáš, Köster, Sigrun, Douhard, Bastien, Fleischmann, Claudia, and Fuhrer, Andreas

Subjects
Condensed Matter - Mesoscale and Nanoscale Physics
Abstract

Hydrogen resist lithography using the tip of a scanning tunneling microscope (STM) is employed for patterning p-type nanostructures in silicon. For this, the carrier density and mobility of boron $\delta$-layers, fabricated by gas-phase doping, are characterized with low-temperature transport experiments. Sheet resistivities as low as $300\thinspace\Omega$ are found. Adsorption, incorporation and surface diffusion of the dopants are investigated by STM imaging and result in an upper bound of 2\,nm for the lithographic resolution which is also corroborated by fabricating a 7.5\,nm wide p-type nanowire and measuring its electrical properties. Finally, to demonstrate the feasibility of bipolar dopant device fabrication with this technique, we prepared a 100\,nm wide pn junction and show that its electrical behavior is similar to that of an Esaki diode., Comment: 19 pages, 5 figures

Published
2019
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12. P-type $��$-doping with Diborane on Si(001) for STM Based Dopant Device Fabrication

Author

��kere��, Tom����, K��ster, Sigrun, Douhard, Bastien, Fleischmann, Claudia, and Fuhrer, Andreas

Subjects
Mesoscale and Nanoscale Physics (cond-mat.mes-hall), FOS: Physical sciences
Abstract

Hydrogen resist lithography using the tip of a scanning tunneling microscope (STM) is employed for patterning p-type nanostructures in silicon. For this, the carrier density and mobility of boron $��$-layers, fabricated by gas-phase doping, are characterized with low-temperature transport experiments. Sheet resistivities as low as $300\thinspace��$ are found. Adsorption, incorporation and surface diffusion of the dopants are investigated by STM imaging and result in an upper bound of 2\,nm for the lithographic resolution which is also corroborated by fabricating a 7.5\,nm wide p-type nanowire and measuring its electrical properties. Finally, to demonstrate the feasibility of bipolar dopant device fabrication with this technique, we prepared a 100\,nm wide pn junction and show that its electrical behavior is similar to that of an Esaki diode., 19 pages, 5 figures

Published
2019
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13. #AiMES2018_20181002_1400_Low-T-SiGe_Porret

Author

Porret, Clement, primary, Hikavyy, Andriy, additional, Granados, Juan Fernando Gomez, additional, Baudot, Sylvain, additional, Vohra, Anurag, additional, Kunert, Bernardette, additional, Douhard, Bastien, additional, Bogdanowicz, Janusz, additional, Schaekers, Marc, additional, Kohen, David, additional, Margetis, Joe, additional, Tolle, John, additional, Lima, Lucas Petersen Barbosa, additional, Sammak, Amir, additional, Scappucci, Giordano, additional, Rosseel, Erik, additional, Langer, Robert, additional, and Loo, Roger, additional

Published
2018
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16. (Invited) Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in Finfet, Stacked Nanowires and Monolithic 3D Integration

Author

Porret, Clement, primary, Hikavyy, Andriy Yakovitch, additional, Gomez Granados, Juan Fernando, additional, Baudot, Sylvain, additional, Vohra, Anurag, additional, Kunert, Bernardette, additional, Douhard, Bastien, additional, Bogdanowicz, Janusz, additional, Schaekers, Marc, additional, Kohen, David, additional, Margetis, Joe, additional, Tolle, John, additional, Lima, Lucas, additional, Sammak, Amir, additional, Scappucci, Giordano, additional, Rosseel, Erik, additional, Langer, Robert, additional, and Loo, Roger, additional

Published
2018
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18. (Invited) Epitaxial CVD Growth of Ultra-Thin Si Passivation Layers on Strained Ge Fin Structures

Author

Loo, Roger, primary, Arimura, Hiroaki, additional, Cott, Daire J., additional, Witters, Liesbeth, additional, Pourtois, Geoffrey, additional, Schulze, Andreas, additional, Douhard, Bastien, additional, Vanherle, Wendy, additional, Eneman, Geert, additional, Richard, Olivier, additional, Favia, Paola, additional, Mitard, Jerome, additional, Mocuta, Dan, additional, Langer, Robert, additional, and Collaert, Nadine, additional

Published
2017
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21. Influence of Doping and Tunneling Interface Stoichiometry on n+In0.5Ga0.5As/p+GaAs0.5Sb0.5 Esaki Diode Behavior

Author

El Kazzi, Salim, primary, Alireza, A, additional, Bordallo, Caio Cesar Mendes, additional, Smets, Quentin, additional, Desplanque, Ludovic, additional, Wallart, Xavier, additional, Richard, Olivier, additional, Douhard, Bastien, additional, Verhulst, Anne, additional, Collaert, Nadine, additional, Merckling, Clement, additional, Heyns, Marc, additional, and Thean, Aaron, additional

Published
2016
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25. Compressively strained SiGe band-to-band tunneling model calibration based on p-i-n diodes and prospect of strained SiGe tunneling field-effect transistors

Author

Kao, Kuo-Hsing, primary, Verhulst, Anne S., additional, Rooyackers, Rita, additional, Douhard, Bastien, additional, Delmotte, Joris, additional, Bender, Hugo, additional, Richard, Olivier, additional, Vandervorst, Wilfried, additional, Simoen, Eddy, additional, Hikavyy, Andriy, additional, Loo, Roger, additional, Arstila, Kai, additional, Collaert, Nadine, additional, Thean, Aaron, additional, Heyns, Marc M., additional, and Meyer, Kristin De, additional

Published
2014
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27. HF-Last Wet Clean in Combination with a Low Temperature GeH4-Assisted HCl In Situ Clean Prior to Si0.8Ge0.2-on-Si Epitaxial Growth

Author

Wostyn, Kurt, primary, Dhayalan, Sathish K., additional, Hikavyy, Andriy, additional, Loo, Roger, additional, Douhard, Bastien, additional, Moussa, Alain, additional, Rondas, Dirk, additional, Kenis, Karine, additional, Mertens, Paul W., additional, Holsteyns, Frank, additional, De Gendt, Stefan, additional, and Profijt, Harald B., additional

Published
2014
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29. Evaluation of the Si0.8Ge0.2-on-Si Epitaxial Quality by Inline Surface Light Scattering: A Case Study on the Impact of Interfacial Oxygen

Author

Wostyn, Kurt, primary, Kenis, Karine, additional, Rondas, Dirk, additional, Loo, Roger, additional, Hikavyy, Andriy Yakovitch, additional, Dhayalan, Sathish, additional, Douhard, Bastien, additional, Mertens, Paul W., additional, Holsteyns, Frank, additional, De Gendt, Stefan, additional, Simpson, Gavin, additional, Bast, Gerhard, additional, and Swaminathan, Karthik, additional

Published
2014
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30. (Invited) Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration

Author

Porret, Clement, Yakovitch, Andriy, Fernando, Juan, Granados, Gomez, Baudot, Sylvain, Vohra, Anurag, Kunert, Bernardette, Douhard, Bastien, Bogdanowicz, Janusz, Schaekers, Marc, Kohen, David, Margetis, Joe, Tolle, John, Lima, Lucas, Sammak, Amir, Scappucci, Giordano, Rosseel, Erik, Langer, Robert, and Loo, Roger

Abstract

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

Published
2018

31. (Invited) Advanced Dielectrics Targeting 2X DRAM MIM Capacitors

Author

Popovici, Mihaela, primary, Swerts, Johan, additional, Aoulaiche, Marc, additional, Redolfi, Augusto, additional, Kaczer, Ben, additional, Kim, Min-Soo, additional, Douhard, Bastien, additional, Delabie, Annelies, additional, Clima, Sergiu, additional, Jurczak, Malgorzata, additional, and Van Elshocht, S., additional

Published
2013
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32. SiGe Band-to-Band Tunneling Calibration based on p-i-n Diodes: Fabrication, Measurement and Simulation

Author

Kao, Kuo-Hsing, primary, Verhulst, Anne, additional, Rooyackers, Rita, additional, Hikavyy, Andriy, additional, Simoen, Eddy, additional, Arstila, Kai, additional, Douhard, Bastien, additional, Loo, Roger, additional, Simoen, Alexey Milenin, additional, Tolle, John, additional, Dekkers, Harold, additional, Machkaoutsan, Vladimir, additional, Maes, Jan, additional, De Meyer, Kristin, additional, Collaert, Nadine, additional, Heyns, Marc, additional, Huyghebaert, Cedirc, additional, and Thean, Aaron, additional

Published
2013
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34. Junction strategies for 1x nm technology node with FINFET and high mobility channel

Author

Horiguchi, Naoto, primary, Zschaetzsch, Gerd, additional, Sasaki, Yuichiro, additional, Kambham, Ajay Kumar, additional, Douhard, Bastien, additional, Togo, Mitsuhiro, additional, Hellings, Geert, additional, Mitard, Jerome, additional, Witters, Liesbeth, additional, Eneman, Geert, additional, Noda, Taiji, additional, Collaert, Nadine, additional, Vandervorst, Wilfried, additional, and Thean, Aaron, additional

Published
2012
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36. The Impact of Dummy Gate Processing on Si-Cap-Free SiGe Passivation: A Physical Characterization Study on Strained SiGe 25% and 45%

Author

Wostyn, Kurt, Ragnarsson, Ake, Schram, Tom, Witters, Liesbeth, Conard, Thierry, Douhard, Bastien, Vanhaeren, Danielle, Holsteyns, Frank, Vandervorst, Wilfried, and Horiguchi, Naoto

Abstract

Si-cap-free SiGe passivation suffers from the potential presence of Ge-oxide in the interlayer prior to high-k deposition. Most of the advanced transistor designs use a replacement metal gate (RMG) integration scheme. The evolution of the Ge-content in the chemical oxide formed on SiGe channels with [Ge] = 25 and 45% was followed after the oxidation of pristine SiGe and compared to SiGe that was exposed to a short-loop flow mimicking an RMG integration scheme. The Ge content of the chemical oxide and SiGe virtual substrate was found to be strongly dependent on the spike anneal temperature. Also the roughness of the interlayer was found to increase. The impact of a TMAH-based clean prior to chemical oxide formation was also studied. Finally, the observations are explained qualitatively as a combination of the behavior for Si and Ge.

Published
2017

37. Biaxial and Uniaxial Compressive Stress Implemented in Ge(Sn) pMOSFET Channels by Advanced Reduced Pressure Chemical Vapor Deposition Developments

Author

Vincent, Benjamin, primary, Gencarelli, Federica, additional, Lin, Denis, additional, Nyns, Laura, additional, Richard, Olivier, additional, Bender, Hugo, additional, Douhard, Bastien, additional, Moussa, Alain, additional, Merckling, Clement, additional, Witters, Liesbeth, additional, Vandervorst, Wilfried, additional, Loo, Roger, additional, Caymax, Matty, additional, and Heyns, Marc, additional

Published
2011
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40. Micro Probe Carrier Profiling of Ultra-shallow Structures in Germanium

Author

Clarysse, Trudo Henri., primary, Moussa, Alain, additional, Parmentier, Brigitte, additional, Eyben, Pierre, additional, Douhard, Bastien, additional, Vandervorst, Wilfried, additional, Nielsen, Peter F., additional, Lin, Rong, additional, Petersen, Dirch H., additional, Wang, Fei, additional, and Hansen, Ole, additional

Published
2009
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43. Influence of Doping and Tunneling Interface Stoichiometry on n+In0.5Ga0.5As/p+GaAs0.5Sb0.5 Esaki Diode Behavior

Author

Kazzi, Salim El, Alireza, A, Cesar, Caio, Bordallo, Mendes, Smets, Quentin, Desplanque, Ludovic, Wallart, Xavier, Richard, Olivier, Douhard, Bastien, Verhulst, Anne, Collaert, Nadine, Merckling, Clement, Heyns, Marc, and Thean, Aaron

Abstract

In this work, we study the influence of molecular beam epitaxy (MBE) growth parameters on the behavior of a staggered band gap n+In0.5Ga0.5As/p+GaAs0.5Sb0.5 Esaki diodes. We first first show that a careful doping is required to avoid any crystal defects. Then the influence of the doping concentration on the Band to Band Tunneling (BTBT) is discussed. At the end, we show that a careful monitoring of the MBE growth allows thin and abrupt n+In0.5Ga0.5As/p+GaAs0.5Sb0.5 tunneling interfaces where BTBT behavior in this case is independent of the III-V interface stoichiometry

Published
2016

44. A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond.

Author

Ritzenthaler, Romain, Schram, Tom, Spessot, Alessio, Caillat, Christian, Aoulaiche, Marc, Cho, Moon Ju, Noh, Kyoung Bong, Son, Yunik, Na, Hoon Joo, Kauerauf, Thomas, Douhard, Bastien, Nazir, Aftab, Chew, Soon Aik, Milenin, Alexey P., Altamirano-Sanchez, Efrain, Schoofs, Geert, Albert, Johan, Sebai, Farid, Vecchio, Emma, and Paraschiv, Vasile

Subjects
COMPLEMENTARY metal oxide semiconductors, DYNAMIC random access memory, STRAY currents, LOGIC circuits, METAL oxide semiconductor field-effect transistors, THERMAL stability
Abstract

In this paper, a low-cost and low-leakage gate-first high- \(k\) metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO2 coupled with Al2O3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 \(\mu \) A/ \(\mu \) m can be obtained for an OFF-state current of \(10^{-10}\) A/ \(\mu \) m, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability. [ABSTRACT FROM AUTHOR]

Published
2014
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45. HF-Last Wet Clean in Combination with a Low Temperature GeH4-Assisted HCl In Situ Clean Prior to Si0.8Ge0.2-on-Si Epitaxial Growth

Author

Wostyn, Kurt, Dhayalan, Sathish K., Hikavyy, Andriy, Loo, Roger, Douhard, Bastien, Moussa, Alain, Rondas, Dirk, Kenis, Karine, Mertens, Paul W., Holsteyns, Frank, De Gendt, Stefan, and Profijt, Harald B.

Abstract

Epitaxial growth requires a clean starting surface for the growth of a high-quality crystalline layer. For epitaxy on Si, an HF-last wet clean followed by an in-situ high-temperature hydrogen bake is the reference pre-epi clean sequence to obtain an oxygen-free surface [1, 2]. The temperature required to remove all residual oxygen also makes the surface atoms mobile, resulting in reflow. The high temperatures used during the H2-bake can also result in intolerable doping profile changes. A lower temperature pre-epi clean sequence is required to avoid this reflow, especially when moving away from Si. In addition the high temperatures needed during a H2-bake would result in the relaxation of high mobility channels, e.g. strained Si1-xGex or III-V materials [3]. Several low temperatures pre-epi cleaning solutions have been proposed in the past, e.g. GeH4-assisted H2-bake [4] or more recently, a GeH4-assisted HCl clean [5]. In this study we looked at the interaction between HF-last wet clean and the in-situ GeH4-assisted HCl clean prior to Si0.8Ge0.2-on-Si epitaxy.

Published
2014
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46. Simulation of the Phosphorus Profiles in a c-Si Solar Cell Fabricated Using POCl3 Diffusion or Ion Implantation and Annealing.

Author

Florakis, Antonios, Janssens, Tom, Posthuma, Niels, Delmotte, Joris, Douhard, Bastien, Poortmans, Jef, and Vandervorst, Wilfried

Abstract

Abstract: In this paper, we present the development of accurate process simulations for the processes leading to the formation of the n-type (phosphorus doped) regions in high efficiency crystalline silicon solar cells. We consider the Phosphorus profile formation either using POCl3 diffusion or by ion implantation; the results are applicable for the formation of the Front Surface Field, emitter, as well as the Back Surface Field regions. The main focus in this paper was on the modeling of the oxidation process, both in terms of the oxide growth rate dependence on the substrate doping concentration and on the doping diffusion enhancement due to oxidation. The detailed description of these two phenomena allows for the accurate prediction of the doping distribution and the oxide thickness, enabling the engineering of the junction formation based on process simulations. For the model calibrations we have used both POCl3 and Phosphorus ion implanted samples, annealed at various temperatures, durations and ambient conditions (oxidizing or inert), so as to quantify the effect of transient and oxidation enhanced diffusion and dopant enhanced oxidation. [Copyright &y& Elsevier]

Published
2013
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48. Material Studies on Si:C Epitaxial Films Grown by CVD

Author

Dhayalan, Sathishkumar, Loo, Roger, Rosseel, Erik, Yakovitch, Andriy, Shimura, Yosuke, Nuytten, Thomas, Richard, Olivier, Bender, Hugo, Douhard, Bastien, and Vandervorst, Wilfried

Abstract

We report the material properties of epitaxial Si:C in terms of layer defectivity and carbon substitutionality in view of its use as Source/Drain stressors for nMOSFET devices. Our discussion includes a comparison of disilane versus trisilane as Si precursor. The expected increase in defectivity with increasing carbon content is followed by an epitaxial breakdown (between 2.3% and 5% total C). The increase in defectivity is attributed to the formation of non-stoichiometric Si-C defect complexes. Raman spectroscopic studies revealed the presence of both random and ordered C distributions in the Si:C lattice. A correlation between these ordered distributions and defect structures is presented. The material properties are affected by both process conditions and the details of the process sequence. Typically, a single step deposition process results in a more ordered C structure while a cyclic deposition and etch (CDE) process results in a lower defectivity and an enhanced C substitutionality.

Published
2014

49. Evaluation of the Si0.8Ge0.2-on-Si Epitaxial Quality by Inline Surface Light Scattering: A Case Study on the Impact of Interfacial Oxygen

Author

Wostyn, Kurt, Kenis, Karine, Rondas, Dirk, Loo, Roger, Yakovitch, Andriy, Dhayalan, Sathish, Douhard, Bastien, Mertens, Paul W., Holsteyns, Frank, Gendt, Stefan De, Simpson, Gavin, Bast, Gerhard, and Swaminathan, Karthik

Abstract

Inline light scattering measurements are frequently used to determine wafer quality and cleanliness. In this paper we will show how this technique can be extended to determine the crystalline quality after hetero-epitaxy. Misfits on the surface of the epitaxial layer cause increased surface light scattering. The Si0.8Ge0.2-on-Si epitaxial quality has been evaluated by surface light scattering. A correlation is observed with the controlled variation of the interfacial oxygen between the Si substrate and epitaxial Si0.8Ge0.2.

Published
2014

50. Low‐Temperature Selective Growth of Heavily Boron‐Doped Germanium Source/Drain Layers for Advanced pMOS Devices.

Author

Porret, Clement, Vohra, Anurag, Nakazaki, Nobuya, Hikavyy, Andriy, Douhard, Bastien, Meersschaut, Johan, Bogdanowicz, Janusz, Rosseel, Erik, Pourtois, Geoffrey, Langer, Robert, and Loo, Roger

Subjects
OHMIC contacts, CHEMICAL vapor deposition, GERMANIUM, BORON, CARRIER density, ELECTRIC lines, CONSTRUCTION materials
Abstract

The peculiarities of heavily boron‐doped germanium, selectively grown at low temperature by means of a cyclic deposition and etch chemical vapor deposition process, are investigated through the analysis of the structural and electrical material properties. The incorporation of B in Ge can exceed 6 × 1020 cm−3, close to a factor 100 above the solubility limit, without any significant degradation of the Ge:B crystalline quality, although high B‐doping induces an unwanted contraction of the Ge lattice. Micro‐Hall effect measurements and the multiring circular transmission line method are used to evaluate the active carrier concentrations and resistivities of Ti/Ge:B contacts. Even though the resistivity of as‐grown layers saturates for chemical B concentrations approaching 1 × 1021 cm−3 and increases beyond that level, a contact resistivity below 3 × 10−9 Ω cm2 is obtained for the highest active doping concentration, showing that a compromise must be found to decrease the total contact resistance. Finally, first principles simulations are used to understand dopant deactivation mechanisms in the Ge:B system. In conclusion, the formation of boron‐interstitial clusters is most likely the cause for electrical performance degradation at high doping values. [ABSTRACT FROM AUTHOR]

Published
2020
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