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The increasing number of distributed power generation systems (DPGSs) is changing the traditional organization of the electrical network. An important part of these DPGSs is based on renewable energy sources. In order to guarantee an efficient integration of renewable-based generation units, grid codes must be fulfilled. Their most demanding requirements, such as low-voltage ride-through and grid support, need a really fast transient response of the power electronics devices. In this manner, the current controller speed is a key point. This paper proposes a methodology to assess and optimize the transient response of proportional-resonant current controllers. The proposed methodology is based on the study of the error signal transfer function roots by means of pole–zero plots. Optimal gains are set to achieve fast and nonoscillating transient responses, i.e., to optimize the settling time. It is proved that optimal gain selection results from a tradeoff between transients caused by reference changes and transients caused by changes at the point of common coupling. Experimental results obtained by means of a three-phase voltage source converter prototype validate the approach. Short transient times are achieved even when tests emulate very demanding realistic conditions: a +90^\circ phase-angle jump in the current reference and a “type C” voltage sag at the point of common coupling. [ABSTRACT FROM PUBLISHER]

The following two types of resonant controllers are mainly employed to obtain high performance in voltage-source converters: 1) proportional + resonant (PR) and 2) vector proportional + integral (VPI). The analysis and design of PR controllers is usually performed by Bode diagrams and phase-margin criterion. However, this approach presents some limitations when resonant frequencies are higher than the crossover frequency defined by the proportional gain. This condition occurs in selective harmonic control and applications with high reference frequency with respect to the switching frequency, e.g., high-power converters with a low switching frequency. In such cases, additional 0-dB crossings (phase margins) appear; therefore, the usual methods for simple systems are no longer valid. In addition, VPI controllers always present multiple 0-dB crossings in their frequency response. In this paper, the proximity to the instability of PR and VPI controllers is evaluated and optimized through Nyquist diagrams. A systematic method is proposed to obtain the highest stability and avoidance of closed-loop anomalous peaks: it is achieved by the minimization of the inverse of the Nyquist trajectory distance to the critical point, i.e., the sensitivity function. Finally, several experimental tests, including an active power filter that operates at a low switching frequency and compensates harmonics up to the Nyquist frequency, validate the theoretical approach. [ABSTRACT FROM PUBLISHER]

The multilevel multiphase technology combines the benefits of multilevel converters and multiphase machines. Recently, a new multilevel multiphase space vector pulsewidth modulation algorithm that is valid for any number of levels and phases was developed. In this paper, a generic digital VHDL module for such an algorithm is presented. This module is parameterizable in relation to the number of levels, the number of phases, and the number of bits of fractional part of the reference vector. It is also technology independent, reusable, and modular. This circuit has been tested by implementation in a field-programmable gate array, with the goal of a balance of speed and area optimization. It was tested by using a five-level five-phase inverter feeding an induction motor. [ABSTRACT FROM AUTHOR]

The increasing demand for non-sinusoidal currents affects the quality of distribution networks. Harmonic detection is a crucial step in the cancellation of those components by active power filters. In this paper, the discrete cosine transform (DCT) is compared with different implementations based on Fourier transforms, demonstrating their equivalences and the advantages provided by the former. We demonstrate that the phase error in the presence of grid frequency deviations and the transient length are reduced by half in comparison to the discrete Fourier transform. A novel algorithm is developed to provide frequency adaptation to the DCT, taking advantage of its good features. The window width is adjusted in real time according to the actual value of the grid fundamental frequency by means of a phase-locked loop. A technique based on dithering is employed to overcome the limitation caused by the truncation of the window number of samples, so the frequency resolution is enhanced. The theoretical approach is verified by simulated and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach in the tuning of phase-locked loops (PLLs) for power electronic converters. PLLs are implemented inside a higher level controller to estimate the grid-voltage phase angle and then control the energy transfer between the power converter and the ac mains. The tuning of the PLL is not a trivial task, particularly when considering power-quality phenomena. In a general way, PLLs with a low bandwidth (low-gain PLLs) are required when handling distorted voltages. It is analytically demonstrated in this paper that low-gain PLLs have more tradeoffs than high-gain PLLs (e.g., PLLs for communications); it is not possible to optimize the settling time for a phase jump without making slower the PLL response to frequency variations. Existing tuning methods do not take into account low-gain features, which may result in nonoptimum designs. The proposed PLL tuning methodology is based on inspection of frequency-domain diagrams and, contrary to the other existing tuning methods, takes into account "low-gain" dynamics. It assures an optimized performance in the presence of any kind of disturbances in the grid. From a practical point of view, the proposed tuning procedure is very intuitive for controller designs. Some significant design examples and experimental results, obtained from a discrete implementation (dSpace platform), are provided in order to validate the theoretical approaches. [ABSTRACT FROM AUTHOR]

Selective harmonic cancellation has become of primary importance in a wide range of power electronics applications, for example, uninterrupted power systems, regenerative converters, and active power filters (APFs). In such applications, the primary objectives are an accurate cancellation of selected harmonics and a quick speed of response under transients. This paper provides a novel signal-processing algorithm for selective harmonic identification based on heterodyning, moving average finite-impulse response filters, and phase-locked loop (PLL). The algorithm is applied over the current of a nonlinear load in the feedforward-based control of an APF. The PLL tracks the phase and frequency of the fundamental component. Then, the fundamental phase is multiplied by the order of the selected harmonic, and two random unitary orthogonal "axis waves" are generated. These unitary waves, rotating at the harmonic frequency, are multiplied by the input load current, thereby "moving" the Fourier series coefficients of the selected harmonic to dc (heterodyning). Moving average FIR filters are used to filter the harmonics generated in the heterodyning process from the dc signal; moving average FIR filters are very suitable for most of the power quality applications, thanks to their "comb-type" frequency response and their quick transient response. Experimental results confirm good performance for steady-state harmonic cancellation and an optimal system response to load transients. The theory of the algorithm has been developed for single- and three-phase systems. [ABSTRACT FROM AUTHOR]

Multilevel converters can meet the increasing demand of power ratings and power quality associated with reduced harmonic distortion and lower electromagnetic interference. When the number of levels increases, it is necessary to control more and more switches in parallel. Field programmable gate arrays (FPGAs), with their concurrent processing capability, are suitable for the implementation of multilevel modulation algorithms. Among them, space vector pulsewidth modulation algorithms offer great flexibility to optimize switching waveforms and are well suited for digital implementation. In this paper, two algorithms, 2-D and 3-D, are analyzed and implemented in an FPGA. In order to carry out the implementation, both algorithms have been described in very high speed integrated circuit hardware description language, partly hand coded, and partly automatically generated using the System Generator tool. Both implementations are compared in terms of implementation complexity and logic resources required. Finally, test results with a neutral-point-clamped inverter are presented. [ABSTRACT FROM AUTHOR]