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We present an improved analog floating-gate pFET synapse that implements a supervised learning algorithm similar to the least mean square (LMS) learning rule. Weight decay plays a key role in several learning rules; this floating-gate synapse exhibits this behavior. We examine implications of the weight decay appearing in the correlation learning rule realized in the floating-gate synapse and provide experimental data characterizing the synapse and its performance in one-input and two-input LMS networks. Analog floating-gate synapses will enable larger-scale, on-chip learning networks than previously possible. Index Terms--Adaptive node, analog systems, floating-gate circuits, least mean square (LMS), supervised learning.

We study the weight dynamics of the floating-gate pFET synapse and the effects of the pFET's gate and drain voltages on these dynamics. We show that we can derive a weight update rule such that the equilibrium weight value is proportional to the correlation between the gate and drain voltages. In particular, we want a rule of the form [Tau]' [Delta]W = -[Delta]W + [Eta]E[xy], where x is a voltage signal on the gate terminal and y is a voltage signal on the drain terminal. We obtain this rule by making a linear approximation to the weight dynamics around a given equilibrium point. We develop this approximation by considering the basic functional form of the system dynamics and then examining the effects of the gate and drain voltages on the specifics of this form. Index Terms--Analog learning rules, analog synapses, electron tunneling, floating-gate circuits, hot-electron injection.