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Influences of source and drain recess structures on SiGe epitaxy growth, SiGe step height, facet formation, ID,sat and resistance performance are investigated. Growth rate of SiGe height increases with decreased recess width at a fixed depth of 62 nm. Under a fixed recess width of 96.3 nm, the deeper the recess, the higher the growth rate of SiGe height. An increase in the depth/width ratio of the recessed Si geometry may promote SiGe {001} growth. Upon the recess, SiGe step height is influenced by the initial SiGe orientation. A longer {001} facet of SiGe initial orientation causes a higher growth rate of SiGe step height. Higher IDsat and lower resistance can be achieved by increasing SiGe volume with wider recess width, deeper recess depth, and higher SiGe step height.

This study reports the achievement of a high short-circuit current density (J sc ) of 9.53 mA/cm 2 for low-cost electrodeposited (ED) semi-transparent Cu 2 O/ZnO nanorod (NR) solar cells. High-quality chemical-bath-deposited ZnO NRs that align with the carrier collection path were used to replace the traditional sputtered ZnO film. An almost four-fold increase (from 1.63 to 6.41 mA/cm 2 ) in J sc was obtained with the NRs compared to the level obtained with a sputtered ZnO thin film cell. Decreased the ED Cu 2 O absorber film thickness is able to compensate for the recombination loss that results from Cu 2 O's short minority carrier drift and diffusion length (both on the order of 100 nm), further boosting J sc to 7.77 mA/cm 2 . Additional photo-generated carriers were created for the semi-transparent solar cells when a silver mirror was deposited on the backside of the glass; this further enhanced absorption and improved J sc to 9.53 mA/cm 2 . This is the highest J sc value reported to date for a low-cost ED Cu 2 O/ZnO solar cell.

In this study, we demonstrated an organic light-emitting diode (OLED) using electro-deposited CuSCN as a hole-injection layer. The effects of thermal annealing and UV-Ozone treatments on ITO/CuSCN/organic interfaces were investigated. By employing both UV-O3 and proper thermal annealing (75 ° C, 20 min), Cu2O was found on the surface of CuSCN. With these treatments, the surface roughness of the organic deposited on CuSCN was reduced from 4.25 to 1.28 nm. The optical transmittance was also enhanced. Additionally, the CuSCN surface energy and polarity were considerably increased and the hole-injection barrier was decreased from 0.70 to 0.47 eV. The interface dipole effects lead to better adhesion between CuSCN/organic interface and facilitate the hole injection capability from anode ITO due to the formation of superficial Cu2O. The underlying mechanisms were illustrated by surface energy, X-Ray photoelectron spectroscopy (XPS), and ultraviolet photoelectron spectroscopy (UPS) measurements. As a result, these significantly enhanced CuSCN characteristics led to improved OLED performances, which achieved a hundred-fold efficiency compared to the device without any treatment. With this realization of integrating electro-deposited CuSCN into conventional organic optoelectronic systems, it could bring various practical benefits particularly concerning industrial interests in low-temperature, cost-effective, and large-area fabrication techniques.

Effects of antimony doping and film preferred crystal orientation on the performance and stability of electro-plated cuprous oxide (Cu2O) resistive random access memory (RRAM) devices were studied. Previous study indicated that electro-plated Cu2O with a small amount of antimony doping improves film uniformity, surface roughness1. The Sb doped film (Cu2O:Sb) also has a smaller grain size as compared to that of an un-doped cuprous oxide (u-Cu2O) film at same PH plating solution. SEM image of the grain boundaries of the Cu2O:Sb film also indicated that the film is more vertically oriented as compare to that of the u-Cu2O film. As some literatures reported, the conductive path (or charge hopping distance) of the RRAM is likely shorter if electrons hopping take place along the vertical-like grain boundaries. It will also reduce the voltage to set the conductive path formation (or set up of the charge hopping path). Moreover, uniform film and smoother surface are likely to have a stable set/reset performance because more uniform charge hopping distance and/or hopping site distribution. Our studies show that the forming voltages of a 700nm electroplated Cu2O:Sb (~2 at. %) and u-Cu2O (strongly (111) oriented) films are about 4V and 7V, respectively. Some of Cu2O:Sb RRAMs are forming free. The set voltages (Vset) of Cu2O:Sb and u-Cu2O RRAMs are ranging from 1.5V to 2.6V and from 1.2V to 9V, respectively. The reset voltages (Vreset) are 1.2V ~ 1.5V and 1V ~ 2V, respectively. The ratio of high/low resistance state (HRS/LRS) for both of the RRAMs is about two orders of magnitude, and no decay is observed for retention test of 5000 seconds at 0.1V. These results indicate that Sb doping does reduce forming (likely forming free) and significantly stabilize its set voltage. Surface morphology and texture of a (200)-preferred Cu2O film is very different from (111)-preferred film2 − 4. For a (200)-preferred film, its grains’ boundaries are more perpendicular to the plating surface (or electrode). This kind of film texture is also likely can help forming shorter conductive paths and/or stabilize the charge hopping resistance. It is similar to our Cu2O:Sb film texture as previous described. For Cu2O:Sb film, the XRD intensity ratio (R) of (111) to (200) phase is ~1. While the u-Cu2O is strongly (111)-preferred film with R= 12. Preferred crystal orientation change will give rise to varying in vacancy, defects, and trap charge distribution along the hopping paths. These variations can affect charge hopping resistance and its characteristics. Charge hopping in film with vertical-like grain boundaries is believed to be a shorter and easier path. Performance of preferred crystal orientation dependence of the u-Cu2O RRAM is investigated. A (200)-preferred u-Cu2O film with R= 0.185 was used. Its RRAM performance improved in forming voltage of ~5V and in HRS/LRS ratio with three orders of magnitude. In short, Cu2O:Sb film can be a good candidate for RRAM application because of its low cost, potential forming free, low set/reset voltages and stability. Sb doping may have helped forming shorter conductive paths due to its vertical like gains boundaries, less charge hopping resistance due to more uniformly distributed Sb induced hopping sites. Improved performance of (200)-preferred u-Cu2O RRAM may result from vacancy, defects and trap charge distribution change along the hopping paths. Reference 1. Baek, S. K., Kwon, Y. H., Shin, J. H., Lee, H. S., & Cho, H. K. “Low‐Temperature Processable High‐Performance Electrochemically Deposited p‐Type Cuprous Oxides Achieved by Incorporating a Small Amount of Antimony” Advanced Functional Materials, 25, (2015) 5214 2. J. Siegfried and K.S. Choi, “Electrochemical Crystallization of Cuprous Oxide with Systemic Shape Evolution” Advanced Materials, 16 (2004) 1743 3. E. Rakhshani and J. Varghese “Surface texture in electrodeposited films of cuprous oxide” J. Materials Science 23 (1988) 3847 4. H. Lee, I.C. Leu, C.L. Liao, K.Z. Fung “The structural evolution and electrochemical properties of the textured Cu2O thin films” J. Alloy Compounds 436 (2007) 241

An alternative route to form a wide band-gap Cu(In,Al)S 2 (CIAS) thin film with Al content of approximately 23 at.% and its application to ultraviolet (UV) photodetectors (PDs) have been demonstrated. X-ray diffraction patterns and scanning electron microscope micrographs show that the CIAS thin film, formed by 700 °C sulfurization of Cu 9 Al 4 (330) compound, is a single phased polycrystalline film with the (112)-preferred orientation and grain size of approximately 400–500 nm. At a 3 V bias voltage, the metal–semiconductor–metal structured UV PD has a dark current of 4.31 × 10 − 9 A and a photocurrent of 6.55 × 10 − 8 A using electrodes with 5-μm finger spacing. More than one order of magnitude in photocurrent amplification has been demonstrated. The spectral response of the PD is 0.72 A/W and the cut off wavelength occurs at 380 nm, which suggests that the band-gap of the CIAS film is 3.27 eV. The wide band-gap CIAS film has the potential to be a good candidate for UV PD applications.

Copper(I) thiocyanate (CuSCN) has been drawing much attention in optoelectronics due to its exceptional optical and electrical properties, as well as its processing versatility. The first organic light-emitting diodes (OLEDs) integrated with electro-deposited CuSCN crystalline thin films based on aqueous electrolyte were fabricated. With precisely tuned deposition parameters, the CuSCN thin films with satisfactory surface roughness and sufficient grain density were realized. We found that the driving voltage (voltage at a current density of 100 mA/cm2) and turn-on voltage of OLEDs using CuSCN as the hole injection layer (HIL) can be reduced by 1.41 and 1.79 V, respectively, compared with devices using vacuum-deposited hole injecting transition metal oxide molybdenum trioxide (MoO3). Moreover, the fabricated OLEDs also demonstrated considerably mitigated efficiency roll-off. Optical and energetic analyses were conducted to investigate the characteristics and enhancement mechanisms. Efficient hole-injection, electron blocking, improved charge balance, enhanced optical properties and good compatibility of electro-deposited CuSCN with thermally evaporated organic systems were found to be the primary contributors for the performance improvements of the OLEDs.

The preferred crystal orientation of the electrochemically deposited (ECD) Cu 2 O film on substrates with an array of ZnO nanorods (NRs) has been extensively investigated. For Cu 2 O film ECD on an array of ZnO NRs, texture of the ECD Cu 2 O films can be manipulated either by the pH value of the solution, the plating current, or the ZnO nanorod (NR) density. With a fixed plating current and at high pH values, highly (111)-preferred Cu 2 O film can only be obtained with certain NR densities, whereas NR too dense or too sparse can only grow a (200)-preferred Cu 2 O film. Low pH value or low plating current density is not able to form (111)-preferred film regardless of NR density. The texture change of the ECD Cu 2 O film deposited on ZnO NRs and its enhanced growth rate along the direction are attributed to the specific electric field configurations for substrate with NRs and the parallel receiving angle of the reactants. The degree of ZnO NR's influence on the preferred Cu 2 O growth and its growth characteristics are investigated and revealed.

We have demonstrated nano-structured Cu(In,Al)Se 2 (CIAS) near-infrared (NIR) photodetectors (PDs). The CIAS NIR PDs were fabricated on ZnO nanowires (NWs)/ZnO/Mo/ITO (indium tin oxide) glass substrate. CIAS film acted as a sensing layer and sparse ZnSe NWs, which were converted from ZnO NWs after selenization process, were embedded in the CIAS film to improve the amplification performance of the NIR PDs. X-ray diffraction patterns show that the CIAS film is a single phased polycrystalline film. Scanning electron microscopy was used to examine the morphology of the CIAS film and the growth of NWs. Two detection schemes, plain Al–CIAS–Al metal–semiconductor–metal structure and vertical structure with CIAS/ZnSe NWs annular p–n junctions, were studied. The nano-structured NIR PDs demonstrate two orders of magnitude for the annular p–n junction and one order of magnitude for the MSM structure in photocurrent amplification. The responsivities of the PDs using both sensing structures have the same cut-off frequency near 790 nm.

A 5 nm thick Cr added Ru film has been extensively investigated as a seedless Cu diffusion barrier. High-resolution transmission electron microscopy micrograph, X-ray diffraction (XRD) pattern and Fourier transform-electron diffraction pattern reveal that a Cr contained Ru (RuCr) film has a glassy microstructure and is an amorphous-like film. XRD patterns and sheet resistance data show that the RuCr film is stable up to 650 °C, which is approximately a 200 °C improvement in thermal stability as compared to that of the pure Ru film. X-ray photoelectron spectroscopy depth profiles show that the RuCr film can successfully block Cu diffusion, even after a 30-min 650 °C annealing. The leakage current of the Cu/5 nm RuCr/porous SiOCH/Si stacked structure is about two orders of magnitude lower than that of a pristine Ru sample for electric field below 1 MV/cm. The RuCr film can be a promising Cu diffusion barrier for advanced Cu metallization.

This study investigated the properties of 5 nm-thick RuMo film as a Cu diffusion barrier. The sheet resistance variation and X-ray diffraction patterns show that the RuMo alloy film has excellent barrier performance and that it is stable upon annealing at 725 °C against Cu. The transmission electron microscopy micrograph and diffraction patterns show that the RuMo film is an amorphous-like structure, whereas pure Ru film is a nano-crystalline structure. The elements’ depth profiles, analyzed by X-ray photoelectron spectroscopy, indicate no inter-diffusion behavior between the Cu and Si layer, even annealing at 700 °C. Lower leakage current has been achieved from the Cu/barrier/insulator/Si test structure using RuMo film as the barrier layer. A 5 nm ultrathin RuMo film provided two orders of magnitude improvement in leakage current and also exhibited a 175 °C improvement in thermal stability than that of the pure Ru film. It is a potential candidate as a seedless Cu diffusion barrier for advanced Cu interconnects.

Room temperature photoluminescence (RTPL) and ultraviolet (UV) Raman spectra from p−-Si wafers and low-energy, low-dose boron (B) implanted n−-Si wafers, annealed under various laser power densities, were measured. The RTPL intensity from implanted wafers, increased with increasing laser power density. UV Raman spectra showed significant, sudden changes in their shape and intensity around the surface melting condition. The sheet resistance of the implanted wafers was reduced as the laser power density decreased. Steep increase of RTPL intensity and steep reduction of the sheet resistance was measured from the B+ implanted n−-Si wafers above surface melting laser annealing conditions. A strong inverse correlation between RTPL intensity and sheet resistance was found for implanted wafers. The RTPL intensity, UV Raman spectra and sheet resistance of p−-Si reference wafers behaved quite differently compared to implanted wafers. The RTPL and UV Raman spectroscopy are very promising monitoring techniques for implant annealing processes.

We have demonstrated superstrate type nano-structured solar cells with ZnSe/ZnO coaxial NWs embedded in the CuInSe2 (CIS) layer. Complete filling of the CIS film into the narrow spaces between the ZnO NWs was realized by growing the NWs sparsely. The ZnSe/CIS heterojunction was self-formed by converting a skin (∼50 nm) layer of ZnO after the selenization. The influences of the NW length and density on light trapping and on cell conversion efficiency have been investigated. A 30% improvement in Jsc and higher efficiency has been achieved by embedding NWs in the CIS layer. Conversion efficiency of 1.79% was obtained from a ZnSe/CIS heterojunction solar cell fabricated on sparse ZnO NWs with Voc = 599 mV, Jsc = 11.60 mA/cm2 and 25.71% fill factor.

Nano-structured Cu2O/ZnO nanorod (NR) heterojunction solar cells fabricated on indium tin oxide (ITO)-coated glass are studied. Substrate film and NR density have a strong influence on the preferred growth of the Cu2O film. The X-ray diffractometer (XRD) analysis results show that highly (2 0 0)-preferred Cu2O film was formed when plating on plain ITO substrate. However, a highly (1 1 1)-preferred Cu2O film was obtained when plating on sparse ZnO NRs. SEM, TEM and XRD studies on sparse NR samples indicate that the Cu2O nano-crystallites mostly initiate its nucleation on the peripheral surfaces of the ZnO NRs, and are also highly (1 1 1)-oriented. Solar cells with ZnO NRs yielded much higher efficiency than those without. In addition, ZnO NRs plated on a ZnO-coated ITO glass significantly improve the shunt resistance and open-circuit voltage (Voc) of the devices, with consistently much higher efficiency obtained than when ZnO NRs are directly plated on ITO film. However, longer NRs do not improve the efficiency due to low short-circuit current (Jsc) and slightly higher series resistance. The best conversion efficiency of 0.56% was obtained from a Cu2O/ZnO NRs heterojunction solar cell fabricated on a 80 nm ZnO-coated ITO glass with Voc=0.514 V, Jsc=2.64 mA/cm2 and 41.5% fill factor.

A (2 2 0/2 0 4)-preferred CuInSe 2 (CIS) film formed using a two-step selenization process is reported, and the growth mechanism is explained. The CIS (2 2 0/2 0 4)-oriented film was grown on an Al:ZnO (AZO) coated glass for superstrate-type solar cell applications. The selenization temperature, Se vapor pressure, and reactive mechanisms of each selenization step were investigated. The first-step selenization at 400 °C favors the CIS (1 1 2) growth as the selenization time increases. For the second-step selenization, a high temperature (≧550 °C) and high Se vapor pressure throughout the process have a strong influence in promoting the CIS (2 2 0/2 0 4) growth. The oxygen in the self-formed In 2 O 3 layer at the AZO interface can be replaced by selenium, and transforms to an In 2 Se 3 (3 0 0)-preferred film, which favors the CIS (2 2 0/2 0 4) formation, in a transient and high Se vapor pressure selenization process. A Cu-rich surface, which is the usual case for selenizing precursor and which favors the CIS (1 1 2) growth, can be optimized to promote the CIS (2 2 0/2 0 4) growth by adding a thin In layer onto a slightly Cu-rich Cu/In precursor.

Tungsten missing was observed at the interface between contact barrier layer and W in the 28 nm node contact process. The potentiodynamic polarization scans showed that H2O2 in the W chemical-mechanical-polishing slurry increased the potential difference between the diborane (B2H6) reduced atomic layer deposited (ALD) W and TiN, suggesting that there is a high tendency for galvanic corrosion to occur. This potential difference kept constant, but the corrosion current density increased when the H2O2 concentration increased. The TEM image showed the depth of ALD W missing is proportional to the H2O2 concentration, which agrees with the electrochemical testing results. ALD W films with various pre- and post-treatments and their correlations with the degree of W missing were also investigated.

Using Al added Mo back electrode to provide Al source to form CuInAlSe 2 (CIAS) absorber with self-formed double graded bandgap (or Al concentration) is reported. The double Al grading is self-forming and requires no process tweaking or modification. A 15 at % Al in Mo(Al) film yielded 0.39 Al/(In+Al) ratio in the CIAS film with a bandgap of 1.54 eV at the surface. The benefits of doping Al into Mo film are: lower resistance of the Mo layer, improved Mo to glass adhesion, increased surface electric field or improved minority carrier collection from the graded Al content (graded bandgap), and supply Al to form a CIAS absorber layer.

In order to realize the high performance of RC delay, direct polished porous type ultra low-K film (ULK) is integrated into Cu dual-damascene interconnects for 45 nm and beyond. In the past, metal line seems not an important role in the world of TDDB. However, because of the minimized feature size and the relative fragile ULK film properties, it was found that the Cu roughness of polished surface also plays an important role to effect on the reliability such as TDDB from this generation. Post-cleaning of Cu CMP is a major process to manage the Cu surface roughness. In this paper, the correlation for post-cleaning time to the TDDB was discussed. The mechanism with two models was built up to explain this behavior as well.

Thermal and electrical properties of physical vapor deposition (PVD) Ru(P) film deposited on porous ultra low-k (p-ULK) material as Cu diffusion barrier were studied. The phosphorous concentration can be tuned by adjusting Ar to PH"3 ratio of the sputtering gases. The leakage current depends on phosphorous concentration. Higher phosphorous content in Ru film has lower leakage current. No obvious phosphorous content dependence was observed when the amorphous Ru(P) film crystallized. The X-ray diffraction (XRD) graphs and energy dispersive spectrometer's (EDS) atomic depth profiles show that the Ru(P) film deposited on p-ULK can effectively block Cu diffusion when the sample is subjected to 800^oC 5min annealing. The phosphorous doped Ru film improves diffusion barrier properties and leakage current performance. The improved Ru(P) barrier capable of direct Cu plating could be a potential candidate for advanced metallization.

The copper diffusion barrier properties of an ultrathin self-forming AlO x layer on a porous low-k film have been investigated. Cu-3 at.% Al alloy films were directly deposited onto porous low-k films by co-sputtering, followed by annealing at various temperatures. Transmission electron microscopy micrographs showed that a ∼ 5 nm layer self-formed at the interface after annealing. X-ray photoelectron spectroscopy analysis showed that this self-formed layer was Al 2 O 3 . Sharp declines of the Cu and Si concentrations at the interface indicated a lack of interdiffusion between Cu and the porous low-k film for annealing up to 600 °C for 30 min. The leakage currents from Cu(Al)/porous low-k/Si structures were similar to as-deposited films even after a 700 °C, 5 min anneal while a Cu sample without Al doping failed at lower temperatures. Adding small amounts of Al to bulk Cu is an effective way to self-form copper diffusion layer for advanced copper interconnects.

The properties of Ru(5 nm)/WCoCN(5 nm) stacked layers as a seedless Cu barrier system has been investigated. Its barrier properties compared to single 10 nm Ru film were investigated by sheet resistances, X-ray diffraction patterns, transmission electron microscopy, energy dispersive spectrometry spot analysis, line scans, and leakage currents. Thermal stability of the Ru(5 nm)/WCoCN(5 nm) improved by over 100 °C than that of Ru(10 nm) barrier. The results show that Ru(5 nm)/WCoCN(5 nm) can effectively block Cu diffusion up to 600 °C for 30 min. The Ru(5 nm)/WCoCN(5 nm) bilayer is a great Cu barrier candidate for seedless Cu interconnects.

Copper diffusion barrier properties of phosphorous doped Ru film are studied. Phosphorous out-diffusion to Ru from underneath phosphosilicate glass (PSG) layer results in P doped Ru film. The doped Ru film improves copper barrier properties and has excellent thermal stability. XRD graph indicates that there is no copper silicide and ruthenium silicide formations after annealing at 550 °C for 30 min in vacuum. This result is consistant with AES depth profiles which show no Cu, Ru, O and Si inter-diffusion. The phosphorous doped Ru barrier also blocks oxygen's diffusion to copper from the PSG layer. The phosphorous doped Ru film could be an alternative Cu diffusion barrier for advanced Cu interconnects.

Single mask dual damascene processes are described. The unique mask merges via and modified trench patterns. We design the mask's trench area to have partial transmission using thin chromium or add phase shifted gratings in the trench area to achieve destructive interference for lowering the intensity. Optical proximity correction is used to obtain the desired lithography process window. Upon exposure, the trench results in a partial exposure while the via is fully exposed and a dual damascene (DD) photoresist profile is created within specifications. Following with an integrated etch can complete the DD image transfer into the underneath dielectric. A single mask DD process eliminates via/trench misalignment issues, can save up to one half of metal mask cost, and 50% of other processing costs. It is expected to also boost yield and improve product reliability.

This study reports a low-cost electrodeposited copper(I) thiocyanate (CuSCN) film as a wide band-gap absorber layer for deep-ultraviolet (DUV) photodetector (PD) applications. Electrodeposited CuSCN films deposited with electrolyte concentrations of 24 mM and 33 mM were evaluated as the absorber layers for planar metal-semiconductor-metal PDs. The best photo-responsivity of the CuSCN PD was found to be as high as 70.3 A/W at a −1 V bias under DUV illumination at 300 nm, which corresponded to an external quantum efficiency of 3.1 × 104%. Furthermore, the DUV-to-visible rejection ratio (R300 nm/R400 nm) of ∼103 was realized. This study demonstrated that the CuSCN film has great potential for low-cost DUV PD applications.

Three kinds of graphene/polyimide specimen were prepared via transfer with 3, 6, and 9 graphene layers, respectively. A self-designed bending tester was applied to carry out cyclic bending tests with various bending cycles and bending frequencies. The variations of electrical resistance of the specimens during the bending process and the rate of increase of electrical resistance with the number of bending cycles and bending frequency for various total graphene thicknesses were determined. The voids that form at the interfaces between any two adjacent layers increase in size, leading to a disconnection between graphene layers after a number of bending cycles. A reduction in the graphene thickness and increases in the number of bending cycles and bending frequency increase the rate of increase of electrical resistance. For specimens with a given graphene thickness, the ID/IG value of the Raman shift increases exponentially with increasing number of bending cycles and bending frequency. An increase in ID/IG is accompanied by increases in both the rate of increase of electrical resistance and the aspect ratio L1/L2 (where L1 and L2 are the half lengths of the long and short axes, respectively, of the selected-area electron diffraction pattern of graphene). The tilt angle formed in the top graphene layer of the specimen after bending tests increases with increasing graphene thickness for a given bending frequency. The rate of increase of the tilt angle is affected by the bending frequency.

CIS thin films formed on several patterned structures, etched cavities and trenches, are studied. The structural influences on CuInSe 2 (CIS) film formation and film texture are reported. The X-ray diffraction (XRD) results show that as the spacing between cavities or trenches decreases, the XRD intensity ratio of CIS I(220/204) to that of I(112) increases. For a fixed spacing, CIS film formed on Mo/SLG with cavities has a higher intensity ratio than that on trenches. The surface morphology of the CIS film is also strongly influenced by the structural patterns. Substrate texturing also affects the preferred phase formation of In 2 Se 3 . Mo/SLG substrates with patterned cavities can eliminate In 2 Se 3 (006) formation. Formation of In 2 Se 3 (110), (202) and (300) phases can be achieved using Mo/SLG substrate with any of the patterned structures studied.

A new approach for fabricating macroscopic (∼10×10×10 mm3) structures with micrometer accuracy has been developed. This approach combines the precision of semiconductor processing and fiber optic technologies. A (100) silicon wafer is anisotropically etched to create four orthogonal v‐grooves and an aperture on each 10×12 mm die. Precision 308 μm optical fibers are sandwiched between the die to align the v‐grooves. The fiber is then anodically bonded to the die above and below it. This procedure is repeated to create thick structures and a stack of 5 or 6 die will be used to create a miniature scanning electron microscope (MSEM). Two die in the structure will have a segmented electrode to deflect the beam and correct for astigmatism. The entire structure is ultrahigh vacuum compatible. The performance of a SEM improves as its length is reduced and a sub‐cm 2 keV MSEM with a field emission source should have approximately 1 nm resolution. A low‐voltage high‐resolution MSEM would be useful for the examination of biological specimens and semiconductors with a minimum of damage. The first MSEM will be tested with existing 6 μm thermionic sources. In the future a micromachined field emission source will be used. The stacking technology presented in this paper can produce an array of MSEMs 1–30 mm in length with a 1 mm or larger period. A key question being addressed by this research is the optimum size for a low‐voltage MSEM which will be determined by the required spatial resolution, field of view, and working distance.

Arrays of sputtered tungsten thermionic emitters have been fabricated. The emitters are microbridges which were fabricated by removing a sacrificial layer of SiO2 below a patterned film, and have two thicknesses: 0.45 and 1.1 mu m. The emitting shape varies from a single straight 'wires'. The emitters initially have a high resistance which drops an order of magnitude with an annealing current. A thermionic electron current of over 10 nA for a duration of 5 to 55 min has been measured. The lifetime depends on the microbridge thickness, shape, and emitting current. Micrographs after emission indicate recrystallization and melting at the midpoint of the microbridges. The thermionic emitters will be used as sources for a miniature scanning electron microscope (MSEM) with a column length of 1-4 mm.

In this paper, the specific 45nm direct polish related defects and its effects were investigated in order to achieve the high yield manufacturing feasibility of direct polish to porous low-k dielectric film. Crater defect (ring shape metal bridge) was identified caused by abrasive residue in the pre-metal layer polish. Polished with colloidal silica based Cu slurry could suppress this defect efficiently. The plasma treatment on porous ultra low-k (ULK) layer improved the adhesion. However, it induced peeling when polish stop at this treated interface. It could be removed if further polish to intact ULK film. High Cu roughness possibly induced both pattern missing and via open in the following metal layer and suffered the yields. The V1M2 upstream electro-migration (EM) at this generation highly correlated to the roughness degree. By optimizing clean chemical concentration and clean time satisfied the needs of Cu roughness. Yield improvement proved the manufacturing feasibility of ULK direct polish technology.

This study reports a high-performance hybrid ultraviolet (UV) photodetector with visible-blind sensitivity fabricated by inserting a poly-(N-vinylcarbazole) (PVK) intermediate layer between low-cost processed Cu2O film and ZnO nanorods (NRs). The PVK layer acts as an electron-blocking/hole-transporting layer between the n-ZnO and p-Cu2O films. The Cu2O/PVK/ZnO NR photodetector exhibited a responsivity of 13.28 A/W at 360 nm, a high detectivity of 1.03 × 1013 Jones at a low bias of −0.1 V under a low UV light intensity of 24.9 μW/cm2. The photo-to-dark current ratios of the photodetector with and without the PVK intermediate layer at a bias of −0.5 V are 1.34 × 102 and 3.99, respectively. The UV-to-visible rejection ratios (R360 nm/R450 nm) are 350 and 1.735, respectively. Several features are demonstrated: (a) UV photo-generated holes at the ZnO NRs can effectively be transported through the PVK layer to the p-Cu2O layer; (b) the insertion of a PVK buffer layer significantly minimizes the reverse-bias lea...

This study demonstrates that air annealing can grow high-quality graphene films on the surface of polycrystalline nickel film with the help of an effective SiO2 capping layer. The number of graphene layers can be modulated by the amount of carbon embedded in the Ni film before annealing. Raman analysis results, transmission electron microscopy images, and electron diffraction patterns of the samples confirm that graphene films can be grown in air with an oxygen blocking layer and a 10 °C/s cooling rate in an open-vented rapid thermal annealing chamber or an open tube furnace. The high-quality low-defect air-annealing grown graphene is comparable to commercially available graphene grown via chemical vapor deposition. The proposed graphene growth using air annealing technique is simple and low-cost, making it highly attractive for mass production. It is transfer-free to a silicon substrate and can speed up graphene development, opening up new applications.

In the development of interconnect architecture for future technologies, LSI has determined that adoption of low-k dielectrics will give higher performance gain as opposed to the replacement of aluminum with copper. The goal is to integrate a robust low-k material for LSI's 0.18 /spl mu/m subtractive aluminum technology with at least 20% capacitance reduction. As a result we have successfully integrated and qualified a flowable carbon doped low-k-film. Dielectric constant ranges from 2.8 to 3.5. We have achieved comparable via resistance performance and 20% to 35% reductions in the line-to-line capacitance compared to the conventional HDP scheme. Greater than 90% system uptime was obtained during the marathon. The process has been released to manufacturing with statistical process control monitoring for the past few months.

We demonstrate the thinnest ever reported Cu diffusion barrier, a 1-nm-thick graphene tri-layer. X-ray diffraction patterns and Raman spectra show that the graphene is thermally stable at up to 750 °C against Cu diffusion. Transmission electron microscopy images show that there was no inter-diffusion in the Cu/graphene/Si structure. Raman analyses indicate that the graphene may have degraded into a nanocrystalline structure at 750 °C. At 800 °C, the perfect carbon structure was damaged, and thus the barrier failed. The results of this study suggest that graphene could be the ultimate Cu interconnect diffusion barrier.

Two inexpensive and extremely accurate methods for fabricating miniature 10 - 50 kV and 0.5 - 10 kV electron beam columns have been developed: `slicing,' and `stacking.' Two or three miniature columns could be used to perform a 20 nm or better alignment of an x-ray mask to a substrate. An array of miniature columns could be used for rapid wafer inspection and high throughput electron beam lithography. The column fabrication methods combine the precision of semiconductor processing and fiber optic technologies to create macroscopic structures consisting of charged particle sources, deflecting and focusing electrodes, and detectors. The overall performance of the miniature column also depends on the emission characteristics of the micromachined electron source which is currently being investigated.

Application of the CuInSe2-based thin film for a near-infrared (NIR) photodetector (PD) has been demonstrated. The Cu(In,Al)Se2 (CIAS) was used as an absorption layer for NIR PD with comb-structured Al electrodes. X-ray diffraction spectrum and scanning electron microscope (SEM) micrographs show that the CIAS film is a single phased polycrystalline film with smooth surface and super large (2–5 μm) grains. Low temperature photoluminescence analysis indicates that the CIAS has a strong NIR excitation emission peak. The CIAS PDs are highly sensitive to the NIR spectrum with cut-off frequency near 790 nm and demonstrate four-orders of magnitude in photocurrent amplification.

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The copper diffusion barrier properties of a 3 nm self-forming InO x layer on a porous ultralow-k (p-ULK) film have been investigated. A 5 at. % In doped Cu film was directly deposited onto porous low-k films by co-sputtering, followed by annealing at various temperatures. Transmission electron microscopy (TEM) images showed that a 3 nm layer was self-formed at the interface between Cu–In and p-ULK films after annealing at 400 °C for 1 h. An EDS line scan on the region near this interface showed obvious accumulation of In at the interface. X-ray photoelectron spectroscopy (XPS) analyses indicated that the self-formed interfacial layer was InO x . The self-forming InO x layer prevented Cu agglomeration on the p-ULK film surface. The XPS atomic depth profiles showed that the self-formed InO x barrier was thermally stable against Cu diffusion to at least 500 °C for 5 h. The sheet resistance of the post 500 °C annealed Cu–In film was comparable to that of a pure Cu film. The Cu–In self-forming barrier approach may be a viable candidate for Cu/p-ULK interconnects.

Barrier properties of 10 nm thick Ru and amorphous Ru 37.2 W 62.8 films as seedless copper diffusion barriers have been investigated. Thermal stability of the barriers was evaluated after annealing at various temperatures. X-ray diffraction (XRD) analyses and sheet resistance measurements suggested that the Ru 37.2 W 62.8 barrier was thermally stable up to 700°C against Cu diffusion, which improved about 150°C over the Ru film. XRD studies and electron diffraction patterns of the Ru 37.2 W 62.8 film showed that it maintained an amorphous-like microstructure after 30 min annealing at 550°C. This film started to recrystallize at about 600°C and developed to a film with Ru and W0 3 grains after a 700°C anneal. The leakage current of the 500°C postannealed Cu/RuW/ porous SiOCH/Si stacked structure provided nearly 2 orders of magnitude superior than that of the Ru sample. The amorphous Ru 37.2 W 62.8 film is an alternative candidate for the Cu direct platable seedless barrier in the advanced copper metallization process.

The failure mode and Cu barrier properties of a 5 nm thick boron and carbon added Ru (Ru―B―C) film deposited on Si substrate have been investigated. Results from X-ray diffraction (XRD) and Fourier-transformed electron diffraction patterns indicate that the Ru―B―C film is amorphous up to 700°C. Unlike pure Ru film, the Ru in the Ru―B―C film recrystallized at 750°C instead of reacting with Si at the interface to form Ru 2 Si 3 . The sheet resistance and XRD results show that the 5 nm Ru―B―C barrier is thermally stable up to 750°C, whereas the 5 and 10 nm Ru are only stable below 550 and 600°C, respectively.

A new approach for fabricating arrays of electron beam columns by stacking silicon wafers with micron accuracy has been developed. This approach combines the precision of semiconductor processing and fiber optic technologies. A (100) silicon wafer is anisotropically etched to create an array of apertures on the top or bottom of the wafer and four orthogonal v- grooves on both surfaces of the wafer. Precision pyrex fibers align and bond the v-grooves on the top of one wafer to the bottom of the next wafer. This procedure is repeated to create thick structures and a stack of six wafers is used to create arrays of scanning electron microscopes (SEMs). This technique is suitable for fabricating 1 - 30 mm long electron optical columns. The optimum size is determined by the desired array size, operating voltage, resolution, field of view, and working distance. The first wafer contains an array of micromachined field emission electron sources. The next three wafers accelerate and focus the electron beams. The last two wafers in the stack have electrodes to deflect each beam and correct for astigmatism. The performance of an SEM improves as its length is reduced and a subcm 2 keV SEM with a field emission source should have approximately 7 nm resolution.

A new microfabrication technique that allows the precise construction of large three dimensional structures with dimensional tolerances approaching 1 micron is being applied to the design of a Miniature Scanning Electron Microscope (MSEM). In this paper we will present the electron optic calculations of the MSEM source (gun). The MSEM measures less than one cubic centimeter and the source measures approximately lx I xO.20 cm3. The details of the MSEM fabrication are in an accompanying article.1