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The design of power delivery system plays a crucial role in guaranteeing the proper functionality of many-core processor systems. The power loss suffered on power delivery has become a salient part of total power consumption, and the energy efficiency of a highly dynamic system has been significantly challenged. Being able to achieve a fast response time and multiple voltage domain control, on-chip voltage regulators (VRs) have become popular choices to enable fine-grain power management, which also enlarge the design space of power delivery systems. This paper analytically studies different power delivery system paradigms and power management schemes in terms of energy efficiency, area overhead, and power pin occupation. The analysis shows that compared to the conventional paradigm with off-chip VRs, hybrid paradigms with both on-chip and off-chip VRs are able to maintain high efficiency in a larger range of workloads, though they suffer from low efficiency at light workload. Employed with the quantized power management scheme, the hybrid paradigm can improve the system energy efficiency at light workload by a maximum of 136% compared to the traditional load balanced scheme. Besides this, the in-package (iP) hybrid paradigm further shows its advantage in reducing the physical overheads. The results reveal that at 120 W workload, it occupies only a 10.94% total footprint area or 39.07% power pins of that of the off-chip paradigm. We conclude that the iP hybrid paradigm achieves the best tradeoffs between efficiency, physical overhead, and realization of fine-grain power management. [ABSTRACT FROM AUTHOR]

Optical networks-on-chip (ONoCs) have shown the potential to be substituted for electronic networks-on-chip (NoCs) to bring substantially higher bandwidth and more efficient power consumption in both on- and off-chip communication. However, basic optical devices, which are the key components in constructing ONoCs, experience inevitable crosstalk noise and power loss; the crosstalk noise from the basic devices accumulates in large-scale ONoCs and considerably hurts the signal-to-noise ratio (SNR) as well as restricts the network scalability. For the first time, this paper presents a formal system-level analytical approach to analyze the worst-case crosstalk noise and SNR in arbitrary fat-tree-based ONoCs. The analyses are performed hierarchically at the basic optical device level, then at the optical router level, and finally at the network level. A general 4 \,\times\, 4 optical router model is considered to enable the proposed method to be adaptable to fat-tree-based ONoCs using an arbitrary 4 \,\times\, 4 optical router. Utilizing the proposed general router model, the worst-case SNR link candidates in the network are determined. Moreover, we apply the proposed analyses to a case study of fat-tree-based ONoCs using an optical turnaround router (OTAR). Quantitative simulation results indicate low values of SNR and scalability constraints in large scale fat-tree-based ONoCs, which is due to the high power of crosstalk noise and power loss. For instance, in fat-tree-based ONoCs using the OTAR, when the injection laser power equals 0 dBm, the crosstalk noise power is higher than the signal power when the number of processor cores exceeds 128; when it is equal to 256, the signal power, crosstalk noise power, and SNR are -17.3 , -11.9 , and -5.5~dB , respectively. [ABSTRACT FROM PUBLISHER]

This paper proposes an all-optical second-order ordinary differential equation (SODE) solver based on a single microdisk resonator. We validate the feasibility of our structure for constant and complex coefficient SODE solutions for Gaussian and super-Gaussian pulses. The results demonstrate a good agreement between the solutions obtained with the designed structure and those obtained through mathematical calculations for both constant and complex coefficient SODEs. We also discuss the influence of input optical signal pulse width on solution result deviations. Furthermore, we validate the capability of the designed structure to achieve tunable solutions for complex-coefficient SODEs with a tuning power of less than 10 mW. The device footprint is approximately 20×30 μm 2 , and it is 3-4 times smaller than the current smallest solving unit. The maximum Q-factor reaches 9.8×10 4 . The proposed device avoids the traditional approach of cascading two resonators for SODE solving. Moreover, achieving mode alignment within the same resonator reduces the process challenges associated with aligning multiple devices in a cascade. Furthermore, it offers wider applicability for solving SODEs, namely, the ability to solve both constant and complex coefficient SODEs with complete derivative terms.