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For scaling of bulk Si Fin field-effect transistor (FinFET), suppression of short-channel effects is required without ON-state current degradation. In this letter, solid-source doping for channel doping using 1-nm phosphosilicate glass was demonstrated on both p-type (100) Si substrate and p-type bulk Si FinFET. The profile of phosphorus in p-type (100) Si substrate was analyzed by secondary ion mass spectrometry and it was diffused deeper with higher thermal budget of anneal. Fabricated bulk Si FinFETs with using 1-nm phosphosilicate glass showed threshold voltage shift with several anneals at 1- $\mu \text{m}$ and 70-nm gate lengths. Hole mobility at 1- $\mu \text{m}$ gate length and transconductance at 70-nm gate length were also reduced due to increase in impurity concentration of phosphorus diffused by anneals into Fins. Phosphorus diffusion into Fins with using 1-nm phosphosilicate glass was investigated and phosphorus behavior after anneal was clarified by electrical data of p-type bulk Si FinFETs.

Air gap (AG) interconnects, with an ideal dielectric constant k of 1, is a promising approach to reduce signal propagation delay. In this paper, a comparative study of AG and dielectric copper damascene interconnect structures is performed through Raphael™ electric field simulation to investigate the capacitance benefit of introducing AG when scaling to small dimensions. The variation in total capacitance as a function of half pitch is simulated for different AG integration schemes proposed in the literature. Ideal and practical cases of these different integration schemes are simulated and compared to assess whether interconnect structures using a low- k ( k = 2.3) dielectric are more suitable than AG interconnects at scaled dimensions. The effect of using an additional (SiC-based) stiff liner on the AG capacitance benefit is also investigated. Finally, we verify our simulations using sub-40 nm half pitch AG structures prepared using the conformal and non-conformal processes.

We report a method to improve the chemical stability and the mechanical properties of a plasma enhanced chemical vapour deposited ultra low-dielectric constant material. This enhancement in the properties was achieved through extended UV cure times using a broad band lamp, emitting light at wavelengths higher than 200nm. These longer cures also increased significantly the Young's modulus, but the dielectric constant did increase less than the experimental error. It is also demonstrated that this improved property depends on the chemical bonds present in the film, such as Si-CH"3, as well as on the density of the film. Films with a dielectric constant of 2.06, Young's modulus of 4.9GPa and perfect resistance against 0.5% HF for up to 300s, were obtained. Another type of UV cure, using a narrow band lamp with wavelength of 172nm, induced completely different chemical resistance characteristics of the resulting films.

Atomic layer deposition is a promising technique to deposit conformal, nm-thin metal barriers in high-aspect-ratio trenches. However, exactly because of its excellent conformality, the deposition can also occur inside the nanopores of the most advanced low-k materials. In this work, the mechanisms of atomic layer deposition on and in low-k, porous dielectric films were studied, using HfO"2 as a test material. Exhaustive analyses showed firstly that the HfCl"4 precursor penetrated uniformly in the pores throughout a 44nm thick low-k film. Secondly, it was shown that the pores were sealed as function of precursor size, i.e. there are conditions where the pores became inaccessible for HfCl"4, while the - smaller - H"2O molecules could still penetrate the pores. From these analyses, a deposition model was proposed.

We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for L G = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.

The use of low-k materials is essential for improving the quality of integrated circuits. Subsequent process steps may however modify this film to the extent that the final result is unacceptable. Organosilicate-based low-k films, with a nominal k-value of 2.3, were exposed to different post-CMP cleaning plasmas used for copper reduction. The resulting plasma damage was investigated and is reported in this paper. All the studied plasmas increased the density of the low-k film. TOFSIMS and FTIR analyses showed that they all removed CH"3 groups from the bulk, leading to water incorporation. The carbon depletion was more pronounced and deeper (100nm) from a NH"3 plasma than from any other investigated plasma. N"2+H"2 plasma removed somewhat less carbon from the low-k film (83nm deep). The N"2 plasma removed carbon down to a depth of 60nm into the film, while a pure H"2 plasma removed the least carbon of all the investigated plasmas, to a depth of only 35nm. The combination of TOFSIMS and XPS indicated the incorporation of a significant amount of N in the films treated with the pure N"2 plasma. C-V measurements showed an increase of the dielectric constant, again mostly for the NH"3 plasmas. There was an intermediate and approximately equal increase of the dielectric constant for all N"2 containing plasmas, and the least increase was for the H"2 plasma. This increase of the dielectric constant was caused by the increase of density of the film, incorporation of water, and in the case of the N"2 plasma also the incorporation of N. This shows that the presence of N"2 in plasma may significantly damage low-k materials, and it should not therefore be treated as a mere carrier gas.

Silicon crystallizes in the diamond-cubic phase and shows only a weak emission at 1.1 eV. Diamond-hexagonal silicon however has an indirect bandgap at 1.5 eV and has therefore potential for application in opto-electronic devices. Here we discuss a method based on advanced silicon device processing to form diamond-hexagonal silicon nano-ribbons. With an appropriate temperature anneal applied to densify the oxide fillings between silicon fins, the lateral outward stress exerted on fins sandwiched between wide and narrow oxide windows can result in a phase transition from diamond-cubic to diamond-hexagonal Si at the base of these fins. The diamond-hexagonal slabs are generally 5–8 nm thick and can extend over the full width and length of the fins, i.e. have a nano-ribbon shape along the fins. Although hexagonal silicon is a metastable phase, once formed it is found being stable during subsequent high temperature treatments even during process steps up to 1050 ºC.

FinFETs are now widely accepted transistor architecture to replace the two dimensional (2D) metal-oxide-silicon field effect transistors (MOSFETs) into a three dimensional (3D), multi-gate (MG) MOSFETs. The MG FinFETs can be fabricated either on a silicon-on-insulator (SOI) substrate or on a bulk silicon substrate. Both approaches require an advanced patterning not only to improve device performance but also to increase the packing density. Despite the simpler process and the benefit of scaling the fin dimension on an SOI substrate, the Si industry prefers the bulk FinFETS owing to their compatibility with the existing CMOS infrastructure and to the reduced wafer cost. The combination of an advanced patterning such as self-aligned-double-patterning (SADP) and a 1× nm FinFETs device fabrication on a bulk Si substrate poses very challenging geometry constraints for the process integration. In this work, the technical and geometrical challenges of a SADP bulk FinFETs process integration are outlined. Finally, an empirical model to establish robust SADP bulk FinFETs integration is presented.

Higher performance, higher operation speed and volume shrinkage require high 3D TSV interconnect densities. This work focuses on a via-middle 3D process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) and before the back-end-of-line (BEOL) interconnect process. A description of the imec 300 mm TSV platform is given, and challenges towards a reliable process integration of high density high aspect-ratio 3D interconnections are also discussed in details.

In this work we integrate an advanced k=2.3 spin-on polymer at 40nm ½ pitch. K-value restoration techniques are investigated and complete k-value restoration is demonstrated using an in-situ HeH 2 plasma. An EUV compatible stack and a dielectric dual hard mask scheme is developed to pattern trenches with good uniformity and low litho-etch bias. The impact of scaling the dielectric spacing and of direct CMP on time dependent dielectric breakdown is also studied.

Atomic layer deposition is a promising technique to deposit conformal, nm-thin metal barriers in high aspect ratio trenches. However, exactly because of its excellent conformality, the deposition can also occur inside the nanopores of the most advanced low-k materials. In this work, the mechanisms of atomic layer deposition on and in low-k, porous dielectric films were studied, using HfO 2 as a test material. Exhaustive analyses showed firstly that the HfCl 4 precursor penetrated uniformly in the pores throughout a 44 nm low-k film. Secondly it is shown that the pores were sealed as function of precursor size, i.e. there are conditions where the pores became inaccessible for HfCl 4 , while the - smaller - H 2 O molecules could still penetrate the pores. From these analyses a deposition model was proposed.

The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. We present a 300mm industry-compliant via-middle TSV module, integrated to an advanced high-k/metal gate CMOS process platform. TSVs are fabricated by a Bosch process after contact fabrication and before the first metal layer. The target for copper diameter is 5μm and via depth in the silicon substrate is 50μm. Dense structures have a pitch of 10μm. The vias are filled with TEOS/O 3 oxide to reduce via-to-substrate capacitance and leakage, a Ta layer to act as Cu-diffusion barrier and electroplated copper. Copper is thermally treated before CMP to minimize copper pumping effects. The processing is integrated as part of a 65nm node CMOS fabrication module and validated with regular monitoring of physical parameters. The module was tested in device lots and also integrated to a thinning and backside passivation flow.