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U ovom završnom radu su prikazana 2 jednostavna načina očitavanja stanja napunjenosti baterije, a to su metoda aproksimacije po naponu i metoda pomoću EEPROM-ove look-up tablice. Metode su međusobno uspoređene kako bi se odredila preciznost i točnost. This final paper presents 2 simple ways of reading battery's state of charge, and those are voltage approximation method and method using EEPROM's look-up table. Methods are compared to each other to determine precision and accuracy.

A prepaid RFID-based electricity payment system is proposed in this paper. The system is intended for rooming houses where residents’ electricity overconsumption and outstanding payment are to be avoided by the house owner. An RFID-card is used as the payment instrument. The system consists of two units, the card balance top-up unit (CTU) and the energy credit top-up unit (ETU). The balance of the RFID-card is topped up by using the CTU. With the balance stored in it, the RFID-card is to be used to top-up the energy credit at the ETU. Each of the CTU and the ETU is equipped with a microcontroller, an RFID reader/writer and a user interface in the form of keypad and liquid crystal display (LCD). Furthermore, the ETU utilizes a relay to control the flow of electricity. If the energy credit of a room is exhausted, then the supply of electricity to the room is cut off by the relay. The electricity consumption is calculated based on the number of pulses of the calibration LED of a standardized electronic energy meter. The pulse is transmitted to the microcontroller by using an optocoupler. The RFID-card records the current card balance, the card’s top-up history, and the card’s usage history. The energy credit is stored in the EEPROM of the ETU’s microcontroller. The energy meter is tested to measure the energy consumption of two loads based on the pulses of its calibration LED. The actual power of the two loads are 87.25 % and 94.23 % of the corresponding power rating. The card balance top-up process at the CTU and the energy credit top-up process at the ETU are successfully checked. After every balance top-up and credit top-up, the current card balance is calculated and stored correctly. During the electricity usage, the LCD of the ETU shows the remaining energy credit in IDR and kWh. These are accumulatively reduced every time the pulse count reaches a certain reset number, which corresponds to the electrical energy’s unit price applied. The proposed electricity payment system can be a solution for owners of rooming houses to secure electricity payments from the residents. The installation cost of the system is low and without the need to change the existing electricity purchase method of the house. The house owner also can individually adjust the maximum power limit for each room.

This article introduces an EEPROM memory cell model that is different from the equivalent capacitance model. This model uses high-frequency components in circuit design, including MOS transistors, zener diodes, resistors, capacitors, etc., and builds a model that can be used in most analog environments. The simulation of the transient process of write and read operations helps designers understand the working principle of EEPROM, and it can also be applied to the overall circuit design. According to the structure and working principle of the EEPROM cell device, a model of its equivalent circuit is established, and the read, write, and erase operations of the EEPROM cell are transiently simulated using this model. The simulation results verify the correctness of the model.

EEPROM is an electrically erasable and programmable memory. The technology is mature and stable with low cost, so it is the mainstream in the application of electronic products in daily life. People use it in every way. In the fields of personal identity card, bank card, medical insurance card, traffic card and other smart cards, which are closely related to personal property, and in the field of communication system and other consumer electronic products such as PDA and digital camera, EEPROM is used. In instruments and other embedded systems, such as smart flowmeters, it is usually necessary to store information such as setting parameters, field data, etc., which requires that the system is not lost when it is powered down so that the data you originally set could be restored next time. Therefore, a certain capacity of EEPROM. Through the storage or release of electrons on the floating gate tube of the memory cell, the memory appears to be on or off when the floating gate tube is read, so its logic value will be judged as “0” Or “1”. The definition of logic “0” or “1” varies depending on the logical design of the product. This work designs a memory cell consisting of two transistors. The NMOS tube is used as a selection tube and controlled by the word line. It can withstand a part of the high voltage and reduce the probability of breakdown of the ultra-thin oxide layer of the floating gate transistor. As a storage tube, the EEPROM device model designed in this paper can work well through the tunnel oxide layer to store data, achieving better storage functions, higher work efficiency, and lower power consumption.

In smartphones, and more generally in IoT devices, manufacturers focus their efforts on securing communications with the outside world that are more exposed to attack while considering communications between secure components. By doing this, it results in internal communication buses with little or no security against attackers. I2C is the most used internal communication bus in IoT devices to communicate with sensors and memories. It is also used in recent smartphones to connect the Trusted Execution Environments (ARM TrustZone, Apple SEP, or Google Titan M) to a dedicated EEPROM memory that contains secret information such as encryption keys, anti-replay counter, or the boot ROM. In this paper, we propose a non-invasive attack through a hardware trojan on the I2C bus, which will allow us to perform two attack scenarios: a heart bleeding type attack which will allow retrieving additional information at each memory read, and a buffer overflow attack which will allow writing additional data in the memory at each write which can result in modifying secret information such as password or counters. These attacks can be performed on any device using the I2C bus. In the context of smartphones, these attacks will allow the extraction of sensitive information stored in the secure EEPROM memory.

This paper is presenting a brief comparison between two of the most used nonvolatile memories (NVM) from automotive industry. Advantages and disadvantages are presented for each one but also a critical scenario for the flash EEPROM (electronically-erasable programmable read-only memory) emulation memory with repetitive undervoltage situation.

The majority of Internet of Things (IoT) devices are tiny embedded systems with a micro-controller unit (MCU) as its brain. The memory footprint (SRAM, Flash, and EEPROM) of such MCU-based devices is often very limited, restricting onboard Machine Learning (ML) model training for large trainsets with high feature dimensions. To cope with memory issues, the current edge analytics approaches train high-quality ML models on the cloud GPUs (uses large volume historical data), then deploy the deep optimized version of the resultant models on edge devices for inference. Such approaches are inefficient in concept drift situations where the data generated at the device level vary frequently, and trained models are clueless on how to behave if previously unseen data arrives. In this paper, we present Train++, an incremental training algorithm that trains ML models locally at the device level (e.g., on MCUs and small CPUs) using the full n-samples of high-dimensional data. Train++ transforms even the most resource-constrained MCU-based IoT edge devices into intelligent devices that can locally build their own knowledge base on-the-fly using the live data, thus creating smart self-learning and autonomous problem-solving devices. Train++ algorithm is extensively evaluated on 5 popular MCU-boards, using 7 datasets of varying sizes and feature dimensions. A few exciting findings when analyzing the evaluation results are: (i) The proposed method reduces the onboard binary classifier training time by ≈ 10 - 226 sec across various commodity MCUs; (ii) Train++ can infer on MCUs for the entire test set in real-time of 1 ms; (iii) The accuracy improved by 5.15 - 7.3% since the incremental characteristic of Train++ enabled the loading of full n-samples of the high-dimensional datasets even on MCUs with only a few hundred kBs of memory.

Cilj ovog diplomskog rada bila je implementacija STM32 biblioteka za EEPROM i NTAG NFC integrirane sklopove. Uređaji koji su se koristili prilikom izrade diplomskog rada bili su mikroupravljač STM32F407VET6, EEPROM CAT24M01 te NTAG I2C plus (NT3H2211). Za razvoj biblioteka korišteno je razvojno okruženje za razvoj programske podrške Keil uVision 5. Bilo je potrebno napraviti da EEPROM te NTAG I2C plus u implementiranim bibliotekama komuniciraju s mikroupravljačem putem I2C sučelja. Također, svaka funkcija unutar pojedine biblioteke morala je biti detaljno testirana. Svaka funkcija obje biblioteke sadrži detaljan opis ponašanja, uz opis svakog pojedinog parametra. EEPROM biblioteka sastoji se od 10 funkcija, od kojih je većina za čitanje i zapisivanje podataka. NFC NXP biblioteka sastoji se od 94 funkcija, gdje se dio funkcija odnosi na čitanje i zapisivanje podataka, a dio funkcija na interakciju s pojedinim registrima da bi NTAG NFC uređaj radio prema zahtjevanim specifikacijama. Nakon uspješnog razvoja NFC NXP biblioteke, koristeći njene funkcije trebalo je implementirati pass-through način rada, koji služi za prijenos velike količine podataka u malome vremenu s NFC sučelja uređaja prema I2C sučelju odnosno s I2C sučelja prema NFC sučelju. Uz to, trebalo je testirati funkcionalnost tog načina rada pomoću NTAG I2C demo aplikacije. Korištenjem ovog načina rada u kombinaciji s EEPROM-om, moguće je ostvariti sustave u kojima korisnik šalje podatke putem NFC sučelja svog pametnog telefona/uređaja, a ti podatci se preko I2C sučelja i mikroupravljača spremaju u EEPROM. Također, moguće je napraviti sustave u kojima mikroupravljač očitava određene senzore, te ih sprema u EEPROM, a korisnik ih zatim očitava pomoću NFC sučelja kada su mu potrebni. Primjer takvog sustava je meteorološka stanica. The aim of this thesis was to implement the STM32 library for EEPROM and NTAG NFC integrated circuits. The devices used in the preparation of the thesis were the microcontroller STM32F407VET6, EEPROM CAT24M01 and NTAG I2C plus (NT3H2211). The Keil uVision 5 software development environment was used to develop the libraries. It was necessary to create that EEPROM and NTAG I2C plus in the implemented libraries communicate with the microcontroller via the I2C interface. Also, every function within a particular library had to be tested in detail. Each function of the libraries contains a detailed description of the behavior along with a description of each individual parameter. The EEPROM library consists of 10 functions, most of which are for reading and writing data. The NFC NXP library consists of 94 functions, where part of the functions is related to reading and writing data, and part of the functions interact with individual registers to make the NTAG NFC device work according to demanding specifications. After the successful development of the NFC NXP library, using its functions, a pass-through mode was to be implemented, which serves to transfer large amounts of data in a short period of time via NFC interface of the device to the I2C interface or from the I2C interface of the device to the NFC interface. In addition, the functionality of this mode had to be tested using NTAG I2C demo application. By using this mode in combination with EEPROM, it is possible to create systems in which the user sends data via the NFC interface of his smartphone/device, and then this data gets transferred to the EEPROM via the I2C interface and microcontroller. Also, it is possible to create systems in which the microcontroller reads certain sensors, then propagates data in the EEPROM and the user then reads the stored data using the NFC interface when he wants to. An example of such a system is a meteorological station.

This paper aims to apply the use of quality tools for fault analysis techniques and internal circuit board defect reduction in an air conditioner company. We currently have millions of air conditioners installed and produced annually on all continents and consecutively there is increasing consumer complaints that internal circuit boards are one of the most critical components of an appliance and it is it that controls its functions as a for example: receive the temperature signal chosen on the remote control so that it works to increase or decrease the temperature as per customer requirement. According to vendor defect, data our top one defects are related to evaporator EEPROM non-write defect circuit board problems and with that 3.12% defect work, we achieved a 0% reduction of defects after Work completed with 2 weeks of follow-up.

In this paper, an analysis of a Verilog-A memristor model is discussed in order to be implemented in a 1T1R cell by exploring the characterization data of an OxRRAM device. The proposed analysis is done using mathematical formulation and verified by Spectre circuit simulator. The analysis is tested for a digital logic gate such as NAND gate for both, SET and RESET processes to perform read and write operations. Moreover, we explore diverse types of memory cells, two configurations are considered as a PROM and an EEPROM. Additionally, the implementation of the Verilog-A model on a crossbar array is discussed in details in terms of switching speed and the range of resistance. A comparison between the performances of various existing memory cells is also discussed. Our simulation results carry the desired nonlinear memristor fingerprint, the applicability to fit different switching behaviors. These results are verified by both electrical and experimental characterization data. We conclude that the proposed Verilog-A model is suitable for digitals circuits, crossbar arrays, low-power and high-density applications at the industrial levels.

Complementary metal–oxide–semiconductor (CMOS) technology is reaching its limits due to the continuous shrinking process, which has an impact on various aspects including device size, performance, and power consumption. The memristor is one of the promising devices under investigation for use with deep-nanometer CMOS, having applicability in several fields due to its nonlinear behavior, nonvolatility, low power consumption, high density, and CMOS compatibility. Several models for memristors have been developed to date, but there is a requirement for compact models that are both flexible and sufficiently accurate. A general memristor model generated in Verilog-A is discussed herein to confirm its behavior in the one-transistor one-resistor (1T1R) oxide-based random-access memory (OxRAM) configuration, and validated at circuit level. The results of the model correlate well with experimental characterization data for the HfO2-based OxRAM memristor device, describing the characteristics of both its bipolar and unipolar memristor behaviors. The 1T1R structure is analyzed using the Spectre circuit simulator. Two cases are considered, using the cell as either programmable read-only memory (PROM) or electrically erasable programmable read-only memory (EEPROM). The simulation results confirm the desired nonlinear memristor characteristic, and the applicability of the model to fit and simulate different switching behaviors. The results are verified against both electrical and experimental characterization data, suggesting that the Verilog-A model is suitable for low-power and high-density logic circuit applications at the industrial level.

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.

The Electrically Erasable Programmable Read Only Memory (EEPROM) technology has been widely studied but EEPROM Technology Computer Aided-Design (TCAD) simulations still need to be improved to handle the rises of the quality requirements of the semiconductor market. In this paper, the impact of endurance degradation on EEPROM programming window and the corresponding TCAD simulation are investigated. Advanced calibrated TCAD simulation on 110nm node is used to evaluate the distribution of negative charges trapped in the tunnel (bulk) oxide during EEPROM cycling. The total negative charge evolution found by our simulation is in agreement with the well-known trapping power law found in the literature.

Дипломний проєкт включає пояснювальну записку (51 с., 20 рис., 15 табл., 4 додатки). Об’єктом розробки є програмно-апаратний комплекс для аналізу параметрів енергонезалежної пам’яті. Метою даного проєкту є розробка програмно-апаратного комплексу для автоматизації тестування та верифікації основних видів енергонезалежної пам’яті в автомобільній промисловості. Розроблений програмно-апаратний комплекс дозволяє: отримувати результати аналізу для вимірів енергонезалежної пам’яті з детальним представленням стану пам’яті; конфігурувати правила аналізу, характеристики енергонезалежної пам’яті (вид пам’яті, загальна кількість адрес, розмір слова пам’яті). Для мінімізації витрат на створення, тестування й майбутні модифікації програмного коду було використано мову програмування Python з відкритими бібліотеками numpy, pandas, seaborn, які надають зручну й надійну основу для створення програм аналізу даних. У процесі розробки було: – проведено аналіз методів верифікації блоків енергонезалежної пам’яті в інтегральних мікросхемах; – сформульовані вимоги до програмно-апаратного комплексу для аналізу параметрів енергонезалежної пам’яті; – створено структуру програмно-апаратного комплексу; – розроблено алгоритми аналізу вимірів енергонезалежної пам’яті; – розроблено засоби для читання вхідних даних з вимірами та генерації вихідних результатів аналізу; – здійснено тестування програмно-апаратного комплексу на вимірах справжніх інтегральних мікросхем. Програмно-апаратний комплекс був успішно впроваджений у ДП «МЕЛЕКСІС-УКРАЇНА» у відділі верифікації енергонезалежної пам’яті. Це дозволило суттєво зменшити витрати часу на аналіз вимірів енергонезалежної пам’яті. The diploma project includes an explanatory note (51 p., 20 fig., 15 tables, 1 equation, 4 additions). The object of development is application software for non-volatile memory parameters analysis. The purpose of this project is development of application software for testing and verification automation of most non-volatile memory in automotive industry. The application software provides: getting analysis results for non-volatile measurements with detailed memory state representation; configuring analysis rules, non-volatile memory properties (memory type, total number of addresses, memory word size). Python programming language with open-source libraries numpy, pandas, seaborn were used to minimize costs for development, testing and future code modifications. These instruments give easy and reliable basis for data analysis software. The development process included: – analysis of non-volatile memory block verification methods inside integrated circuits; – designing the application software requirements for non-volatile memory parameters analysis; – designing the application software structure; – development of non-volatile memory measurements analysis; – development of input measurements data reading methods and output analysis results generation; – testing of application software using real integrated circuits measurements. The application software has been successfully integrated at non-volatile memory verification department of Melexis-Ukraine company. It has minimized costs for non-volatile memory measurements analysis.

A high-precision digital readout interface for a ±15g open-loop MEMS capacitive accelerometer is present in this paper. The differential capacitance resulting from input acceleration is picked up by a low-noise switch-capacitor (SC) charge sensitive amplifier (CSA) and further digitized by a 2nd-order Σ-Δ ADC after amplification. In order to reduce the nonlinearity of the open-loop accelerometer with high mechanical sensitivity, a digital nonlinearity calibration system is implemented on chip with a 320×8-bit embedded EEPROM for parameters storage. Newton-Raphson iteration algorithm is utilized for compensation parameter calculation, and serial processing as well as floatingpoint operation is used for hardware overhead reduction. The interface designed in a 0.35-µm 3.3V/14V embedded EEPROM CMOS process occupies 12.14 mm2 and draws 11.1mA from a 3.3-V supply. The measured original nonlinearity of the accelerometer is 0.32%, while it is reduced to 0.084% after the compensation parameters are written into EEPROM. Moreover, the accelerometer system achieves a noise floor of 5.5µg/√Hz over a 200-Hz bandwidth and a bias instability (BI) of 5.13μg.

Recently, we proposed a novel 3D AND-type Flash memory [1]–[3] architecture for 3D NOR Flash solution. In this work, we further propose a “write-in-place” (or “in-place write”) operation (like EEPROM) and demonstrate the feasibility. “Write-in-place” is to provide the same erase unit (page erase) as the program unit (page program). Thus to overwrite a page data the users just need one page erase followed by the page program, without the need to deal with a large erase unit (like NAND and NOR Flash memories). The in-place write does not require complex GC (garbage collection) algorithms by system controller, and can eliminate the write amplifications effect and improve the QoS (quality of service) of system performances. After optimization of BE-MANOS charge-trapping device, the in-place page write time can be minimized to around 110usec. Small neighbor-WL interferences, free from pattern loading effects and hot-carrier disturbs are merits of 3D AND architecture to enable write-in-place. We also suggest the future extensions of integrating ferroelectric memory FeFET device in the 3D AND architecture to further boost the in-place write speed to nearly 1 micro second at lower write voltages (∼5V).

This paper aims to evaluate and exhibit the State of Health and initial State of Charge of a Lithium-ion Polymer Battery, which offers high power and energy density. SOH and SOC estimations are vital in terms of safety and fidelity of electric vehicles. As the other estimation techniques are quite challenging with complicated algorithms and models, the proposed method just uses voltage as a common factor, because of its dropping nature, along with the battery’s age. The two salient features of Battery Management System (BMS) are SOH, determined with the voltage variation in the charging phase and SOC, determined using the exact voltage present in the battery at that instant and the maximum voltage obtained during each full charge cycle under no load conditions. The experimental setup includes a charger, LiPo battery of 11.1V, Arduino (ATMEGA 328 for the UNO) on I2C protocol, and a relay. The battery’s full charge voltage is stored in Electrically Erasable Programmable Read-Only Memory (EEPROM) of the Arduino, which acts as an input for both the estimations. This study concentrates on the full charge voltage, each and every time, regardless of the age and condition of the battery for improvisation in the accuracy.

In this paper, a nonvolatile switch based on n-type floating-gate transistors is described. The switch states are programmed through the memory cell floating-gate voltage, allowing higher levels than the application supply. Furthermore, due to its nonvolatile nature, the power consumption is reduced. The on-state resistance, which does not depend on the supply voltage, is one of the greatest advantages of this type of switch in comparison to conventional switches. This benefit can be successfully exploited in low-voltage applications. The switch on-resistance can be increased without the need for increasing the switch area. The characteristics of the proposed switch were confirmed by the experimental results obtained on a test chip fabricated in a 0.18 µm EEPROM process. Measured on-resistance values between 45 and 70 Ω were obtained for a floating-gate voltage of 6.2 V and input source levels below 2 V. The required programming voltage was 18 V. The maximum off-state leakage current was measured at 5 nA.

Non-volatile memory (NVM) devices, based on floating gate (FG) technology, including EEPROM, NAND and OR Flash memories, are increasingly used today in both consumer products and high-end applications. Quality of 3D NAND Flash in solid-state drive (SSD) storage used in data center, automotive and space science is critical. While NOR Flash used in TWS earbuds for smartphones and IoT/5G products offers a quality of live option. To ensure reliability of the high-end products, e.g. for space application where ionizing radiation can produce potential damage to FGs, single event effects (SEEs) and total ionizing dose (TID) are typical assessments to evaluate product quality of Flash memory, subject to ionizing radiation particles of different energy and hence linear energy transfer (LET) in interactions with CMOS materials, Si and SiO 2 . Reported studies of SEE and TID using energy; stopping power (SP or S) or LET on various Flash memories are numerous. However, the quantitative results at various energy, S or LET can be misleading, as neither energy nor LET is an ideal quality factor in interpreting radiation hazards. Based on previous analysis of various radiation particles in CMOS silicon gate, the current study is extended to using the characteristics of range (R) of particle trajectory and specific ionization (Is) to analyze mean free path (Δ, distance between two ionization events) of electron, proton and several heavy ions in FG of Flash memory and the impact of electric charges generated by ionizing radiations. In the past decades the silicon process (of the gate length) has progressed from 100 nm down to 10 nm, our work further aims to explore effective radiation damage of SEE and TID by different types of particles, with respect to gate sizes of NVM cells.

This paper presents the design of a digital part for a low frequency passive RFID tag in a double-poly 180 nm CMOS process. The digital part was designed for the RFID tag, which operates at 125 kHz frequency and meets the ISO 11784/11785 standards. As a memory storage unit, the device uses an EEPROM block with a capacity of 544 bits. The tag supports 32-bit writing and single-bit reading. Manchester and bi-phase coding schemes are used to transfer data between the reader and the tag. To prevent memory hacking, a 2-word OTP anti-tearing feature was implemented. For the target 180 nm CMOS process the average power consumption of the digital part is less than 1 μW, and the occupied area is 0.042 mm2.

The increase in the number of fatalities in road accidents, it has become important to know the reasons for the crash and use the retrieved information for further study. The purpose of the project is to develop a crash box that can be installed for diagnosis into the vehicle. It will act as an independent system, which in case of a crash; will record speed, time of accident, and location of the vehicle, for some references. This recorded data will provide valuable information during the post-crash analysis. The device will make use of components like the ATMEGA328P, a GSM module, a rotary encoder, a NEO 6M GPS module & an EEPROM. The data obtained by the device can be used by the vehicle manufacturers to analyze the reason for the crash and to find proper solutions to prevent the same in the future.