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In this work, an in-depth static and low frequency noise characterization of nanosheet FETs, consisting of two vertically stacked silicon channels per device, is performed. A comparison of the performances from n- versus p-channel FETs operated at 300 K and 78 K, in terms of static and low frequency noise parameters variability, is also discussed. The main electrical parameters are estimated from the I-V characteristics using access resistance robust methodologies. An additional criterion demonstrating that the extracted parameters are not influenced by the second mobility attenuation factor is proposed. The low frequency noise studies prove that the dominant flicker noise mechanism is linked to correlated carrier number and mobility fluctuations, with additional access resistances noise contribution in very strong inversion. The importance of the considered total flicker noise model on the estimation of the Coulomb scattering coefficient is highlighted.

In this work, two types of gate-all-around (GAA) vertically stacked silicon nanosheet (NS) FETs are investigated, the main difference being the vertical distance between the stacked NSs. Principal electrical parameters are estimated at room and liquid nitrogen temperatures using a refined Y -function methodology, the main advantage being that no extra iterative steps are necessary. The results are confirmed using other derivative dc parameter estimation methodologies. Low-frequency noise measurements evidence variability of the flat-band voltage noise and correlation between the noise level and the low field mobility. The dominant flicker noise mechanism is related to the correlated mobility and carrier number fluctuation mechanism with access resistance noise contribution in very strong inversion. The impact of the access resistance on the estimation of the Coulomb scattering coefficient is evidenced.

The low-frequency (LF) noise characterization of Si0.7Ge0.3 pFinFETs and transistors’ performance were analyzed for different NH3 post deposition annealing (PDA) temperatures. The flicker noise of these pFinFETs is dominated by carrier number fluctuations at low and intermediate drain currents. At high gate overdrive, the voltage noise Svg increases dramatically and the effect of the access resistance cannot be ignored. By analyzing the input-referred voltage noise power spectral density(PSD) at flat band voltage ( Svgfb ), we will demonstrate that nitridation of the high- κ layer at 650 °C yields the best quality gate-stack and also results in the highest mobility. While NH3 PDA temperature above 650 °C may introduce more hydrogen at the oxide layer and at the interface, hydrogen can induce hole traps and interface traps that degrade the quality of the gate-stack and reduce the mobility.

We report on vertically stacked nanosheet (NS) FET devices as the most promising candidates to replace finFETs, discussing some of their key features and potential extension and/or alternative options to help preserve the power, performance, area, and cost (PPAC) logic roadmap for advanced sub-5nm technology nodes, being also attractive for cold computing. In addition, given the increased complexity and cost in back-end-of-line processing, to take full advantage of the scaling performance benefits at transistor level it has also become ever more pressing to address signal and power wiring bottlenecks. The concept of moving power delivery to the wafer’s backside has been gaining traction and we will thus also explore it in this work by combining logic and 3D technologies and assess its feasibility by evaluating the impact of 3D processing on device characteristics.

Here, it has been verified through numerical simulations calibrated to experimental data the changes that the insertion of a germanium layer can bring to the electrical power generation of a silicon solar cell. The studied device is a lateral PIN photodiode embedded in a wafer with SOI (Silicon-On-Insulator) technology as part of a CMOS (Complementary Metal Oxide Semiconductor) circuit. The insertion of a germanium layer on top or below a silicon PIN diode has been considered. Results showed that different semiconductor characteristics (bandgap, mobility, and absorption coefficients) result in a general improvement in the solar cell performance, therefore allowing a better understanding of the phenomena that occur in the photogeneration of a cell with a heterojunction between germanium and silicon.

In this article, the interfacial properties of nMOSFETs with different thickness high- $\kappa $ Al2O3 capping layer on an 8-nm SiO2 and TiN gate stacks have been investigated using electrical measurement and low-frequency noise at room temperature. It is shown that the predominant 1/ ${f}$ noise is governed by the number fluctuations mechanism. It is indicated that: 1) presence of an Al2O3 capping layer increases the noise power spectral density and, hence, the oxide trap density has an influence on the low-field mobility further and 2) effective work-function and the threshold voltage of nMOSFET should be modulated using the high- $\kappa $ Al2O3 capping layers.

The variability of the low-frequency (LF) noise in n-channel MOSFETs fabricated on an Ultra-Thin Buried Oxide (UTBOX) Silicon-on-Insulator (SOI) substrate has been studied and compared with the variability in the threshold voltage and low-field mobility of the same devices. No correlation has been found between the noise magnitude and the DC parameters, suggesting that the traps responsible for the current fluctuations do not affect the latter. A possible explanation is that the LF noise is dominated by Generation-Recombination (GR) centers in the silicon film, which have less impact on the drain current. Index t erms: FD SOI nMOSFET; low-frequency noise; generation-recombination noise; noise variability.

This paper presents an analytical model to determine the threshold voltage in Ultrathin Body and Buried Oxide Fully Depleted Silicon on Insulator (UTBB FD SOI) MOSFETs operating in dynamic threshold (DT) voltage modes. The analytical model is based on implementing the quantum confinement effect and the DT restriction. The results show that the proposed analytical model in its simplicity provides a good agreement to the experimental data.

In this work, the X-ray irradiation impact on the back gate conduction and drain current for Triple-Gate SOI FinFETs is investigated for strained and unstrained devices. Both types (P and N) of transistors were analyzed. Since X-rays promote trapped positive charges in the buried oxide, the second interface threshold voltage shifts to lower gate voltage. The performance of n-channel devices presented a strong degradation when submitted to X-rays, while for p-channel devices the opposite trend was observed. Two different dose rates were analyzed.

This work aims to analyze through 2D numerical simulations the minimum drain bias for the onset of the parasitic bipolar transistor (BJT) effect (VLatch) of a Ultra-Thin-Buried-Oxide (UTBOX) Fully-Depleted-Silicon-on-Insulator (FDSOI) transistor used as a Single-Transistor-Dynamic-Random-Access-Memory (1TDRAM) cell at high temperatures. The buried oxide thickness (tBOX) and silicon film thickness (tSi) variation were also taken into account and initial studies of the retention time (RT) and the data degradation have been performed. It was verified that the latch voltage, the sense margin current, the latch time and the retention time decrease as the temperature rises.

This work presents an analysis of SOI p- and nMuGFET devices with different TiN metal gate electrode thickness for rotated and standard structures.Thinner TiN metal gate allows achieving a higher intrinsic voltage gain in spite of the reduced variation observed of the gm/IDS characteristics. This effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. Even with the larger mobility of the rotated nMuGFET devices when compared with the standard ones, the larger output conductance degradation resulted in an almost similar intrinsic voltage gain. P-channel devices, when implemented on the rotated layout, offer a lower intrinsic voltage gain.The GIDL current was also analyzed on these devices, indicating to be larger in thinner metal gate and rotated configuration.

This work presents an analysis of the analog performance of SOI MuGFET devices and the impact of different TiN metal gate electrode thickness.Thinner TiN metal gate allows achieving large gain and this effect can be attributed to the increased Early voltage values observed for thinner TiN metal gate. This VEA increase suggests an increase of the transversal electrical field for thin TiN metal gate (reduced gate oxide thickness) that is confirmed with the increment of the GIDL current.This impact on the voltage gain is maintained for short channel length.The impact of different gate dielectrics was also studied where high-k dielectric indicated a higher VT due to a VFB variation. Additionally, lower intrinsic voltage gain was observed for hafnium dielectric and this can be related to the lower Early voltage (VEA) present in this devices.

This article describes an experimental comparative study of the matching between the Octo conventional (octagonal gate geometry) and Conventional (rectangular gate shape) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) Integrated Circuits (ICs) technology and exposed to different X-rays Total Ionizing Doses (TIDs), under the on-state bias conditions. The results indicate that the Octo layout style with alpha ( $\alpha $ ) angle equal to 90° and a cut factor of 50% for MOSFETs is capable of boosting the device matching by at least 56.1%, on average, regarding the electrical parameters studied (Threshold Voltage and Subthreshold Swing), as compared to those found in the Conventional MOSFET counterparts, considering that they present the same bias conditions and regarding different TIDs. This happens due to the Longitudinal Corner Effect (LCE), Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) which are present in the Octo MOSFETs. Therefore, the Octagonal layout style can be considered as an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS ICs applications.

This paper presents an analysis of the instability of the Zero Temperature Coefficient (ZTC) as a function of the gate length and drain bias for partially depleted SOI MOSFETs operating at high temperatures (from room temperature up to 573K). The study takes into account temperature dependent model parameters such as threshold voltage and channel mobility. The analytical predictions are in very close agreement with experimental results in spite of the simplifications used for the VZTC model as a function of temperature in the linear and the saturation regime.

The influence of Selective Epitaxial Growth (SEG) and the Uniaxial and Biaxial Strain are studied in triple gate FinFETs, analyzing the Drain Induced Barrier Lowering Effect (DIBL). The splits using SEG present better performance for strained devices than the unstrained ones but the inverse is observed for devices without SEG. The DIBL values are higher for SEG devices in all cases. For devices without SEG, the effect of mechanical stress is more pronounced and the mobility is higher in the uniaxially strained devices. These devices have lower VT values in the saturation condition causing the highest DIBL.

This article presents a comparative low-frequency noise (LFN) characterization of gate-all-around nanosheet n-channel Si metal–oxide–semiconductor field effect transistors, processed with three different metal gates (MGs): an aluminum-based reference process and two alternative effective work function (EWF) stacks. In all cases, the gate dielectric is composed of HfO2 over an SiO2 interfacial layer. The LFN figures of merit are extracted, such as the oxide trap density and Coulomb scattering coefficient, and the correlations with the threshold voltage and the electron mobility are investigated. Carrier number fluctuations are confirmed as the dominant mechanism of the 1/ ${f}$ noise for all evaluated devices. Additionally, it is shown that the specific MG can contribute to the carrier scattering, degrading the electron mobility. The most promising results are obtained for one of the alternative MGs, exhibiting a low oxide trap density level, a low threshold voltage and insignificant mobility degradation.

The impact of different process options on the low-frequency noise (LFN) performance and reliability of Ge nFinFETs is investigated. The results show that the LFN is mainly determined by carrier number fluctuations, and the density of traps in the high- $\kappa $ dielectric can be reduced by an extended dry clean. In some small-size devices, the Lorentzian-type noise comes from GR centers in the oxide layer or dislocations in the Ge fins. Due to the Coulomb scattering by charged oxide traps, Ge nFinFETs with higher input-referred voltage noise at flat band voltage ( $S_{{\text {vgfb}}}$ ) usually have a lower mobility. Since the charged traps in the oxide layer are one of the main responsible factors for the shift of the threshold voltage, the transistors with bigger $S_{{\text {vgfb}}}$ show higher PBTI degradation, and $S_{{\text {vgfb}}}$ can be considered as an early indicator for the reliability of Ge nFinFETs.

In this article, a metal/carbon-doped GaN (GaN:C)/Si-doped GaN (GaN:Si) structure was used to investigate the defect characteristics and carrier transport mechanisms in GaN:C layers with different carbon doping concentration. Capacitance-voltage, current–voltage, and deep-level transient spectroscopy measurements were performed at different temperatures. At forward bias, a pinning effect was found at the interface of the GaN:C/GaN:Si layer, due to the defects capturing electrons. The forward currents of the samples with high carbon doping concentration ( ${N}_{C}> {1} \times 10^{{19}}$ cm−3) increase gradually with increasing forward bias voltage. Ohm’s law, space-charge-limited current, and variable-range-hopping mechanisms may dominate the forward current. For the samples with low carbon doping concentration ( ${N}_{C} cm−3), a device turning on behavior was observed, which is attributed to the carriers overcoming a potential barrier. In addition, the DLTS spectra reveal that only electron trapping happens at forward bias for the samples with high carbon doping concentration, while, in addition, hole trapping was observed for the samples with low carbon doping concentration. The process of the carrier capture by defects was demonstrated.

Fast characterization methods are utilized to investigate DC and AC negative bias temperature instability (NBTI) characteristics in pMOSFETs with different TiN capping layer thicknesses ( ${t} _{\mathrm{ TiN}}$ ). The impacts of ${t} _{\mathrm{ TiN}}$ scaling on the threshold voltage shift ( ${\Delta }\text{V}_{\mathrm{ T}}$ ), pre-existing hole traps ( ${\Delta }\text{V}_{\mathrm{ HT}}$ ), generated traps (GTs), and their relative contributions are studied. The time exponents of ${\Delta }\text{V}_{\mathrm{ T}}$ and GTs, and the impacts of stress voltage, temperature, frequency, and duty cycle on the NBTI degradation are analyzed. DC and AC NBTI degradations increase with ${t} _{T}{}_{iN}$ . When ${t} _{\mathrm{ TiN}}$ is scaled down from 3 nm to 1 nm, the maximum operation field is improved by 60%, which originates from the reduction in both ${\Delta }\text{V}_{\mathrm{ HT}}$ and GTs. Moreover, we experimentally demonstrate that bulk trap generation is an ${f}$ -dependent process and that its relative contribution to ${\Delta }\text{V}_{\mathrm{ T}}$ increases with ${t} _{\mathrm{ TiN}}$ , which is an important factor for the improvement of NBTI through ${t} _{\mathrm{ TiN}}$ scaling.

This article presents an experimental, room temperature, low-frequency noise characterization of germanium n-channel fin-field-effect transistors (finFETs) integrated on silicon. After determining the dominant mechanism in the noise spectrum, the main parameters associated with the noise mechanism are extracted and evaluated as a function of fin width from a planar-like (100 nm) up to narrow fin (20 nm) for 1- $\mu \text{m}$ length devices. The main findings are that the 1/ ${f}$ noise plays an important role in the Ge n-finFETs, whereby the trap density profiles in the gate-stack are quite uniform and have a lower level than in n-/p-channel Ge planar MOSFETs. In addition, a generation-recombination (GR) component was found in 160-nm-length devices, which is caused by GR centers located in the depletion region.

In this letter, we present an experimental study on the frequency ( f ) dependence of trap generation under AC negative bias temperature instability (NBTI) stress in Si p-channel fin field-effect transistors (p-FinFETs), by adopting the direct-current current voltage (DCIV) method and an energy profiling technique. The interface trap generation ( $\Delta ~\text{N}_{IT}$ ) and bulk trap generation ( $\Delta ~\text{N}_{OT}$ ) are separated from the measured DCIV data and their ${f}$ dependences are independently investigated. The DCIV results indicate that the observed strong ${f}$ dependence of trap generation is primarily attributed to the ${f}$ -dependent $\Delta ~\text{N}_{OT}$ that exhibits a 36% reduction when ${f}$ increases from 10 Hz to 1 MHz. Furthermore, this ${f}$ -dependent $\Delta ~\text{N}_{OT}$ is mainly distributed between ${\text{E}_{v}}$ and ${\text{E}_{i}}$ , and exhibits a visible ${f}$ -dependent peak of energy density around ${\text{E}_{c}}$ .

Continued scaling of DRAM technologies has required a limitation of the power dissipation from the logic components on-chip, while downscaling both transistor oxide thickness and gate length. One route to enable further scaling, while circumventing excessive leakage currents, is the integration of high-permittivity ( ${\kappa }$ ) metal-gate (HKMG) components into the logic and high-voltage (e.g., I/O) devices. The requirement of a gate-first flow for devices in the peripheral region introduces significant reliability challenges. Even though Negative Bias Temperature Instability (NBTI) performance of CMOS and memory thermal budget compatible transistors are aligned with conventional HKMG integration with thin oxide devices, it is not the case for thick oxide devices. In particular, it will be shown that strong NBTI lifetime degradation is observed as soon as high- ${\kappa }$ layers are deposited on top of the thick interfacial layer. In this work, a review of the impact of these high- ${\kappa }$ layers on the NBTI high voltage logic for memory devices is presented. The stress induced degradation is correlated to a diffusion of metal atoms from the HKMG gate stack towards the silicon surface. Directions for reliability improvements are then defined. The presence of Nitrogen throughout the HKMG stack can originate either from high- ${\kappa }$ processing or metal-nitride gate electrode. It is shown that preventing nitrogen diffusion towards the Si/SiO2 interface region, together with AlOx and/or F incorporation at the HKMG interface, can tune device threshold voltage and modulate access to donor trap-defect bands. The result of these effects is a vast improvement in NBTI performance. A detailed study of NBTI-degradation, supported by physical analysis, assessing the impact of various tuning components within the stack (interface layer, high- $\kappa $ fluorination and/or cap, metal gate) will be presented. Potential solutions for this reliability challenge will be reported.

Introduction. The Gate-All-Around (GAA) Nanowire (NW) or nanosheet (NS) architecture provides superior short-channel effects control and is widely considered as one of the most promising candidates to replace finFETs in advanced Logic technology nodes. Compared with their horizontal implementation, vertical NWs (or NSs) FETs [1] offer some clear advantages, appearing promising devices to overcome some of the limitations encountered by conventional CMOS scaling as it reaches its physical limits and faces interconnect routing congestion. They have the potential to yield smaller circuits with reduced power consumption [2], allowing relaxed Lgate without impacting the device footprint. While their fabrication is challenging, several schemes have been proposed for improved process control and device performance [1]. In this work, the static parameters of vertical NW junctionless (JL) nMOSFETs have been studied for devices with two different Replacement Metal Gate (RMG) cap layer widths (see schematics in figure 1), encapsulating the top part of the pillars during processing at the RMG module. It will be shown that this strongly impacts the static device parameters: the threshold voltage (VT), the maximum transconductance (gmmax) and the dynamic output resistance (rout). Moreover, a correlation is shown with the input-referred voltage noise Power Spectral Density (PSD) SVG at 10 Hz, which could be explained in terms of a process-induced variation in the diameter D of the NWs. Experimental. A detailed process description has been recently reported [1]. A 55 nm in situ P-doped n+ layer is deposited by CVD on a low-resistivity silicon substrate (source contact), followed by 90 nm undoped silicon and again 55 nm n+ Si. The RMG stack consists of IL-SiO2/HfO2/TiN/W. An RMG cap consisting of SiO2 is used to encapsulate the top of the pillars. Here, devices with two different cap widths and 100 wires in parallel are compared. On-wafer DC and low-frequency noise measurements have been performed using a BT1500 Parameter Analyzer and an E4727A Advanced Low-Frequency Noise Analyzer from Keysight, respectively. Measurements have been performed in linear operation at a drain voltage VDS=50 mV, while the gate voltage VGS is stepped from weak to strong inversion. Results and Discussion. Figure 1 and 2 compares the linear input ID-VGS characteristics of a set of narrow and wide cap vertical NW nFETs. While there is obvious device-to-device variability, the wide-gap devices (Fig. 2) clearly exhibit a lower VT than their narrow-gap counterparts in Fig. 1. The transconductance (gm) plots of Figs 3 and 4 reveal another trend: devices with a high VT generally exhibit a lower gmmax and vice versa. This is even so within each flavour of devices in Figs 3 and 4. As will be shown, nFETs with a high(er) VT and lower gmmax also tend to exhibit a higher rout. Finally, Figs 5 and 6 demonstrate that the corresponding SVG at f=10 Hz is smaller for the wide-cap devices, especially around VT, where the minimum noise PSD is found. As will be shown, the noise spectra are dominated by 1/f-like noise (fVG could suggest a difference in oxide/interface trap density, but this is not reflected in the subthreshold swing nor in the PBTI behaviour [1]. On the other hand, it has been reported before that the VT of NW transistors increases for reduce D [3]. This could well explain also the lower gmmax (scales with D) and the higher SVG (scales with 1/D). The different NW diameter could result from the different dummy dielectric removal [1]. References [1] A. Veloso et al., to be published in the Proc. of IEDM 2019. [2] T. Huyng-Bao et al., SPIE 2016, 978102 [3] A. Veloso et al., J. Phys: Condens. Matter, 30, 384002 (2018). Figure 1

In the semiconductor industry, the scaling down of devices has always been the driver in order to improve circuit area efficiency and high current drive, leading to the triple gate FinFET, which is the newest technology for high performance applications. However, it is believed that these devices cannot reach the sub 7 nm nodes and the GAA nanowires MOSFETs has emerged as one of the most promising candidates for this technology node, as it presents high density of integration and higher electrostatic control between gate and channel (1-2). The studied devices are GAA silicon nanosheet MOSFETs, fabricated at Imec, Leuven – Belgium, with two stacked channels with the vertical distance between the sheets of 7.5 nm, an EOT of 0.9 nm, a width of 15 nm and a channel length varying from 200nm down to 28nm. The threshold voltage (VTH) as a function of temperature is presented in figure 1, in which it is possible to observe that, VTH is reduced (in absolute value) for both n- and pMOS as temperature increases due to the fermi potential reduction. The VTH variation rate for these devices shows to be better when compared to other technologies, presenting a variation around -0.64 mV/ºC for the p-type, and -0.4 mV/ºC for the n-type, while planar fully depleted SOI devices reach around -0.8 mV/ºC (3), junctionless FinFETs can achieve around -0.94 mV/ºC (4) and bulk nFinFETs present values around -0.67 mV/ºC for narrow fins and -0.92 mV/ºC for wide ones (5). It is possible to see that the subthreshold swing (SS) values (figure2) are very close to the theoretical limit for the MOS technology, except for 28nm channel length pMOS devices, indicating that pMOS is more susceptible to short channel effects (SCEs) than the nMOS counterpart. In figure 3, the Drain Induced Barrier Lowering (DIBL) degrades when the temperature increases. DIBL degradation for both n- and pMOS with temperature are very similar, showing a variation rate of 0.11 mV/V.ºC. It is also important to note that although DIBL is affected by the temperature, the obtained values (except for L=28nm) are very small reaching in the worst case 50mV/V at 200ºC. The transconductance (gmsat) and output conductance (gd) on saturation region of n-type and p-type, showed in figure 4, decreases with increased temperature mainly due to the carrier mobility degradation. Although the gd degradation for L=28nm occurs for both caused by the channel length modulation, the p-type device presents a higher degradation in all range of temperature due to the gate to channel electrostatic coupling as already observed in the SS behavior (figure 2). The intrinsic voltage gain (AV) does not change significantly with temperature due to the compensation between the gm degradation and gd improvement as shown in figure 4. Long p-channel devices present higher Av (gm/gd) than n-type GAA FETs due to the smaller values of gd which is not compensated by the gm degradation. However, for short devices the higher gd degradation results in smaller Av. As said before, AV is calculated considering gmsat and gd and both depend on the mobility, so it is possible to note that AV is barely affected by temperature. Other important highlight is the obtained AV values for the studied GAA MOSFETs that are very high considering other multiple gate MOSFET structures. Both nMOS and pMOS nanosheet devices, with channel length of 100 nm, reach around 42 dB and 50dB respectively, while for bulk FinFETs , junctionless SOI nanowires and W-gate SOI nanowires the values achieved are 34 dB (6), 37 dB (7) and 40 dB (8), respectively, for the same VGT and similar channel length. Even though the longest devices show better SCE immunity and higher AV values, the device with a channel length of 28 nm still shows a good performance. The GAA nanosheet achieves AV of 33 dB and 28 dB, for n and p-type, respectively, while triple gate SOI nanowires, with channel length of 40 nm, and W-gate SOI nanowires, with channel length of 20 nm, presents values around 27 dB (9) and 20 dB (10), respectively. Figure 1

As conventional CMOS scaling is reaching its physical limits with ever more constraining design restrictions, new device architectures are being explored as potential fin-field-effect-transistor (finFET) replacements for future technology nodes. Among the various options, vertically stacked lateral nanosheet (NS) FETs with a gate-all-around (GAA) configuration are considered the most promising and mature candidates to use next to help preserve the overall power-performance logic roadmap [1-5]. These devices offer improved electrostatics control and allow additional design flexibility for applications-driven power and performance tuning. Indeed, the possibility to fabricate on the same wafer varying NS widths, enabling devices with a wide range of effective widths (Weff), is one of their key attractive features. Wider GAA NS FETs enable higher drive current (ION) gains. However, as shown in ref. [2], these can be compromised for shrinking gate length (Lgate) due to degraded electrostatics, e.g., worst subthreshold slope (SS) values. As for narrower NS FETs, despite their lower ION, they also correspond to decreased channel, overlap and fringe capacitance values. In addition, as extension and contact resistances can also depend substantially on the NS cross-sectional areas [2], several trade-offs will ultimately determine the NS device configuration that best fulfills the requirements for a given application. Fabrication-wise, GAA lateral NS FET devices can be regarded as a natural extension of finFETs sharing many of their building blocks. Some of the key process steps are illustrated in Fig. 1, wherein Si/SiGe multi-layers are epitaxially grown prior to fin patterning to form vertically stacked silicon lateral NS. At replacement metal gate (RMG) module, prior to gate stack deposition, NS are released by implementing a selective removal of the SiGe from the Si/SiGe multi-layer fins. This is a key step, critical for preserving the integrity of the Si channels in terms of shape, dimensions and quality of the NS surfaces. Another crucial step occurs earlier on in the flow at STI module, where insertion of a thin nitride liner prior to STI oxide fill and densification anneal can prevent Si/SiGe fin oxidation and Ge diffusion. Such processing helps preserving the fins profile while also protecting them from irreversible strain modifications [4]. Fig. 2 shows an example of a TEM image from a device built with two vertically stacked NS. The well-preserved shape of the NS also enables implementation of a highly uniform and scaled gate stack on all NS surfaces with smooth interfaces [6]. This is of increased importance for scaled GAA NS FETs where reduced vertical distance between the stacked NS is required to minimize device parasitics. Another type of GAA NS transistors are the vertical NS (VNS) FETs for which Lgate is defined vertically and hence can be relaxed without impacting the device footprint. Representing a more disruptive technological transition, both in terms of device fabrication and circuit layout design, these devices have nevertheless the potential to open up new scaling paths and enable denser, better performing circuits, e.g., for SRAM (as the cell transistors) or MRAM (as the cell selector) memories [7,8]. Fig. 3 illustrates some of the key steps followed to implement an RMG module in GAA vertical nanowire (VNW) or VNS FETs. A layout dependence for some of the processes used in this block can be seen to impact DC characteristics such as VT, ION. The VNW/VNS doping vs. wire/sheet dimensions also needs to be accounted for in case of junctionless devices [8, 9]. RMG can also be used to enable a scheme that boosts the mobility in vertical channels via process-induced stress as described in Fig. 4 for NMOS. Here, a SiGe stressor is epitaxially grown around the Si channel after spacers formation. This stressor is removed at RMG module, after dummy gate removal, with stress memorization into its surroundings enabled by the fact that the layer encapsulating the top of the pillars remains connected (at some places) to the bottom isolation layer. Stress and ballistic current simulations indicate that up to ~19% higher ION can hence be obtained [8]. References [1] H. Mertens et al., VLSI Tech. Dig., 158 (2016). [2] D. Jang et al., IEEE Trans. Elec. Dev., 64(6), 2707 (2017). [3] N. Loubet et al., VLSI Tech. Dig., 230 (2017). [4] H. Mertens et al., IEDM Tech. Dig., 828 (2017). [5] P. Weckx et al., IEDM Tech. Dig., 505 (2017). [6] A. Veloso et al., SSDM Tech. Dig., 559 (2019). [7] T. Huynh-Bao et al., SPIE Proc., 978102 (2016). [8] A. Veloso et al., IEDM 2019 (in press). [9] A. Veloso et al., SSDM Tech. Dig., 221 (2017). Figure 1

Made available in DSpace on 2022-04-28T19:51:21Z (GMT). No. of bitstreams: 0 Previous issue date: 2022-05-01 In this work the gate-all-around nanosheet transistor is analyzed at high temperatures, from analog point of view. At first, the gate-all-around nanosheet (NS) behavior is compared with reported omega-gate nanowire (NW) transistors, at room temperature. It is worth noting that the nanosheets devices present a stronger electrostatic coupling between gate and channel (lower short channel effect -SCE), and higher intrinsic voltage gain, AV (better Early voltage) when compared with NW devices (60 dB for NS and 55 db for NW, with L = 200 nm). Therefore, the second part of this work focuses on the analog study only for NS transistors (with different metal gate stacks), presenting the trade-off between transistor efficiency and unit gain frequency, fT from room temperature to 200 °C. The obtained results are very promising for both gate stack transistors, where values of transistor efficiency about 37 V−1 (T = 25 °C and L = 200 nm) and fT about 260 GHz (T = 25 °C and L = 28 nm) are obtained. The optimal application point was obtained at the transition from moderate to strong inversion. LSI/PSI/USP University of Sao Paulo imec UNESP Sao Paulo State University UNESP Sao Paulo State University