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The problem of organizing the automation and computer technology combinational devices control with the diagnostic tools synthesized using redundant coding is considered. In contrast to the known approaches, a method is proposed for generating a uniform separable code, considering the structural features of the original combination devices. This method makes it possible to use data about possible errors at the outputs of the circuit in the code under construction and take this into account when synthesizing the control circuit. When setting the problem, a fault model is determined, relative to which the code will be built with the detection of all (or, possibly, part) errors at the circuit outputs. In contrast to the known redundant codes used to organize the combinational device’s control, the proposed method of generating a code makes it possible to consider the individual features of their structures. Such an approach in the self-checking combinational devices organization with an unchangeable design expands the number of ways to construct them compared to the previously known duplication and use of circuit outputs groups controlled by codes with unique diagnostic properties. [ABSTRACT FROM AUTHOR]

A method for constructing a family of sum codes is described based on weighting the transitions between groups of bits in the data vector. In this case, weights are used that are powers of the number 2. This makes it possible to obtain a code with check bits described by linear functions. The proposed weight-based sum code makes it possible to synthesize self-checking devices based on the standard elements and optimization methods of the logical device’s structures. A standard structure of a device with a concurrent error-detection (CED) circuit based on transitions weight-based sum codes between bits groups in the data vector is presented. The standard structure advantage lies in the possibility of synthesizing CED circuits with technical implementation reduced complexity by using codes with check bits numbers that are much smaller than the data bits numbers. Self-checking devices synthesized using the described codes in some cases may turn out to be less redundant than when using the standard duplication structure. The structure disadvantage is the need to consider the restrictions on the multiplicity of errors arising at the outputs of the diagnostic objects. This limitation increases with a decrease in the number of check bits. Despite this, in many cases, the use of a standard structure based on transitions weight-based sum code between groups of digits in the data vector makes it possible to synthesize self-checking digital devices. Using a standard structure for organizing a CED circuit allows going to implement of fault-tolerant digital devices according to standard structures, one of which is given in this article. [ABSTRACT FROM AUTHOR]

The article considers the construction of fault-tolerant digital devices and computing systems that does not use the principles of introducing modular redundancy. To correct the signals, a special distorted signal fixation unit, concurrent error-detection by the pre-selected redundant code circuit, as well as a signal correction block are used. The distorted signal fixation unit is implemented by the Boolean complement method, which makes it possible to design a large number of such blocks with different indicators of technical implementation complexity. When synthesizing a fault-tolerant device according to the proposed method, it is possible to organize a concurrent error-detection circuit for both the source device and the Boolean complement block in the structure of the distorted signal fixation unit. This makes it possible to choose among the variety of ways to implement fault-tolerant devices according to the proposed method, one that gives a device with the least structural redundancy. Various redundant codes can be used to organize concurrent error-detection circuits, including classical and modified sum codes. The author provides algorithms for the synthesis of distorted signal fixation unit and the Boolean complement block. The results of experimental researches with combinational benchmarks devices from the well-known LG’91 and MCNC Benchmarks sets are highlighted. The article presents the possibilities of the considered method for the organization of fault-tolerant digital devices and computing systems. [ABSTRACT FROM AUTHOR]

The presented paper is devoted to the development of the Boolean complement method for the organization of the self-checking concurrent error-detection (CED) systems for digital devices. The article considers the features of using the modular sum codes (Bose-Lin codes) for these purposes, especially the Bose-Lin code by the modulo M = 4. This code has two check bits and only four different check vectors, this makes it easier to use it in the organization of the selfchecking CED system. The article presents the block diagrams of the organization of the CED system by the method of Boolean complement to the considered modular sum code. The examples of the CED system synthesis by the Boolean complement method are given. The article defines the restrictions imposed on the CED systems synthesis procedure, and also forms an algorithm for synthesizing a self-checking CED systems by the method of the Boolean complement to the Bose-Lin code by the modulo M = 4. [ABSTRACT FROM AUTHOR]

Error correction circuit typical structures are described — majority and duplication structure with control by parity. A new structure of the correction circuit based on duplication with weighted-transitions sum code control is proposed. The code is constructed by weighting the transitions between the adjacent bits in data vectors, numbers from sequentially increasing powers of the number «two», starting from the zero degree. The specified code detects any errors in data vectors, except for errors associated with distortions of all data bits at the same time. The weighted sum code features allow it to be used in the synthesis of error detection circuits. An example of the correction circuit synthesis is given. The experiments results using control combinational circuits MCNC Benchmarks showed that the duplication structure with weighted-transitions sum code control in many cases allows one to obtain lower complexity indicators values of the correction circuits technical implementation than the known structure of majority correction. [ABSTRACT FROM AUTHOR]