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This paper proposes an efficient design of Hamming (11, 7) encoder utilising Full Swing-Gate Diffusion Input (FS-GDI) approach in 65 nm technology nano-size node. The proposed design of Hamming codes aims to improve the power and area efficiency through reducing of transistors count by employing power-efficient logic style. Encoding circuits of Hamming code (11, 7) and (7, 4) are designed using the various traditional and proposed approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity are employed as a metrics for evaluating the efficiency of the proposed designs of encoding circuits. The simulation experiments are executed utilising Cadence Virtuoso simulator package. These experiments revealed that the proposed designs of Hamming encoding circuits achieve delay time reduction by 50.91% and 20% for Hamming codes (7, 4) and (11, 7), respectively. Also, hardware (H/W) simplicity and area efficiency of the circuits are improved by 50% compared to CMOS-based circuits. From the results analysis, the proposed FS-GDI based Hamming encoding circuits achieve efficient power and delay optimising. Hence, the power consumption, delay and area in communications systems and DSP circuits due to encoding process are reduced. The whole performance of DSP circuits can be more power/area efficient. [ABSTRACT FROM AUTHOR]

A novel implementation of Block and Convolutional encoding circuits approach using Gate Input Diffusion-Full Swing (FS-GDI) and Complementary Metal Oxide Semiconductor (CMOS) logic styles has been presented. Performance analysis of the proposed encoding circuits has been performed using Cadence Virtuoso (CV) S/W package. The performance metrics of FS-GDI-based encoding circuits have been compared with traditional CMOS-based designs. The proposed encoding circuits involve Block Hamming (15, 11), Convolutional (2, 1, 3), and Recursive Systematic Convolutional (2, 1, 2) encoding circuits; these presented circuits are simulated and tested using a word length of 11 bits. The simulation experiments revealed that the proposed implemented circuits achieve delay time improving by 27.91% and 33.27% for Hamming (15, 11) and Convolutional (2, 1, 3) codes, respectively. The simple proposed RSC encoder performs better than the Convolutional (2, 1, 3) due to shorter constraint length and less H/W complexity. On the other hand, the Transistor Count-Hardware (TC-H/W) is enhanced by 50% for the Block and Convolutional encoding based on employing area-efficient FS-GDI-XOR gate. From the analysis of the results, the proposed designs achieve efficient power and delay optimization of Hamming and Convolutional encoding utilizing the FS-GDI logic style. Also, it is clear that the characteristics of the proposed encoding circuits are vital and effective in the digital signal processing circuits and encoding/decoding schemes implementation in low-power wireless networks. [ABSTRACT FROM AUTHOR]